JPH0330301B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stacked semiconductor integrated circuit device constructed by stacking a plurality of semiconductor layers with an insulating layer in between, in which elements including field effect transistors (FETs) are integrated.

The most prominent of the circuits that include N-channel and P-channel devices are complementary circuits. Figure 1 shows one example of this, a three-input CMOS NOR circuit.
6 MOSFETs - T ₁ , T ₂ , T ₃ and T ₁ ′, T ₂ ′,
T ₃ ' is opened and closed by three input signals V ₁ , V _{2 and} V ₃ . T ₁ , T ₂ , T ₃ are N channels, T ₁ ′, T ₂ ′,
T ₃ ′ is a P channel, so when T ₁ , T ₂ , and T ₃ are open, T ₁ ′, T ₂ ′, and T ₃ ′ are closed, and when T ₁ ′, T ₂ ′, and T ₃ ′ are open, In this case, T ₁ , T ₂ , and T ₃ are closed, and no DC current flows from V _DD to Vss except at the moment of state transition. In other words, power consumption is extremely low, and in the future LSI
This circuit method becomes increasingly important as the scale of the system increases.

Conventionally, to build such a circuit, elements were arranged in a plane on the surface of a semiconductor such as Si. Second
The figure is an example of the layout of the 3-input CMOS NOR circuit shown in Figure 1 on the surface of a Si crystal. Both the N-channel MOSFET elements and the P-channel MOSFET elements are all arranged on the same plane, so a special method called a P-well is used to isolate the two types of elements. That is, a limited P-type region is created on an N-type Si crystal and is called a P-well. N-channel MOSFET-T ₁ to _{T 3} are fabricated in the P-well, and P-channel MOSFET-T ₁ ′ to _{T 3} ′ are fabricated on the original N-type Si surface. The reverse separation method is also possible; an N-well may be formed on the P-type Si surface, a P-channel element may be formed inside the N-well, and an N-channel element may be formed outside the N-well.

Such conventional integrated circuits have the following drawbacks. First, it consumes a large amount of Si surface area. Second, since many input lines are placed on the same plane, long wiring is required between them and the output section of the preceding circuit. That is, the input is 1
In the case of a book, the preceding stage circuit and the main circuit can be placed in close proximity, but if there are multiple inputs, there will also be multiple preceding stage circuits, and of course they cannot be placed closely together. Inevitably, the wiring becomes long, and it is simply
This not only consumes a large amount of Si surface area, but also causes delays in signal propagation.

Although the explanation is given using a CMOS circuit as an example, it is also possible to use only N-channel FET or P-channel FET.
The same situation applies to circuits made up only of FETs.

In view of the above points, the present invention aims at high density by stacking a plurality of semiconductor layers in which elements including FETs are integrated with an insulating layer in between, and stacking them vertically.
By arranging FETs in a predetermined relationship, the wiring length can be shortened to reduce delay in signal propagation, thereby providing a stacked semiconductor integrated circuit device that can achieve high performance.

That is, the present invention basically consists of three-dimensionally configuring a circuit by stacking semiconductor layers one above the other with an insulating layer in between. Although this basic configuration is already a conventional concept, the feature of the present invention is that the N-channel
FETs consist of N-channel FETs, and P-channel FETs consist of stacking P-channel FETs one above the other. In this case, the top and bottom overlap
It is preferable to set the element arrangement such that the FET overlaps the source, the drain region overlaps the source, the drain regions overlap each other, and the gate regions overlap each other. This allows the source or drain region,
Alternatively, it is possible to obtain the feature that both can be directly connected vertically.

The present invention provides the following advantages.

First, the area consumed on the substrate surface is greatly reduced, allowing for higher density integrated circuits.

Second, since contact between the upper and lower semiconductor layers is made in the same type of layer, crystal mismatch is small, a high-quality single crystal layer can be obtained, and a high-performance device can be formed.

Thirdly, when forming the upper layer using a part of the lower layer as a seed crystal, the single crystal region to be controlled by the seed crystal is relatively narrow, and single crystallization can be achieved easily, resulting in a high yield as an LSI. Become.

Fourth, when constructing a multi-input NOR circuit, each input can be provided on a different layer, making wiring with the previous stage circuit block easy, and shortening the wiring length to reduce signal propagation delays. It can be made smaller, the area is smaller, and the operating speed of the circuit is higher.

As shown in Figure 5, output lines and power lines can also be installed on the desired layer.

Sixthly, when configuring a memory array, for example, according to the present invention, each memory cell can be stacked vertically, and bit lines can be passed vertically, so a large number of outputs can be extracted. can. This point will be extremely useful for future computers that will be required to read a large number of memory contents at once.

Examples of the present invention will be described below.

(1) CMOS NOR circuit Figure 3 shows the 3-input circuit shown in Figure 1 based on the present invention.
This figure shows a schematic configuration of an example in which a CMOS NOR circuit is configured. The insulating layer is omitted for clarity. The semiconductor layer has a stacked structure of three layers, and the three layers of FET on the left
-T ₁ , T ₂ , and T ₃ are N-channel MOSFETs.
These three FETs have wiring layers 1, 2, 3, and 4 above and below on both the source side (inside) and drain side (front).
from the source side of the top layer.
The Vss power line is taken out. 3 on the right
The layer FETs - T ₁ ′, T ₂ ′, T ₃ ′ are P channels.
In a MOSFET, the bottom layer has the source on the front, the middle layer has the source on the inside, and the top layer has the source on the front, and the drain on the bottom layer and the source on the middle layer, and the drain on the middle layer and the source on the top layer are wired, respectively. The layers 5 and 6 are connected vertically. The V _DD power supply line is taken out from the drain side of the top layer. N channel side is also P
The channel side is also characterized by layers of the same conductivity type stacked one above the other. The N channel side and the P channel side are connected at the bottom layer.
That is, the drain of the N-channel MOSFET-T ₃ in the lowest layer and the source of the P-channel MOSFET-T ₃ are connected by the wiring layer 7.

Inputs V ₁ , V ₂ , and V ₃ are distributed to each layer and connected to the gates of T ₁ and T ₁ ′, T ₂ and T ₂ ′, and T ₃ and T ₃ ′, respectively. The output part V ₀ is taken out from the drain of the N-channel MOSFET-T ₂ in the intermediate layer, but it can be taken out from the top layer or the bottom layer as required. It is also possible to place the Vss line not on the top layer but on the middle layer or the bottom layer.

According to this embodiment, compared to the conventional example shown in FIG. 2, when the same design criteria are used, the area occupied by the Si surface is reduced to 1/2 or less. This effect is even greater when the number of inputs is large, and accordingly, the wiring becomes shorter and the signal transmission time decreases in proportion to the square root of the area, making it possible to achieve higher speeds.

FIG. 4 shows a part of the specific cross-sectional structure of the above embodiment. N-channel MOSFET
are stacked with the source, drain, and gate aligned. Insulating layer 8 is, for example, SiO ₂ . The sources and drains are connected vertically by wiring layers 1 to 4, and these portions are used as seed crystals to sequentially form Si single crystal layers in which FETs of each layer are to be formed. Since a layer of the same conductivity type as the seed portion is first grown, the growth is easy and there are advantages in that it is easy to obtain high-quality crystals. Furthermore, since the region to be controlled by one seed crystal is only an extremely narrow range, single crystallization is easy and the yield as an IC is greatly improved. However, since the channel section under the gate is slightly away from the seeds, it is easy to control the threshold voltage.

A NAND circuit can also be easily constructed in the same manner as in the above embodiment.

(2) Address Decoder Circuit FIG. 5 is a schematic diagram of an embodiment of a four-input address decoder circuit according to the present invention. The circuit has a stacked structure of eight semiconductor layers. Each of NOR ₁ , NOR ₂ , NOR ₃ , . . . is a 4-input NOR circuit, and if it is constructed of CMOS, for example, it will have a structure in which one layer is stacked on top of the other in FIG. 3 of the embodiment (1). However, in the case of this embodiment, in selected four layers among the eight layers,
FET is formed and other layers are empty.

A ₁ , A ₂ , A ₃ , A ₄ are address inputs, ₁ ,
A ₂ , ₃ , _{and 4} are the opposite. These 8 are 8
distributed to each layer, NOR ₁ , NOR ₂ ,…
are connected to the gates of the corresponding layers, except for vacant positions. For example, if you decide that NOR ₁ outputs 1 when the address (A ₁ , A ₂ , A ₃ , A ₄ ) is (0, 0, 0, 0),
NOR ₁ has four layers corresponding to A ₁ , A ₂ , A ₃ , and A ₄
It has an FET, and the corresponding positions in the other four layers are vacant. Next, if we decide that NOR ₂ will output 1 at address (0, 0, 0, 1), NOR ₂ will output A ₁ , A ₂ , A ₃ , ₄
It has FETs in four layers corresponding to , and the corresponding positions in other layers are vacant. The structures of NOR ₃ , NOR ₄ , . . . are determined in the same manner.

As shown in FIG. 3 of the previous embodiment (1), each NOR circuit has a stack of driver FETs on the left side, so its sources and drains are connected vertically. Therefore, output can be extracted from any hierarchy. In FIG. 5, the front side is the drain side of the driver FET, and the case where outputs O ₁ , O ₂ , . . . are taken out from all layers is shown.

This embodiment also provides effects such as a reduction in substrate area, faster signal propagation, and improved circuit characteristics and yield due to high-quality crystal growth.

(3) CMOS static memory circuit FIG. 6 is a schematic diagram of an embodiment configuring a CMOS static memory based on the present invention.

(m, n) (m=1, 2,...; n=1, 2,
) represents a memory cell, (1, n), (2,
n), ... are overlapped one above the other. Wm (m=1,
2,...) are word lines, _W1 is the top layer, _W2 is the next layer, and so on.
Bn, (n = 1, 2, ...) are bit lines, and memory cells (1, n), (2, n) overlapped above and below.
It is connected to the input/output section of... V _DD is the High side electric wire, and Vss is the Low side power supply line. A feature is that V _DD and Vss are also connected to memory cells stacked one above the other.

Inside the memory cell, there is one transfer gate MOSFET on each end of the CMOS flip-flop.
It is a so-called static memory cell with T ₁₃ and T ₁₄ attached. T ₁₁ , T ₁₂ , T ₁₃ , T ₁₄ are N-channel MOSFETs, T ₁₁ ′, T ₁₂ ′ are P-channel MOSFETs
It is a MOSFET. In FIG. 6, each FET is shown by a symbol, and structurally, FETs represented by the same symbol are arranged so as to exactly overlap one another. For example, T ₁₁ is in cell (1, n), in cell (2, n), and in cell (m,
The items in n) are all layered,
Furthermore, drain regions overlap each other, source regions overlap each other, and gate regions overlap each other. What's more, each FET is unique in that it is connected vertically at either the source or drain end.

According to this example, since the upper and lower layers are connected by the same conductivity type layer, it is easy to make the upper single crystal layer with good quality by using the connection part with the lower layer as a seed crystal. Since one end of the FET is always above the seed crystal in the lower layer, the single crystallization rate is good and the carrier mobility is high. Further, the bit lines can be made extremely short, and the signal propagation delay due to the wiring can be made extremely small, making it possible to shorten the access time as a memory. Further, by expanding this structure laterally and arranging a large number of memory cells, a large number of bit lines can be taken out. This point is similar to associative memory, etc.
It is extremely useful for applications that require reading out a large number of memory contents at once, and for image information processing.

In the above embodiments, CMOS circuits have been taken up, but the present invention can be similarly applied to N-channel MOS and P-channel MOS circuits. Also, the FET
It can be applied not only to MOSFETs but also to MESFETs.

In addition, in the above memory circuit embodiment, the static
RAM is shown, but in the same way, dynamic
RAM and ROM can also be configured in the same way, and similar effects can be achieved.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a CMOS NOR circuit, Figure 2 is a layout diagram of this CMOS NOR circuit integrated on a Si substrate, and Figure 3 is also a diagram of this CMOS NOR circuit.
A diagram showing a schematic configuration of an embodiment of the present invention in which CMOS NOR circuits are three-dimensionally integrated, FIG. 4 is a diagram showing a cross-sectional structure of a part thereof, and FIG. 5 is an application of the present invention to an address decoder. FIG. 6 is a diagram showing a schematic structure of an embodiment in which the present invention is applied to a CMOS static memory. T ₁ , T ₂ , T ₃ ... N-channel MOSFET, T ₁ ',
T ₂ ′, T ₃ ′……P channel MOSFET, ,,
... Semiconductor layer, 1 to 7 ... Wiring layer, 8 ... Insulating layer, T ₁₁ , T ₁₂ , T ₁₃ , T ₁₄ ... N channel
MOSFET, T ₁₁ ', T ₁₂ '...P channel
MOSFET, (1, n), (2, n), ... (m, n)
...Memory cell.

Claims (1)

[Scope of Claims] 1 A semiconductor layer in which memory cells each consisting of a plurality of field effect transistors are integrated is stacked in multiple layers with an insulating layer in between, and the memory cells that overlap each other are arranged in respective device regions. are arranged so as to overlap each other, and signal wires connecting corresponding terminals of memory cells that overlap above and below are arranged vertically penetrating the stack of semiconductor layers and insulating layers. Stacked semiconductor integrated circuit device.