JPH0330955B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an address buffer circuit in a dynamic RAM (random access memory), and in particular, the present invention relates to an address buffer circuit in a dynamic RAM (random access memory). The present invention relates to an address buffer circuit that has the function of selecting information.

[Prior art]

Generally, as is well known, written data in dynamic RAM disappears after a certain period of time even when the power is turned on, so it is necessary to periodically refresh the data and rewrite the memory cells.
Therefore, external refresh control is required. At this point the static RAM
The timing control becomes more complicated than that.

Therefore, in recent years, in order to avoid this complexity, a refresh address counter is built into the memory circuit, and when refresh information is received, a function is created to select addresses one after another to complete the refresh, and a refresh timer is also built in. A method has been adopted in which a function is provided to automatically repeat the refresh once every certain period of time. In other words, by performing refresh control, which was previously performed externally, inside the memory circuit, external timing control is simplified and static
It has become possible to use it in a form similar to RAM.

In this method, it is necessary to provide an internal refresh counter, and therefore, apart from external address information (row and column address information),
It is necessary to take in refresh address information generated internally through an address buffer.

Conventionally, the address buffer circuit in this type of memory circuit includes a preamplifier 10 and a main amplifier 11 for amplifying external address information, and a preamplifier 12 and a main amplifier 13 for amplifying internal address information, as shown in FIG. , and a signal selection circuit 14 that selects the output from the main amplifiers 11 and 13, inputs external address information and internal address information to the respective preamplifiers 10 and 12, and further selects the output from the main amplifier 1.
1 and 13, and one of them is selected by the selection circuit 14 and output.

[Problem that the invention seeks to solve]

In the conventional address buffer circuit described above, an amplifier circuit (10, 1
1) and internal address amplifier circuit (12, 13)
Since the configuration is a combination of the two, there are essentially two sets of amplifier circuits (10, 11) and (12, 13), which has the drawback of requiring a large area on the semiconductor chip.

[Means for solving problems]

In order to reduce the area occupied on a semiconductor chip, the address buffer circuit according to the present invention has the following features:
A preamplifier receives and amplifies address information input from the outside (row address and column address information), and a preamplifier receives and amplifies address information generated inside the circuit (refresh address count information). , a signal selection circuit that receives the outputs of the two preamplifiers and selects one of the address information, and a main amplifier that amplifies and outputs the selected information.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This address buffer circuit is composed of an external address information preamplifier 1, an internal address information preamplifier 2, a signal selection circuit 3, and a main amplifier 4. External address information and internal address information are first stored in each preamplifier 1,
2 to obtain O ₁ and O ₂ . The output information O ₁ and O ₂ are input to the signal selection circuit 3. This selection circuit 3 outputs O 1 , O ₁ in response to control signals S ₁ and S ₂ .
Select one of _O2 and output the selection information as output _O3 . This is input to the main amplifier 4.
Information via the main amplifier 4 is output as required address information. In other words, it is output from this address buffer circuit. The signal selection circuit 3 includes, for example, two control signals S1 and S2.
The internal address information is selected and output.

FIG. 2 shows the input/output timing of this address buffer circuit. Now, suppose that the outputs O ₁ and O ₂ of the preamplifiers 1 and 2 shown in FIG. 1 are simultaneously input to the selection circuit 3 as shown in FIG. 2 a and b. As shown in FIG. 2c, when the first control signal S ₁ is first input to the signal selection circuit 3, external address information (O ₁ ) is input to the main amplifier 4 at time t ₁ . At this time, the internal address information (O ₂ ) is the signal S
2, it is in a non-selected state and internal address information is not transmitted to the main amplifier 4. Next, at time _t2 , both control signal waveforms S1 and S2 become non-selected, and information transmission ends. Thereafter, the control signal waveform S2 for taking in internal address information becomes a selected state at time _t3 , and the internal address information is transmitted to the main amplifier 4, and thereafter address information transmission ends at time _t4 in the same manner.

〔Effect of the invention〕

As explained above, the present invention does not input the preamplifier output that amplified external address information and the preamplifier output that amplified internal address information directly to the main amplifier, but inserts a signal selection circuit between them, and selects either one of each information. Select the main
The input is input to the amplifier, and therefore the address buffer circuit with the same function as the conventional one is realized with a smaller circuit configuration than the conventional one (conventionally, there were two main amplifiers, and the present invention has one main amplifier). There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is an input/output timing diagram of FIG. 1, and FIG. 3 is a block diagram showing a conventional example.

Claims (1)

[Claims] 1. A first preamplifier that receives address information input from the outside and amplifies it, a second preamplifier that receives address information generated internally and amplifies it, and outputs of the first and second preamplifiers. 1. A semiconductor memory device comprising: a signal selection circuit that selects and outputs one of the signals received; and an address buffer circuit that includes a main amplifier that amplifies and outputs the selected information.