JPH0331015B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a frequency division method, and more particularly to a frequency division method for obtaining a frequency divided waveform having a required duty cycle using a hexadecimal counting circuit. In recent years, counting circuits have been widely used as frequency dividing systems, and of course they are applied to devices that use digital signals, especially electronic computers. Attempts have been made in the past to divide the frequency of the clock signal that controls digital signals. For example, if an attempt was made to divide the frequency of an input clock to 1/10, the frequency could be divided using a circuit like the one shown in Figure 1. We do the rounds.
That is, the clock is input to the decimal counting circuit 1, the signals output from each bit of the decimal counting circuit 1 are input to the decoding circuit 2, and the discontinuation results are displayed at the output terminals #0 to #9 of the decoding circuit 2, respectively. The required output terminals #3 and #9 are input to the K and J terminals of the flip-flop circuit 3, respectively, and a clock signal is also input to the flip-flop circuit 3. Needless to say, the flip-flop circuit 3 is set and reset by the signals at the #9 and #3 output terminals, respectively. Therefore, #9 to #2-4
The flip-flop circuit 3 outputs six period "off" signals of period "on"#3 to #8, and the frequency of the clock signal is divided by 1/10 of the duty cycle 4/6. The terminal input to the flip-flop is changed and connected according to the required duty cycle.
The above is the conventional frequency division method. However, when this method is applied to an electronic computer using a hexadecimal counting circuit, the disadvantage is that providing a decimal counting circuit and a decoding circuit increases the number of circuits and costs. The present invention has been made in view of the above drawbacks, and an object of the present invention is to provide a frequency division method that can perform frequency division at low cost without increasing the number of circuits. To briefly explain the present invention, an AND circuit is attached to the output terminal of a hexadecimal counting circuit, and using the required output terminal, the output of the AND circuit divides the output of the hexadecimal counting circuit with a required duty cycle. It is characterized by having a waveform. Preferred specific examples for carrying out the present invention will be described in detail below with reference to the drawings. FIG. 2 is a block diagram showing the duty cycle 7/3 frequency division method of the present invention, in which 5 is a hexadecimal counting circuit, 6 is an AND circuit, and 7 is an inverter circuit. With such a configuration, when the hexadecimal counting circuit 5 generates a clock frequency divided by 10 signal with the required duty cycle, as shown in Table 1.
Controls the hexadecimal counting circuit 5. In Table 1, each row shows the conditions for obtaining a 10-frequency divided signal with various duty cycles,
"Duty cycle" column is u/(10-u)
Indicates the duty cycle of duty period u in the form of ``input condition'' column indicates the count value j that is forcibly set by the preset of the hexadecimal counting circuit 5, and the ``counting circuit operation'' column indicates the duty cycle of duty period u. is hexadecimal counting circuit 5
The rightmost value indicating the maximum value of the counting range is the count value i to be detected as the preset time point. Now, to explain the values in Table 1, taking the case of a duty cycle of 4/6 as an example, 10
Since this is frequency division, m=10, and first the highest significant digit of the binary number representing m or a higher order digit is selected. Since this is a hexadecimal counting circuit, the only digit that meets this condition is the "8" digit, and the digit value d=8.
Choose. Next, based on d=8, the counting range for obtaining a signal with the required frequency division ratio of the required duty cycle is determined. First, in order to obtain the duty cycle 4/6, that is, the duty period u = 4 clock length. Then, calculate the value 11 by counting 4 clocks from d=8 to determine the preset time point i=
11. That is, i is determined as d+u-1. Next, the count value j to be preset is i-m+1+n
is calculated as the remainder when divided by n (however, the counting circuit is an n-ary counting circuit), and j=2 is determined. Therefore, the hexadecimal counting circuit 5 is controlled to repeat counting from j to i, that is, from 2 to 11 in this example, and as a result, as will be described later, the hexadecimal counting circuit 5 d= in binary output of 5
Obtain a signal output divided by 10 with a duty cycle of 4/6 at the 8th digit. In the case of other duty cycles, i and j can be determined in the same way from the value of the required duty period u using d as a reference. Next, the operation will be described in the case where a signal with a duty cycle of 7/3 divided by 10 is obtained.

[Table] In other words, when trying to create the duty cycle 7/3 marked with * in Table 1, the hexadecimal counting circuit 5 is set to 10.
When the hexadecimal counting circuit 5 counts up to 14, input "5" to the preset input and change it to 14.
Next, set the input conditions to count sequentially from 5 to 14. The output terminals 1 to 4th bits of the hexadecimal counting circuit 5 in FIG.
Among B, C, and D, B, C, and D terminals, that is, 2, 4, and 8
The hexadecimal value is input to the AND circuit 6.
The AND circuit 6 outputs “1” and the inverter circuit 7
, and inputs "0" to the E terminal of the hexadecimal counting circuit 5. The E terminal is a load terminal of the hexadecimal counting circuit 5, and operates to set a preset input signal when it is "0". Therefore, the output "1" of the AND circuit 6 sets the A and C terminals, that is, 5, and it operates as a decimal counting system from 5 to 14 mentioned above. The above operation is shown in FIG. As shown in FIG. 3, the D terminal output signal becomes "1" for 7 clocks between 8 and 14 counts. As a result, the duty cycle is 7/3.
A frequency division of 1/10 will be obtained. FIG. 4 is a block diagram for outputting a duty cycle of 5/5. Although the above explanation has been made regarding frequency division by 1/10, it goes without saying that any frequency division can be used without any problem. As is clear from the above explanation, the present invention provides a frequency division method that can be created at low cost by simply using an easily available AND circuit without increasing the number of circuits.
If the present invention is applied to an electronic computer system that requires frequency division, it will have many advantages in manufacturing.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional frequency division method, Fig. 2 is a block diagram of an embodiment showing a duty cycle 7/3 frequency division method of the present invention, and Fig. 3 is a time chart diagram of the present invention. , FIG. 4 is a block diagram showing the duty cycle 5/5 frequency division method of the present invention. In the figure, 5 indicates a hexadecimal counting circuit, and 6 indicates an AND circuit.

Claims (1)

[Claims] 1. Input a clock and calculate m of the period of the clock.
An n-ary counting circuit having a binary display counting output and counting the clock when outputting a frequency-divided signal having a duty cycle with a duty period that is u times the period of the clock. (however, n>m), the counting output is i
(However, when d is the highest significant digit of the binary number representing m or the value of the digits determined from the upper digits, i = d +
u-1) and count value j (however, j
(remainder obtained by dividing i-m+1+n by n) is preset in the n-ary counting circuit, and the count output of the n-ary counting circuit corresponding to the digit of the value d is taken out as the frequency division signal. Method.