JPH0331205B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a weight measuring device that measures weight by converting an analog weight signal into a digital signal.

Currently, various weight measuring devices have been developed.
Widely used. By the way, many weight measuring devices have a built-in analog-to-digital converter (hereinafter referred to as an A-D converter) that converts an analog weight signal into a digital signal. Many of them are integral type. However, 2
Since the double integral type A-D converter has a counting error, the triple integral type A-D converter is used as a means to solve this problem.
A transducer was previously developed. FIG. 1 is a waveform diagram showing the output waveform of the integrator in this triple integration type AD converter. As shown in this figure, triple integral type A
In the -D conversion, first, the analog weight signal is integrated from time 0 to _t1 (predetermined time), and the reference voltage is integrated from time _t1 to _t3 . Also, from time t ₁ , ○
Counting of the integration time is started based on the clock signal as indicated by the numbers in . By the way, the time
At t ₂ , the integrated output waveform crosses 0, but this 0 crossing is detected at the next rising edge of the clock, and the count result for the period (t ₁ - t ₂ ) is "4".
becomes. However, the count result for the period (t ₁ - t ₂ ) must be "3.5" as shown in the figure, and this error is caused by the double integral (period (0 - t 2 )) mentioned above.
This occurs in the integral of t ₂ ). Now, in triple integration, after integrating the reference voltage until time t ₃ , the slope of the integrated waveform is set to 1/10 of the previous period (t ₁ − _{t 3} ) (however, the sign is reversed) Then, integrate to the next 0 cross point. Then, from time t ₃ to time t ₄ which is the 0 cross point
time until. The count result during this period is "5" as shown in the figure, and this result and the period (t ₁ -
From the count result "4" of _t3 ), for example, 4-
Perform the calculation 0.5=3.5 to obtain the correct count value (time measurement result) of 3.5 for the period (t ₁ −t ₂ ).

By the way, in the weight measuring device using the above-mentioned triple integral type A-D converter, the voltage at the starting point of the third integral (voltage at time _t3 ) is small;
Because the slope of the integral is small, the integrator output waveform approaches the 0 level from a small initial value very gently, and for this reason, the comparator that detects the 0 cross of the integrator output must be an expensive, high-precision comparator. ,0
There was a problem that the cross time could not be detected accurately. Another drawback is that it takes a long integration time, ie, A/D conversion time.

In view of the above-mentioned circumstances, the present invention provides a weight measuring device that does not require an expensive high-precision comparator and has a short integration time. A time-measuring integration period in which the reference power source is integrated at a predetermined slope until the integrated output crosses the 0 level as it is reversed, and this integration period is clocked by a predetermined clock; and after the integrated output crosses the 0 level, the clock is m ⁿ times the above slope until timing (m, n are integers)
a high-speed integration period in which the reference power source is integrated with a slope of and a corrected time-integration period for integrating with a slope having the same absolute value and measuring this period by the clock; conversion means for converting the analog weight signal into a digital signal, and the switching integration means converts the operation of the high-speed integration period and the corrected time-keeping integration period after the operation of the timekeeping integration period following the input integration period is completed. is configured to be performed one or more times.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

In this figure, SW ₀ to _{SW 3} are analog switches, which are controlled on and off by the control circuit 3. LD is a load cell, and its output signal is amplified by amplifier AMP, and the output voltage Vx (analog weight signal) of this amplifier AMP is
is supplied to terminal a of analog switch _SW0 .
1 is an operational amplifier, with a capacitor C ₁ and a resistor R ₁
(value r ₁ ) and resistor R ₂ (value r ₁ /9), integrating circuit A
It consists of In this case, the analog switch
When SW ₁ is turned ON, resistors R ₁ and R ₂ are connected in parallel, and the time constant of the integrating circuit A is changed from r ₁ C ₁ to r ₁ C ₁ /10, that is, 1/10. _R3 to _R6 are resistors connected in series, and a constant voltage V _R is supplied to one end of the resistor _R3 ,
One end of resistor _R6 is grounded. This resistance R ₃ ~
R ₆ creates three types of reference voltages by dividing the constant voltage V _R. The reference voltage Va is from the connection point of resistors R ₃ and R ₄ , and the reference voltage is from the connection point of resistors R ₄ and R ₅ . Voltage Vc
However, from the connection point of resistors R ₅ and R ₆ , the reference voltage Va/10
are output respectively. In this case, the reference voltage Vc and the output voltage Vx of the amplifier AMP have a relationship of Vx<Vc. The reference voltage Va is supplied to terminal b of the analog switch SW ₀ via the analog switch SW ₂ ,
The reference voltage Vc is supplied to the non-inverting input terminal of the operational amplifier 1 and one input terminal of the comparator 2, and the reference voltage Va/10 is supplied via the analog switch SW ₃ .
Supplied to terminal b of SW ₀ . Comparator 2 compares the output voltage e of integrating circuit A with reference voltage Vc, and determines that e>
When e<Vc, an "H" level signal is supplied to the control circuit 3, and when e<Vc, an "L" level signal is supplied to the control circuit 3. A clock generating circuit 4 generates a clock signal CLK and supplies it to the control circuit 3. Reference numeral 5 denotes a count calculation circuit that performs counting and correction calculations for the integration period, and details of the aforementioned control circuit 3 of this count calculation circuit 5 will be described later.

Next, the operation of this embodiment with the above-described configuration will be explained with reference to FIGS. 2 and 3. In addition, the third
This figure is a waveform diagram showing the output signal waveform of the integrating circuit A shown in FIG. 2, and corresponds to FIG. 1.

First, control circuit 3 is an analog switch.
Set SW ₀ to terminal a side, and connect other analog switch SW ₁
~Turn SW ₃ OFF. As a result, the integrating circuit A integrates the voltage Vx as shown in period T ₁ (input integration period) in FIG. In this case, the time width of period _T1 is set in advance, and the control circuit 3
has a time width that counts a predetermined number of clock CLKs. Further, the output voltage e of the integrating circuit A during this period _T1 is expressed by the following equation when the reference voltage Vc is set to 0 level.

e=1/C ₁ r ₁ ∫ ₀ ^t Vxdt ...(1) Then, when period T ₁ ends at time t ₁ ,
Control circuit 3 sets analog switch SW ₀ to terminal b side and turns SW ₂ ON (SW ₁ and SW ₃ are
OFF). As a result, the integrator circuit A operates during the period T ₂ in FIG.
As shown in (timekeeping integration period), the direction of integration is reversed and the reference voltage Va is integrated, and the count calculation circuit 5 counts this period _T2 based on the clock CLK (circle in Figure 3). (see numerical values). The output voltage e of the integrating circuit A during this period _T2 is expressed by the following equation.

e=-1/C ₁ r ₁ ∫ ₀ ^t Vadt+ex ...(2) (however, e _x is the value of e at time t ₁ ) Then, when the output voltage e crosses the 0 level at time t ₂ , the comparator The output signal of 2 is inverted. When the output signal of comparator 2 is inverted, control circuit 3 turns on analog switch SW ₁ (at this time, only SW ₃ is OFF). As a result, the time constant of the integrating circuit A becomes 1/10, and the time constant of the integrating circuit A becomes 1/10.
Integrate the reference voltage Va at high speed as shown in T ₃ (high speed integration period). The output voltage e during this period _T3 is expressed by the following equation.

e=-10/C ₁ r ₁ ∫ ₀ ^t Vadt...(3) In this embodiment, this period _T3 is the period from when the output signal of comparator 2 is inverted until the next clock CLK.
This is the period until the rise of the control circuit 3.
When the next clock CLK is supplied at time _t3 , analog switch SW ₂ is turned OFF, SW ₃ is turned ON (SW ₁ remains ON), and high-speed integration is stopped.
On the other hand, the count calculation circuit 5 learns of the inversion of the output signal of the comparator 2 at time _t3 , and ends counting for the period _T2 at this point, as in the conventional case described above. Therefore, the count result for period T ₂ is "4"
(The correct value is "3.5" as shown in the figure). Then, the count calculation circuit 5 stores this count result "4". Then, at time t ₃ , analog switches SW ₁ and SW ₃ are turned on, and SW ₂ is turned on.
When turned off, the integrating circuit A starts integrating the reference voltage Va/10. Since this reference voltage Va/10 is negative with respect to the reference voltage Vc as shown in Fig. 2,
Integrating circuit A reverses the integration direction and sets the reference voltage Va/
10 (period T ₄ (corrected timekeeping integration period) in FIG. 3) Also, the count calculation circuit 5 starts counting again from time t ₃ . The output voltage e during this period _T4 is expressed by the following equation.

e=10/C ₁ r ₁ ∫ ₀ ^t Va/10dt = 1/C ₁ r ₁ ∫ ₀ ^t Vadt ……(4) The right-hand side of this equation (4) is the sign of the right-hand side of the above-mentioned equation (1) reversed. Therefore, the slope of the integral in period T ₄ is the inversion of the slope in period T ₂ . That is, the absolute values of the slopes of the integrals in periods T ₂ and T ₄ are equal. In this manner, in this embodiment, the slope (absolute value) of the corrected timekeeping integration period _T4 is a predetermined slope. Therefore, the slope of the corrected timekeeping integration period _T4 is larger than that of the prior art described above. And the time
When the output voltage e of the integrating circuit A crosses the 0 level again at _t4 , the output signal of the comparator 2 is inverted. When the output signal of the comparator 2 is inverted, the count calculation circuit 5 finishes the counting operation and stores the count result (in this case, "5" as shown in the figure). Next, the count calculation circuit 5 performs the calculation shown below.

10・CT ₂ − CT ₄ ...(5) (However, CT ₂ and CT ₄ are counts and results in periods T ₂ and T ₄ , respectively) In this case, CT ₂ = 4 and CT ₄ = 5, so (5 ) formula is "35", and after aligning the decimal point position, the correct period width of period T ₂ is "3.5"
I understand that it corresponds to counting. Then, the count calculation circuit 5 converts the calculation result "35" into a digital signal and outputs it to an external circuit.

In this embodiment, the high-speed integration period starts after the output signal of the comparator 2 is inverted and then the next clock signal is inverted.
CLK is supplied, but this high-speed integration period may be made a little longer, for example, from the time when the output signal of the comparator 2 is inverted until the next clock CLK is supplied. However, the calculation operation of the count calculation circuit 5 in this case is not based on the above equation (5) but according to the following equation.

10・CT ₂ −(CT ₄ +10)... (6) Also, in this embodiment, in the period T ₄ shown in FIG. 3, the integrated output waveform approaches the 0 level from a large initial value with a relatively large slope. So,
0 even if comparator 2 is not particularly highly accurate.
Cross time can be detected accurately. On the other hand, if the input integration period T ₁ is reduced to about 1/10, time t ₃
Although the integrated output voltage becomes smaller, this method may be used if the A-D conversion accuracy is sufficient as in the conventional method described above. In this case, there is an advantage that the conversion time is shortened.

In addition, in this embodiment, the case of quadruple integration is taken as an example, but the operations of the high-speed integration period and the corrected timekeeping integration period are further repeated alternately to perform multiple integration such as six-fold integration, eight-fold integration, and so on. You may do so. The calculations in the count calculation circuit 5 during six-fold integration and eight-fold integration are shown in the following equations.

10 ²・CT ₂ −(10・CT ₄ −CT ₆ ) ……(7) 10 ³・CT ₂ −{10 ²・CT ₄ −(10・CT ₆ −CT ₈ )} ……(8) (However, , CT ₆ and CT ₈ are the count results in periods T ₆ and T ₈ , respectively) As can be seen from equations (7) and (8), in the case of a six-fold integral, it is 100 times the double integral, and in the eight-fold integral, it is a double integral. This is 1000 times more accurate than integration. Furthermore, when performing binary conversion in the corrected timekeeping integration period, the slope of the high-speed integration period may be twice the slope of the previous section. In this case, the calculation in the count calculation circuit 5 is 2・CT ₂ −CT ₄ ...(9) in the quadruple integrator circuit, and 2 ²・CT ₂ −(2・CT ₄ −CT ₆ ) ... in the sixfold integrator circuit. …(10) becomes.

Furthermore, the slope of the first or subsequent high-speed integration period is 10 ² times the slope of the previous interval,
It may be 10 ³ times (or 2 ² times, 2 ³ times). For example, if the slope of the first high-speed integration period is increased by 10 ² times, it is possible to obtain accuracy 100 times that of double integration in quadruple integration.

As explained above, according to the present invention, there is an input integration period in which an analog weight signal is integrated, and a reference power supply is integrated at a predetermined slope until the integration direction is reversed and the integration output crosses the 0 level. The reference power source is integrated during a time-measuring integration period during which time is measured using a predetermined clock, and at a slope that is m ⁿ times the slope (m and n are integers) until the clock measures a predetermined number of times after the integral output crosses the 0 level. a high-speed integration period, and after the clock has counted a predetermined number of times, the integration direction is reversed and the absolute value is the same slope as the time measurement integration period based on the integral value of the high-speed integration period until the integral output crosses the 0 level. a switching integration means having a corrected time-keeping integration period for integrating and timing this period with the clock; and converting the analog weight signal into a digital signal based on the time measurement results in the time-keeping integration period, the high-speed integration period, and the corrected time-keeping integration period. and converting means for converting, and the switching integration means is configured to perform the operation of the high speed integration period and the corrected timekeeping integration period one or more times after the operation of the timekeeping integration period following the input integration period ends. Therefore, high conversion accuracy can be obtained without using a highly accurate and expensive comparator, and the conversion time can also be shortened.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram showing the output waveform of the integrator in a conventional triple integration type A-D converter, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is the diagram shown in FIG. FIG. 3 is a waveform diagram showing the output waveform of the integrating circuit A shown in FIG. 2... Comparator (switching integrating means), 3... Control circuit (switching integrating means), 4... Clock generation circuit (switching integrating means), 5... Count calculation circuit (switching integrating means; converting means), A ...Integrator circuit (switching integration means), SW ₀ ~ SW ₁ - _{SW 3} ... Analog switch (switching integration means), T ₁ ... period (input integration period), T ₂ ... period (timekeeping integration period), _T3 ...
period (fast integration period), T ₄ ... period (corrected timekeeping integration period).

Claims (1)

[Claims] 1. An input integration period in which the analog weight signal is integrated; and a timing integration period in which the direction of integration is reversed and the reference power source is integrated at a predetermined slope until the integral output crosses the 0 level, and this integration period is clocked by a predetermined clock. , a high-speed integration period in which the reference power source is integrated with a slope m ⁿ times (m and n are integers) the slope until the clock counts a predetermined number of times after the integral output crosses the 0 level; After timing, the direction of integration is reversed, and the integration is performed at a slope with the same absolute value as the timed integration period based on the integral value of the high-speed integration period until the integral output crosses the 0 level, and this period is timed by the clock. and a conversion means for converting the analog weight signal into a digital signal based on the timekeeping results in the timekeeping integration period, the high speed integration period, and the correction timekeeping integration period, A weight measuring device characterized in that the switching integration means performs the operation of the high speed integration period and the corrected time measurement integration period one or more times after the operation of the time measurement integration period following the input integration period ends.