JPH0331282B2 - - Google Patents

Description

[Detailed description of the invention] [Summary] PNP transistor C-B on the constant current output terminal side
This is a constant current circuit using a short diode, and a PNP transistor is added between the current source to improve reverse breakdown voltage and saturation voltage, and to eliminate current errors caused by parasitic sub PNP transistors.

[Industrial application field]

The present invention relates to a circuit that causes a constant current to flow through a bias application terminal in response to the application of an external bias, and more particularly to a semiconductor integrated circuit composed of bipolar transistors.

[Conventional technology]

FIG. 3 shows a conventional constant current circuit. This circuit is a circuit L1 connected to current output terminals A and B,
This is a circuit that supplies a constant current to one of L2..., and by controlling the voltage bias applied to terminals A, B, etc., current flows only to the terminal that has reached a high level "H". There is. In Figure 3, terminal A has a collector base (hereinafter referred to as C-B).
A series circuit of short-circuited npn transistors Q _1a and Q _1b is connected, and a series circuit of CB-shorted npn transistors Q _2a and Q _2b is connected to terminal B. Each series circuit is connected to the collector of one transistor Q3 of the current mirror, and a constant current source _J1 is connected to the other transistor Q4 constituting the current mirror.

For example, external transistors T2 and T1
A signal is given to one of the bases of ..., and one of the terminals A, B, etc. becomes "H", and the others become low level "L", and become "H". Current switching is performed so that a constant current (set by constant current source J1) flows only through the terminal and no current flows through the "L" terminal.

However, when there are multiple outputs as shown in Figure 3, a potential difference occurs between the respective terminals. For example, if the potential of the A terminal is high and the potential of the B terminal is low, the potential of the collector node N of the transistor Q3 is approximately Terminal A
, and a reverse bias is applied between node N and terminal B. By the way, the reverse breakdown voltage of the C-B short diode of the npn transistor in the integrated circuit is 5V.
Since it is as low as ~8V, when the potential difference between A and B is large, there is a drawback that it breaks down and current flows in the opposite direction. One of the countermeasures against this insufficient breakdown voltage is to connect two stages of diodes of the C-B shorts of npn transistors in series as shown in FIG. However, if three or four stages are connected depending on the required withstand voltage, the saturation voltage becomes high and the control voltages at points A and B are limited, which is a drawback.

Therefore, in order to improve these, as shown in Figure 4,
It is conceivable to use C-B short diodes of pnp transistors Q1 and Q2. In Figure 4, pnp transistors Q1 and Q2 are connected to terminals A and B.
CB short diode is connected, and its connection node is connected to the collector of the current mirror transistor Q3, otherwise the circuit is the same as in FIG. C
-B short pnp transistors have a higher breakdown voltage than npn transistors, and depending on the process, they can easily achieve a voltage of about 30 to 40V.

[Problem that the invention seeks to solve]

As shown in Figure 4 above, pnp of C-B shot
When using transistors, current output terminals A and B
Although the risk of breakdown due to the potential difference between the lateral transistors is eliminated, parasitic currents IsQ ₁ and IsQ ₂ due to the parasitic sub pnp transistors of the lateral transistors flow, resulting in a problem that the constant current setting accuracy deteriorates.

In order to explain this parasitic current, FIG. 5 shows a cross-sectional main part of a lateral transistor. As usual, a p-type substrate 51 has a buried layer 52, an n ^- epitaxial growth layer 53, an isolation diffusion layer 54, A p emitter diffusion layer 55 and a p collector diffusion layer 56 are formed, and a lateral n base 57 is formed between the collector and the emitter. Holes injected from the emitter 55 flow laterally and head toward the collector 56, but some of the holes are formed by the p layer of the emitter 55, the n ^- epitaxial growth layer 53, and the isolation diffusion layer 54, or the p layer of the substrate. The parasitic sub pnp transistor actually causes isolation diffusion layer 54 or substrate 51
Run to the side. In Figure 4, this is summarized as IsQ1,
It is shown as IsQ ₂ .

Conventionally, the circuit shown in FIG. 3 has been used despite the breakdown problem because the parasitic current deteriorates the current setting accuracy of the constant current accordingly.

The present invention aims to solve this problem of deterioration of current setting accuracy due to parasitic current, and to provide a constant current circuit in which there is no risk of breakdown of the PNP transistor due to bias between current terminals.

[Means for solving problems]

The present invention connects the first terminal of a collector-base short diode of a pnp transistor to the current output terminal, connects the second terminal to the output terminal of a constant current supply circuit, and applies a potential to the current output terminal from an external circuit. Accordingly, in the circuit for flowing a constant current to the current output terminal, a constant current circuit is provided, characterized in that a diode of the collector-base short of another pnp transistor is inserted between the constant current supply circuit and the constant current source. provide.

For example, when applied to the circuit shown in Figure 4 above, the C of the current switching pnp transistors (Q1, Q2, etc.)
- A constant current circuit using a B-shot diode improves reverse breakdown voltage and saturation voltage, and
IsQ ₁ , IsQ ₂ due to the parasitic sub pnp transistor
In order to reduce the current error to zero, a PNP transistor is added between the current mirror and its current source.

[Effect]

In an integrated circuit, the relative variation of transistors is small, and the parasitic current Is component of each parasitic sub pnp is substantially constant due to its emitter current, so the current setting error can be canceled out by the above-described configuration of the invention.

〔Example〕

FIG. 1 shows a circuit according to an embodiment of the present invention.
Q1 and Q2 are pnp lateral transistors whose emitters are connected to terminals A and B, respectively, and the terminals whose collectors and bases are shorted are each connected to the collector of a current mirror npn transistor Q3, which is further connected to a current mirror npn transistor. Q
A pnp lateral transistor Q5 is inserted between the collector side of 4 and the constant current source J1.

Output current IA when current flows through A terminal now
The calculation results in the following.

The collector current of Q4 is IcQ4 = (J1 - IsQ5) - (IBQ4 + IBQ3) where IsQ5 is the current flowing to the parasitic sub pnp of Q5, and IBQ4 + IBQ3 is the error due to the base currents of Q4 and Q3. Further, the collector current of the current mirror transistor Q3 is IcQ3=IcQ4.

Therefore, the output current of current output terminal A, IA = IcQ3 + IsQ1 = IcQ4 + IsQ1 = (J1 - IsQ5) - IBQ4 - IBQ3 + ISQ1 Here, since IsQ5≒IsQ1, IA = J1 - IBQ4 - IBQ3 As above, the conventional The error current IsQ1 caused by the parasitic sub pnp can be removed, and the current setting accuracy can be improved.

Note that there is an error IBQ4 + IBQ3 due to the base current of the current mirror, but it is generally sufficiently small. However, to further improve current accuracy, it is necessary to eliminate errors caused by this base current.
FIG. 2 shows an example of a circuit that eliminates the error caused by the base current.

Components that are the same as those in FIG. 1 are indicated by the same reference numerals. This embodiment is characterized in that an npn transistor Q6 is added to the current mirror. The npn transistor Q6 has its base connected to the collector of Q4, its collector connected to the high-level power supply Vcc, and its emitter connected to the bases of Q3 and Q4. Therefore, if the base resistance R of Q3 and Q4 is sufficiently large, the error in the base current IBQ4 + IBQ3 will be the same as that of Q6.
It will be reduced to 1/hfe.

Note that although the above embodiments have been described with reference to the case where there is a plurality of current output terminals, the number of outputs may be one (only the A terminal). In that case, a circuit is constructed in which the current is cut off when the potential of terminal A goes negative in the external circuit. In the conventional example, the potential of terminal A contacts the collector of npn transistor Q3, but in an integrated circuit, the potential of terminal A contacts the collector of npn transistor Q3.
When forming a transistor, there is a p-n
A junction is formed and a diode is created between it and GND. Therefore, an undesirable reverse current flows while the potential of the terminal A is negative. On the other hand, in the circuit according to the present invention, the pnp transistor is
Since no diode is formed between the device and GND (substrate potential), no unnecessary reverse current flows.

Although the embodiments of the present invention have been described above, the present invention is not limited to these and can be modified in various ways without departing from the scope of the claims.

〔Effect of the invention〕

As described above, according to the constant current circuit of the present invention,
In addition to preventing reverse current in the constant current circuit, setting current errors based on parasitic currents caused by parasitic sub PNP transistors can be eliminated, and constant current setting accuracy can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the first embodiment of the present invention;
The figure is a circuit diagram of a second embodiment of the present invention, Figure 3 is a circuit diagram of a conventional example, Figure 4 is a circuit diagram of another conventional example, and Figure 5 is a sectional view of a main part of a lateral bipolar transistor. . Main symbols, A, B: (current output) terminal, Q1,
Q2, Q5: pnp transistor, Q3, Q4:
(npn transistor that constitutes a current mirror,
J1: constant current source, Q6: npn transistor.

Claims (1)

[Claims] 1. Connect the first terminal of the collector-base short diode of the PNP transistor to the current output terminal, connect the second terminal to the output terminal of the constant current supply circuit, and connect the external circuit to the current output terminal. In the circuit for flowing a constant current to the current output terminal in accordance with the potential applied from the current output terminal, a diode of the collector-base short of another PNP transistor is inserted between the constant current supply circuit and the constant current source. Constant current circuit.