JPH0331287B2 - - Google Patents

Description

[Detailed description of the invention]

FIELD OF THE INVENTION The present invention relates to a pitch restoring device that restores the pitch of a sound to the same pitch as when it was recorded when an audio signal is played back at twice the recording speed. BACKGROUND ART In recent years, it has become important to reproduce audio signals at a speed different from the recording speed. If you play back at twice the recording speed, it will take half the time it would normally take, and you can understand the content recorded on a tape recorder or VTR in half the time. However, simply increasing the playback speed to 2
If the pitch is doubled, the pitch will be higher and it will be difficult to hear, and at the same time, the characteristics of the speaker will not be revealed.
Therefore, there is a need for a device that can quickly listen to recorded content in a short time without changing the pitch of the sound. (For example, "Tape recorder that compresses and expands the time axis of conversation" Nikkei Electronics 1976.7.26) A conventional pitch restoring device will be explained below with reference to the drawings. FIG. 8 shows a configuration diagram of a conventional pitch restoring device. In FIG. 8, 1 is an analog-to-digital conversion circuit that converts an input signal into a digital signal, 2 is a digital memory that stores the digital signal, and 3 is a write/read control circuit that controls writing and reading from the digital memory 2. , 4 is a holding circuit that holds the signal read out from the digital memory 2, 16 is a digital-to-analog conversion circuit that converts the digital signal output from the holding circuit 4 into an analog signal, and 10 is for operating the analog-to-digital conversion circuit 1. 11 is a write address generation circuit that supplies the address to be written in the digital memory 2 to the write/read control circuit 3; 12 is a read address generator that supplies the address to be read from the digital memory 2 to the write/read control circuit 3. circuit, 14
1 is a demodulation clock generation circuit that operates the digital-to-analog conversion circuit 16, and 15 is a reduction pass filter. The operation of the pitch restoring device configured as described above will be described below. Fig. 9 shows a diagram of its principle. When reproducing at the same speed as recording, at time 0t2NT, d ₀ , d ₁ , ..., with a period of 2T.
Suppose that N signals, d _N-1, are to be reproduced. At this time, in double speed playback, when 0t<2NT,
Signals d ₀ , d ₁ , ..., d _2N-1 are reproduced. In order to lower the pitch and make it the same pitch as when recording,
As shown in FIG. 9d, when 0t<2NT, d ₀ , d ₁ , ..., d _N-1 are reproduced, and d _N , d _N+1 , ...,
The signal of d _2N-1 is not regenerated, and d _2N when 2NTt<4NT,
Play d _2N+1 ,..., d _3N-1 . The following will be played in the same manner. This restores the reproduced signal to its original pitch at the time of recording. Problems to be Solved by the Invention However, in the above method, the signal becomes discontinuous between d _N-1 and d _2N , and noise is generated. Also,
The signals of d _N , d _N+1 , ..., d _2N-1 are not regenerated at all,
There was a problem in that the information of this part of the signal was lost. Also, in order to avoid missing continuous long-range signals, if N is made small,
The number of connection points per time increases and the noise increases. In view of the above-mentioned problems, the present invention provides a pitch restoration device that uses all input signals and processes discontinuous points, thereby reducing information loss and reducing noise at connection points. It is. Means for Solving the Problems In order to achieve this object, the pitch restoring device of the present invention converts an analog input signal into a 1-bit digital signal, and outputs the digital signal to a digital memory that stores the digital signal. The address data generated by the digital conversion circuit, the write address generation circuit, and the first and second read address generation circuits are used as input data to specify the write and read addresses of the digital memory, and write and read control signals are generated. A write/read control circuit that generates a write/read control circuit, first and second holding circuits that latch each signal read from the digital memory at the first and second read addresses at a period of 2T, and the first and second For each signal latched in the holding circuit, a monotonically increasing weight function W ₁ (x)
(0xNT, 0W ₁ (x)1) or a monotonically decreasing weighting function W ₂ (x), (0xNT, 0
W ₂ (x) 1), an amplitude control circuit that controls the first and second multipliers, and a digital output signal of the first and second multipliers. The configuration includes a digital-to-analog conversion circuit for converting into an analog signal by the first and second integration circuits, and an addition circuit for adding the outputs of the first and second integration circuits. Effect The present invention has the above-described configuration, and the signals d ₀ , d ₁ , d ₂ , ..., d _2N-1 are generated at a period T from a certain reference time t=0.
The 2N signals of 0t<2NT are stored in the digital memory, and in the first holding circuit
At 2T, N signals d ₀ , d ₁ , d ₂ , ..., d _N-1 are read out from the digital memory and held, and in the second holding circuit, the period 2T is set at a time when NTt<3NT.
reads out and holds N signals d _N , d _N+1 , d _N+2 , ..., d _2N-1 from the digital memory, and also performs a first multiplication on the output signal of the first holding circuit. In the circuit, W ₁ (t) for 0tNT, NTt
2NT is multiplied by W ₂ (t-NT), and the output signal of the second holding circuit is multiplied by W ₂ (t) for 0tNT, NTt
The pitch is restored by multiplying 2NT by W ₁ (t-NT) and repeating the above writing, reading, and amplitude control at a cycle of 2NT. Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a pitch restoring device according to an embodiment of the present invention. Reference numeral 21 indicates a 1-bit analog signal which converts the input signal into a 1-bit digital signal using the clock of the modulation clock generating circuit 10 and outputs the digital signal to a digital memory (RAM) 2 that stores the digital signal.
a digital conversion circuit; 3 is a write address generation circuit 11; first and second read address generation circuits 12;
13 are write and read control circuits that designate write and read addresses in the digital memory 2 as input data and generate write and read control signals; 4 and 5 are first and second write and read control circuits; First and second holding circuits each latching each signal read out from the digital memory 2 according to the read address at a period of 2T; For the signal, a monotonically increasing weight function W ₁ (x)
(0xNT, 0W ₁ (x)1) or a monotonically decreasing weighting function W ₂ (x), (0xNT, 0
8 is an addition circuit that adds the output signals of the first and second integrating circuits 16 and 17 _, and 9 is the first and second multiplication circuit. The amplitude control circuit that controls the circuits 6 and 7 generates signals d ₀ , d ₁ , d ₂ , . . . at a period T from a certain reference time t=0.
The 2N signals of d _2N-1 are stored in the digital memory 2, and the first holding circuit 4 stores the signals d ₀ , d ₁ , d ₂ , ..., d _N-1 with a period of 2T at a time of 0t<2NT. The second holding circuit 5 reads the N signals from the digital memory 2 and holds them, and the second holding circuit 5 reads the signals d _N , d _N+1 , d _N+2 , ..., d _2N with a period of 2T at a time when NTt<3NT. N signals of _-1 are read out from the digital memory 2 and held, and the output signal of the first holding circuit 4 is applied to the first multiplier circuit 6 to calculate W ₁ (t) for 0tNT.
, NTt2NT is multiplied by W ₂ (t-NT), and the output signal of the second holding circuit 5 is multiplied by the second multiplication circuit 7, and W ₂ for 0tNT is multiplied by W 2 (t-NT).
(t) and NTt2NT are each multiplied by W ₁ (t-NT). The output signals of the first and second multiplier circuits 6 and 7 obtained in this way are transmitted to the first and second integrator circuits 1 and 1.
6 and 17, each becomes an analog output,
The outputs of the first and second integrating circuits 16 and 17 are output to the adding circuit 8. Reference numerals 26 and 27 constitute a 1-bit digital-to-analog conversion circuit for converting the digital signal from the digital memory into an analog signal as described above. In each figure, the same parts are given the same numbers. Here, the principle of the present invention will be explained using FIG. 2. FIG. 2 shows a principle diagram of the present invention. During double speed playback, d ₀ , d ₁ ,
..., d _2N-1 2N signals are input and written into the digital memory 2. At this time, due to the address given by the first read address generation circuit 12, the first holding circuit 4 has d ₀ ,
The signals d ₁ , ..., d _N-1 are read out, and the addresses given by the second read address generation circuit 13 cause the signals d _N , d _N+1 , ..., d _2N- , which were missing in the past, to be read out. ₁ signal is
The data is read out to the second holding circuit 5 during time NTt<3NT. Since the two signals read out to the first holding circuit 4 and the second holding circuit 5 have a discontinuous point, amplitude control T ₁ , T is performed to eliminate the influence of the discontinuous point on each signal. Add ₂ . The signal read out to the first holding circuit 4 is controlled by amplitude control T ₁ as shown in FIG. As shown in g, amplitude modulation is applied linearly in synchronization with the period of the discontinuous point by amplitude control _T2 . A method for adding this amplitude modulation is shown below. That is, the outputs of the first holding circuit and the second holding circuit are controlled by the amplitude control circuit 9 to the first multiplication circuit 6 and the second multiplication circuit 7.
Amplitude control T ₁ and T ₂ is performed by changing the multiplication coefficient of 0 to 1. The two read signals described above are transferred to the first and second integrating circuits 16 and 1.
By outputting the sum added by the adder circuit 8 via the adder circuit 7, a pitch-restored sound with less missing information and less noise at connection points can be obtained. The operation of the pitch restoring device configured as above will be explained below. The 1-bit analog/digital conversion circuit 21 converts the input signal into a 1-bit digital signal. This output digital signal is written into the digital memory 2 every cycle T by the write/read control circuit 3 at the timing shown in FIG. 2a. The addresses written to and read from the digital memory 2 are reset after a certain period of time, as shown in an example in FIG. 2b. The write address, the first read address, and the second read address are generated by a write address generation circuit 11, a first read address generation circuit 12, and a second read address generation circuit 13, respectively, and write/read control is performed. The circuit 3 applies the signal to the digital memory 2 at the timing shown in FIG. 2a. The first holding circuit 4 holds the signal read out at the time of readout _D1 in FIG. 2a for 2T time, and the second holding circuit 5
The signal read out at the time of read D ₂ is 2T
Hold time. The first multiplication circuit 6 changes the amplitude shown in FIG. 2f by changing the multiplication coefficient using the amplitude control circuit 9 and multiplying this by the holding circuit 4. The second multiplier circuit 7 similarly applies amplitude control _T2 shown in FIG. 2g. The adder circuit 8 adds the output of the first multiplier circuit 6 and the output of the second multiplier circuit 7, and outputs the result through the reduction pass filter 15 as an output signal. Incidentally, FIG. 3 is a timing chart showing the operating state of each part and the arrangement of addresses in this embodiment. As described above, according to this embodiment, reading is performed twice in one unit time as shown in FIG. 2, signals stored at different times are read out, and the amplitude is controlled and added. It is possible to reduce the loss of information in the pitch-restored voice and to reduce the noise at the connection point. Although a 1-bit analog-to-digital converter is used in this embodiment, a case will be described in which an adaptive delta modulator/demodulator is used for this analog-to-digital converter. FIG. 4 is a block diagram of its configuration. In FIG. 4, block a represents an adaptive delta modulator. In FIG. 4, 30 is a comparator, 31
32 is a step width adaptive logic circuit having an algorithm for determining the quantization step width; 33 is an up-down counter that outputs a 1-bit digital signal for each sampling clock; Counter output appears. 34 is a decoder that converts an m-bit signal into n-bit signal; 35 is a pulse width modulation circuit that outputs a pulse width in response to the n-bit output signal from the decoder 34; 36 is a "1" from the sampling circuit; “0”
37 is an integrating circuit that integrates the output from the polarity switching circuit 36 and converts it into an analog signal. Similarly, block b represents an adaptive delta demodulator. In the figures, the same parts are given the same numbers. Therefore, the output of the integrating circuit 37 is passed through a reduction filter 38 to obtain an analog output. The operating principle of the present invention will be explained with reference to FIG. The step width adaptation logic circuit 32 sends a signal to the up-down counter 33, which activates an up counter when the step width is to be made larger than the current one, and a down counter when the step width is to be made smaller than the current one. The following explanation assumes that the output of the up-down counter 33 is m=3 bits and the output of the decoder 34 is n=4 bits.
The output of the up-down counter 33 selects one of eight signals (000, 001, . . . , 111). The decoder 34 is not required when output signals of pulse widths are made to correspond in a straight line to eight types of signals. However, linear correspondence alone is not sufficient to reduce noise when there is no signal and to reduce overload noise that occurs at high frequencies or large inputs. Therefore, the decoder 34 makes a non-linear correspondence. The 3-bit counter output becomes 4-bit (2 ⁴ =
16 ways), the non-linear type is used, for example, as shown in the table below.

[Table] When expressed in decimal numbers, 0, 1, 2, 3, 5, 7,
11, 15. Next, pulse width modulation for converting the output of the decoder 34 into a pulse width can be concretely realized by a counter. In this case, a 4-bit counter is used, but the pulse width corresponding to the number of counters determined by the master clock is determined. As an example, master clock MCK=4.00MHz
(ΔM = 0.25 μsec), and if the sampling clock of the modulator/demodulator is 250 KHz (ΔT = 4 μsec), the maximum within one cycle is ΔT/ΔM = 16 (number of counts). At this time, all signals are "1" within one cycle (4 μsec), and the pulse width is also the maximum. Similarly, the pulse width is 12 counts → 3 μsec, 8 counts → 2 μsec, 6 counts → 1.5 μsec, 4 counts → 1 μsec, 3 counts → 0.75 μsec, 2 counts → 0.5 μsec, 1 count → 0.25 μsec. This pulse width may be at any position within one cycle; for example, pulse output widths as shown in FIG. 6b and FIG. 7b can be considered. A pulse output as described above is obtained every cycle, this signal is switched between positive and negative by the polarity switching circuit 36, and is integrated by the integrating circuit 37 to output an analog signal. In order to further reduce quantization noise and overload noise, it is recommended to increase the number of bits of the up-down counter 33 and the number of bits of the counter 34. Next, the multiplication method will be explained. Specifically, the amplitude control circuit 9 generates a signal having a pulse width as shown in FIG. 6a and FIG.
Varies between. Now here, pulse width modulation circuit 35
If the output from the amplitude control circuit 9 is set to P7 in Fig. 6b, and the output from the amplitude control circuit 9 is set to D2, P7×D2 becomes zero, and the originally intended signal of P7 is reduced to 1/4.
I can't do it. A similar phenomenon may occur with multiplication under other conditions. Therefore, in this embodiment, the output of the pulse width modulation circuit 35 is generated into temporally dispersed pulses as shown in FIG. 7b, and multiplication is performed as described above. Then P7× from earlier
In D2, only the first peak becomes "1" and remains, the other three peaks become "0", and a 1/4 output waveform is obtained. Note that multiplication of digital waveforms can be realized using an AND gate circuit. In this embodiment, amplitude control is performed on the digital signal, but it may be performed after digital-to-analog conversion and then added. As described above, this embodiment uses an adaptive delta modulator/demodulator in the analog-to-digital conversion system, so the circuit scale is small, and since many parts that can be realized with gate circuits are used, the pitch restoring device is inexpensive. can be configured. Effects of the Invention The present invention provides a second readout number generation circuit, a second holding circuit, first and second multiplier circuits, an addition circuit, and an amplitude control circuit, thereby eliminating the need for an amplitude control circuit that has not been used in the past. Pitch can be restored using the signal. Therefore, even after pitch restoration, there is less information missing,
Further, by controlling the amplitude, it is possible to realize an excellent pitch restoring device that can obtain the effect of reducing noise at the connection point. In addition, ADM is used as an analog-to-digital conversion method.
By using this method, it is possible to realize a pitch restoring device with a small circuit scale and at low cost.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a pitch restoring device according to an embodiment of the present invention, Fig. 2 is a diagram showing the principle of pitch restoring according to the present invention, and Fig. 3 is an operational state of a digital memory according to an embodiment of the present invention. 4 is a configuration block diagram of the analog-to-digital conversion circuit of the present invention, FIG. 5 is a block diagram for explaining the main operations of the analog-to-digital conversion circuit of the present invention, and FIG. 6 is a timing chart showing the address arrangement. 7 is a waveform diagram for explaining the operation of the multiplication circuit of the present invention, FIG. 8 is a block diagram of a conventional pitch restoring device, and FIG. 9 is a diagram showing the principle of pitch restoring in the conventional pitch. 2... Digital memory, 3... Write/read control circuit, 4... First holding circuit, 5...
Second holding circuit, 6... First multiplication circuit, 7...
Second multiplier circuit, 8...Addition circuit, 9...Amplitude control circuit, 10...Modulation clock generation circuit, 11...
...Write address generation circuit, 12...First read address generation circuit, 13...Second read address generation circuit, 14...Demodulation clock generation circuit, 15...
...reduction pass filter, 16...first integration circuit,
17...Second integration circuit, 21...1-bit analog-to-digital conversion circuit, 26, 27...1-bit digital-to-analog conversion circuit.

Claims (1)

[Scope of Claims] 1. An analog-to-digital conversion circuit that converts an analog input signal into a 1-bit digital signal and outputs it to a digital memory that stores the digital signal, a write address generation circuit, and first and second
The address generated by the read address generation circuit and
Specify the write and read addresses of the digital memory as input data, write,
a write and read control circuit that generates a read control signal, and first and second holding circuits that latch each signal read from the digital memory at the first and second read addresses at a period of 2T; For each signal latched by the first and second holding circuits, a monotonically increasing weighting function W ₁ (x)
(0xNT, 0W ₁ (x)1) or a monotonically decreasing weighting function W ₂ (x), (0xNT, 0
1 for converting the digital output signals of the first and second multiplier circuits into analog signals in the first _and second integration circuits. It is equipped with a bit digital-to-analog conversion circuit and an addition circuit that adds the outputs of the first and second integration circuits, and outputs signals d ₀ , d ₁ , d ₂ , . . . at a period T from a certain reference time t=0. d _2N-1 2N signals are stored in the digital memory, and the first holding circuit stores the signals at a period of 2T at a time of 0t<2NT.
N signals d ₀ , d ₁ , d ₂ , ..., d _N-1 are read out from the digital memory and held, and the second holding circuit reads the signals at a period of 2T at a time when NTt<3NT.
Read and hold N signals d _N , d _N+1 , d _N+2 , ..., d _2N-1 from the digital memory, and
A first multiplier circuit applies the output signal of the first holding circuit to
W ₁ (t) for 0tNT, NTt2NT
are multiplied by W ₂ (t-NT), and the output signal of the second holding circuit is multiplied by the second multiplier circuit, and the output signal is 0.
It has an amplitude control circuit that multiplies tNT by W ₂ (t) and NTt2NT by W ₁ (t-NT), and by repeating the above writing, reading, and amplitude control at a cycle of 2NT, the pitch can be adjusted. A pitch restoration device that restores pitch. 2. An adaptive delta modulation method is used for 1-bit analog-to-digital conversion, and when the 1-bit delta-modulated digital data "1" or "0" is consecutive, the quantization step width is increased. 2. The pitch restoring device according to claim 1, wherein the adaptive quantization step width is determined using a pulse width modulation circuit in a delta modulator having a compression/expansion circuit that varies an integrator output. 3. The pitch restoring device according to claim 2, characterized in that a linear pulse width modulation circuit is used as the pulse width modulation circuit, which linearly converts the pulse width into a pulse width corresponding to the number of pulses. 4. The pitch restoring device according to claim 2, wherein a non-linear pulse width modulation circuit that non-linearly converts the pulse width into a pulse width corresponding to the number of pulses is used as the pulse width modulation circuit. 5. The pitch restoring device according to claim 1, wherein in the first and second multiplier circuits, both the multiplier and multiplicand signals are pulse width modulated signals.