JPH0332251B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a device for detecting frames in digital transmission.

Conventional technology As a conventional frame detection device, for example, the National Technical Report “High Quality Video Signal
PCM optical transmission equipment” (Hiroaki Nakata et al., National
Tech. Rept. 29, No. 5, p. 38-45 (1983)).

FIG. 3 is a block diagram of a data signal frame detection device which simplifies the device and uses an alternating pattern of “1” and “0” every 8 bits as a frame signal, where 1 is an input data signal; 2 is a clock signal whose frequency is the same as the transmission speed of input data signal 1; Reference numeral 3 designates a frequency dividing section which divides the frequency of the clock signal 2 by eight, and reference numeral 4 designates a frame synchronization pulse which is the output of the frequency dividing section 3 and which divides the frequency of the clock signal 2 by eight. 5
and 7 are D flip-flops (hereinafter referred to as D-FF)
D-FF5 and D-FF7 constitute a two-stage shift register, and 6 and 8 are D-FF5 and D-FF.
7 is the D-FF output of each output. 9 is D-FF output 6 and D-FF output 8 “1” and “0”
Or it determines whether it is a frame signal based on whether it is "0" or "1", and if it is not in a frame synchronization state, it outputs a hunting pulse 10 to the frequency divider 3,
Set the width of frame synchronization pulse 4 to 1 of clock signal 2.
This is a synchronization determination unit that increases the number by the period.

_FIG . ₄ is a time chart showing the signal waveforms of each part of the block diagram of FIG. 0" in an alternating pattern. A ₁ and A ₂ represent data one bit before frame synchronization bits F ₁ and F ₂ . b is frame synchronization pulse 4, c is hunting pulse 10, d, e
are D-FF output 6 and D-FF output 8, respectively, and A ₁ , A ₂ , F ₃ , and F ₄ correspond to the data in a.

In the conventional frame detection device configured as described above, data of every 8 bits of the input data signal 1 is captured into the D-FF 5 using the frame synchronization pulse 4 obtained by dividing the frequency of the clock signal 2 by 8 in the frequency divider 3. , simultaneously shifts D-FF output 6 to D-FF 7. A synchronization determination section 9 determines whether or not the synchronization state is present based on the D-FF output 6 and the D-FF output 7, and outputs a hunting pulse 10 when necessary. When the frequency dividing unit 3 receives the hunting pulse 10, it stops dividing the clock signal 2 by one period.
Set the width of frame synchronization pulse 4 to 1 of clock signal 2.
It operates so that the D-FF5 can next take in data 9 bits after the data taken in by the D-FF5. Frames are detected by repeating the above operations. Figure 4 shows a time chart when detecting a frame. Data A ₂ of a is taken in, and it is determined that they are not in synchronization based on A ₂ of d and A ₁ of e, and a hunting pulse is generated. ing. and frame synchronization bit F ₃ of a.
The frame synchronization bit _F4 of a is fetched with the next frame synchronization pulse, and the F4 of d and the bit _F4 of e are fetched.
It is determined that synchronization has been achieved from _F3 , and a frame is detected.

Problems to be Solved by the Invention However, in the above configuration, even if the hunting pulse 10 is generated and the data to be captured is shifted by 1 bit, both of them will be different as shown in F ₃ in d and A ₂ in e in Fig. 4. has not become a frame synchronization bit, and both do not become frame synchronization bits until one period after the frame synchronization pulse 4. Therefore, once the hunting pulse 10 is generated, control must be performed so that the hunting pulse 10 is not generated during one cycle of the next frame synchronization pulse 4.
The problem was that it took a long time to detect the frame.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a frame detection device having a simple configuration and shortening the frame detection time.

Means for Solving the Problems In order to solve the above problems, the present invention provides a second shift register, and stores data one bit after the input data signal taken in by the first shift register into the second shift register. The frame is detected quickly by loading the data in the second shift register into the first shift register at the same time as the hunting pulse is generated.

Effects According to the present invention, with the above-described configuration, the data of the second shift register is loaded into the first shift register at the same time as the hunting pulse is generated, so that the data of the second shift register is determined from the moment it is loaded. Since the frame synchronization bit is detected quickly, the frame detection time becomes shorter.

Embodiment FIG. 1 is a block diagram showing an embodiment of the frame detection device of the present invention. In this embodiment, as in the conventional example, it is assumed that the input data signal has a frame signal with an alternating pattern of "1" and "0" every 8 bits. A similar frame detection device can be configured for signals having complex frame signals. Note that elements in FIG. 1 that are common to those in FIG. 3 are designated by the same numbers.

13 is a frequency dividing unit that divides the clock signal 2 by 8;
4 is the output of the frequency divider 13 and is a delayed frame synchronization pulse delayed by one cycle of clock signal 2 from frame synchronization pulse 4, 15 is D-FF, and 16 is D-FF.
15 is the D-FF output, 21 is the D-FF output 6
a switching unit 19 that selects either of the D-FF output 16 and the D-FF output 16 according to the control signal 22 and outputs the selected one to the D-FF 7;
determines whether the D-FF output 6 and D-FF output 8 are “1” and “0” or “0” and “1” as frame signals, and if they are not in frame synchronization state, the frequency divider 3 It is a synchronization determination section that outputs a control signal 22 so that the switching section 21 selects the D-FF output 16 at the same time as outputting the hunting pulse 10. Other numbers that are the same as those in FIG. 3 of the conventional example are the same.

FIG. 2 is a time chart showing signal waveforms at each part of the block diagram in FIG. 1, and f is a in FIG. 4.
is the same input data signal as , and B ₁ to B ₄ represent data one bit after frame synchronization bits F ₁ to F ₄ . g is frame sync pulse 4, h is delayed frame sync pulse 14, i is hunting pulse 10, j, k, l are D-FF output 6 and D, respectively.
-FF output 16 and D-FF output 8, A ₁ , A ₂ , F _{1 , F 2 ,} F ₃ , F ₄ , B ₃ , B ₄ in each are f
This corresponds to the data in .

The operation of the frame detection device of this embodiment configured as described above will be described below.

With the frame synchronization pulse 4, which is obtained by dividing the frequency of the clock signal 2 by 8 in the frequency divider 13, the data of every 8 bits of the input data signal 1 is taken into the D-FF5, and on the other hand, with the delayed frame synchronization pulse, the next bit of the data is taken into the D-FF5. The data is taken into the D-FF 15. D-
D-FF output 6 or D-FF output 16 to FF7
One of them is selected and inputted by the switching section 21. A synchronization determination section 19 determines whether or not they are in a synchronized state from the D-FF output 6 and the D-FF output 8, outputs a hunting pulse 10 when necessary, and at the same time, a switching section 21 selects the D-FF output 16. A control signal 22 is output as shown in FIG. hunting pulse 1
0 is output, the frequency divider 13 stops frequency division by one period of the clock signal 2, thereby increasing the width of the frame synchronization pulse 4 and the delayed frame synchronization pulse 14 by one period of the clock signal 2. However, the D-FF5 operates so that the data 9 bits after the data taken in by the D-FF5 can be taken in next. Also, by operating the switching section 21, D
-FF output 16 is taken into D-FF7. Frames are detected by repeating the above operations. Figure 2 shows a time chart when detecting a frame, and when the data A ₂ of a is captured, it is determined that they are not in synchronization from A ₂ of j and A ₁ of l, and the hunting pulse is occurring. The switching unit 21 selects D-FF16 (k in FIG. 4) at the same time that the hunting pulse is generated, so data _F3 is transferred to D-FF5 at the rising edge of the frame synchronization pulse immediately after the hunting pulse is generated. - Since data F ₂ is taken into FF7, the synchronization determination unit 19 immediately reads F ₃ of j at that point.
It can be determined that synchronization has been achieved from F ₂ of and l, and frames can be detected quickly.

Effects of the Invention As explained above, according to the present invention, frames can be detected more quickly with an extremely simple configuration.
It is extremely useful in practical terms.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a frame detection device according to an embodiment of the present invention, FIG. 2 is a time chart showing signal waveforms of each part of the device in FIG. 1, and FIG. 3 is a block diagram of a conventional frame detection device. FIG. 4 is a time chart showing signal waveforms of various parts of the device in FIG. 1...Input data signal, 2...Clock signal,
3...Frequency dividing section, 4...Frame synchronization pulse, 5,
7, 15...D flip-flop, 6, 8, 16
. . . D flip-flop output, 9 . Control signal.

Claims (1)

[Claims] 1. A clock signal having the same frequency as the transmission rate of the input data signal having 2 frame synchronization bits is divided, and a second frame synchronization pulse is generated at a frequency corresponding to the period of the frame synchronization bits in the first frame. Two types of frame synchronization pulses are generated that are delayed by one period of the input data signal from the synchronization pulse, and when a hunting pulse is input, the periods of the two types of frame synchronization pulses are lengthened by one period of the input data signal. a first D flip-flop that latches the input data signal with the first frame synchronization pulse; and a first D flip-flop that latches the input data signal with the first frame sync pulse; a second D flip-flop that latches with two frame synchronization pulses; a switching section that selects and outputs either the output of the first D flip-flop or the output of the second D flip-flop;
a third D flip-flop that latches the output of the switching section with the first frame synchronization pulse;
It is determined from the output of the flip-flop whether the flip-flop is in a synchronized state, and if the flip-flop is not in a synchronized state, the hunting pulse is outputted to the frequency dividing section as necessary, and the switching section outputs the output of the second D flip-flop. and a synchronization determination section that outputs a signal for controlling the switching section to select and output to the third D flip-flop.