JPH033254B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device, and more specifically, to a storage device that allows expansion and addition of storage blocks without changing the common control unit of the centrally controlled storage device. It's about configuration.

Conventionally, in an information processing apparatus, as shown in FIG. is accessing. However, in recent years, with the increase in the degree of integration of LSI memory elements, a centrally controlled storage device, as shown in FIG.

In a centrally controlled storage device, the storage block 4 is an expansion unit, and the memory capacity installed in one storage device can be changed using the capacity of the storage block 4 as a unit.

Note that in information processing systems that use centrally controlled storage devices, only one storage device is often used in the system.

As shown in FIG. 2, the method for adding a centrally controlled storage device is to
Since the interface 5 is the same with the common control unit 3, if you prepare space for mounting the required number of interfaces 5 and memory blocks 4 in the common control unit 3 in advance, you can change the common control unit 3 when adding memory blocks 4. do not have to.

However, apart from adding memory block 4, 1
When expanding the storage device of each storage block 4, the configuration of the common control section 3 must be changed because the interface 5 with the common control section 3 will no longer match in terms of addresses. For example, change the maximum storage capacity per memory block from 32K words x 2 bytes.
When expanding to 128K words x 2 bytes, if the chip size increases, or if the generation of the storage device itself is changed, all you need to do is design a new common control unit 3, so there will be no problems. There isn't.

However, in recent years, the storage density of semiconductor storage devices has improved significantly, and even for N-MOS RAM, the storage capacity per chip of approximately the same size has increased significantly in recent years.
It has been gradually increased to 4K bits, 16K bits, and 64K bits, and is now commercially available.

Under these circumstances, since the unit price per bit has become low, users often desire to expand the storage capacity of existing storage devices within the same space.

An object of the present invention is to meet such demands by providing an interface with the common control section without changing the design of the common control section even when expanding the maximum storage capacity per memory block in an existing storage device. To provide a storage device that can easily expand the maximum storage capacity per unit block and add expanded storage blocks.

In order to achieve the above object, the storage device of the present invention includes a plurality of storage blocks each containing a plurality of chips each constituted by a storage element array, and a control unit that commonly controls the storage blocks. The control section includes an address data bit register for storing address data bits consisting of a plurality of bits, and a predetermined bit of the address data bits inputted from the address data register without going through a switching means to control the storage element array. a multiplexer that outputs word row address selection bits and word column address selection bits for selecting word rows and word columns in the address data bit; and a first bit array that does not overlap with predetermined bits of the address data bits. , and a second bit array including bits that are not used for selecting the storage array out of the predetermined bits, and specify the storage block according to the switching signal indicating expansion or reduction of the storage capacity of the storage block. The memory block selection signal to be used is
or means for generating and outputting from either of the second bit arrays, and using the memory block selection signal and the multiplexed word row address selection bits and word column address selection bits to select the memory element of the memory chip. There is a feature in selecting the array.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of a storage device equipped with an address/data/bit switching mechanism showing an embodiment of the present invention.

In FIG. 3, a storage device 2 connected to a processor 1 is composed of a common control section 3 and one or more storage blocks 4.

The common control unit 3 stores address data sent from the processor 1.
A register 13, an address/data bit switching mechanism 10 to 12 for changing the use of the address/data bits, and a mechanism for sending part of the address/data to eight address/data buses 19 in a time-sharing manner. multiplexer 14; decoder 1 for selecting any one of the two element enable lines 18;
It is composed of a decoder 16 that selects any one of the 5 and 16 MS selection signal lines 17.

The memory block 4 includes two rows of memory element chips 22 connected to an address gate 20 and an address/data buffer commonly connected to them.
It is composed of a gate 21.

Since the storage block 4 corresponds to the MS selection signal line 17, the common control section 3 can connect up to 16 blocks. Two element enable lines 18 and an address/data bus 19 are commonly connected to each storage block 4.

Note that the MS selection signal line 17, element enable line 18, and address data bus 19 are
This corresponds to interface 5 in the figure.

In addition, descriptions of timing systems and other necessary functions are omitted.

When the common control unit 3 and the memory block 4 are connected, the decoder 16 selects only one memory block 4 during one memory cycle, and the AND gate 2 in the memory block 4 selected by the decoder 15
0, select either A ₀ or A ₁ . Therefore, in the memory block 4, one column (18 bits=2 bytes) of the two columns of memory element chips 22 is selected and operated. At this time, the address data passed through the buffer gate 21 indicates a 1-bit address of each storage element array in the storage element chip 22.

Figure 4 shows the address and address of the storage device shown in Figure 3.
FIG. 3 is an explanatory diagram showing the usage of data bits.

The address/data bit display 30 shown in FIG. 4 corresponds to the address/data register 13 in FIG. 3, and shows 24 bits of byte addresses ²⁰ to ²²³ .

In the storage device 2, each of the storage element chips 22
If the memory capacity is 16384 words x 1 bit (=16K bits)/chip, the maximum memory capacity of memory block 4 will be approximately 64K bytes, so the maximum memory capacity for 16 memory blocks will be approximately 1M bytes.

In order to be able to increase the storage capacity starting from 64K bytes in 64K byte increments up to a maximum of 1M byte,
The use of address data bits is determined as shown in case A of FIG. That is, the usage display (ECS) 31 uses bits 2 ¹ to 2 ⁷ for selecting word row addresses in the memory array in the storage chip 22 , and the usage display (ERS) 32 uses bits 2 ⁸ to ^{2 14} . The bits are also used for word address selection, and the purpose display (CS) 33 is used for chip selection to select any one column out of the ^two columns of memory element chips ( _C0 to _C17 ) 22. and usage indication (MSS) 34
²¹⁶ to ²¹⁹ are respectively used for MS selection to select any one memory block 4 among the 16 blocks.

For use in such applications, address/data/bit switching mechanisms 10 to 1 are shown in FIG.
Bit selection is performed by adding a switching signal to 2.

As the density of memory devices increases, the memory element chip 22
By replacing the memory block 4 with one with a memory capacity of 65536 words x 1 bit (=64K bits)/chip, the maximum memory capacity of memory block 4 is expanded to 256K bytes, and the maximum memory capacity of memory block 2 is 4M in units of 256K bytes. In order to be able to increase the number of bytes,
It is necessary to determine the use of address data bits as shown in case B of FIG.

Application indications 35, 36, 37, 38 shown in Figure 4
are used for word row address selection, word column address selection, chip selection, and MS selection in the storage element array in the storage element chip 22, respectively.

In FIG. 3, the switching signals applied to the address/data/bit switching mechanisms 10 to 12 are changed in order to use it for an application like case B in FIG.
The bit address, data, and bits are switched and sent to the multiplexer 14 and decoders 15 and 16.

Note that in case A, the output of M7 of multiplexer 14 corresponding to ²⁸ bits is not used on the memory block 4 side, but in case B, it is used, so prepare hardware for case B. .

Furthermore, the TF signal applied to the decoder 15 is
This is an activation timing signal for the memory element chip 22, and the TRC signal applied to the multiplexer 14 is a timing signal for transmitting address data in a time-division manner.

In Figures 3 and 4, the basic address
A storage device 2 with data bit switching mechanisms 10-12 is shown.

FIG. 5 is a block diagram of a storage device illustrating another embodiment of the present invention, in which a simplified address/data/bit switching mechanism is provided.

Address/data/bit switching mechanism (G8~
G11) 12 can expand the storage capacity by simply switching 4 bits. Address/Data/
The configuration other than the bit switching mechanism 12 is the same as that shown in FIG. 3, so a description thereof will be omitted.

FIG. 6 is an explanatory diagram of the uses of address data bits in the storage device 2 shown in FIG.

Case A in FIG. 6 is exactly the same as case A in FIG.
This is the case with chips. Also, case C in Figure 6
is when the memory element chip 22 is 64K bits/chip, and the usage indicators (ECS) 31 and 39 are for selecting the word row address in the memory element array, and the usage indicators (ERS) 32 and 40 are also for selecting the word column address. The purpose display (CS) 33 is used for chip selection, and the purpose display (MSS) 38 is used for MS selection. Address/data/bit switching between case A and case C can be performed by a switching signal applied to the switching mechanism (G8 to G11) 12 in Fig. 5 depending on the purpose of use.
It is only necessary to switch 4 bits ²¹⁶ to ²¹⁹ .

Furthermore, although not shown in FIG. 5, an address/data/bit switching mechanism can be added to the decoder 15 to realize a simplified switching mechanism. The use of address data bits in that case is shown in case D of FIG. Case D is the same as case C, when the memory element chip 22 is set to 64K bits/chip, and the purpose display (ECS) 41 is for selecting a word row address in the memory array, and the purpose display (ERS) 42 is Likewise, the word column address selection and purpose display (CS) 43 are used for chip selection. Other usage indication 3
1, 32, and 38 are the same as case C, and address/data/bit switching between case A and case D is performed in the same manner as in case A and case C. In this case, the address data bits that need to be switched are 5 of ²¹⁵ to ²¹⁹ .
It's bit.

An example of the use of the address data bits shown in FIGS. 4 and 6 is for the memory element chip 22.
It is based on the use of 16K bits/chip, but it is also possible to use memory element chips with other capacities.

FIG. 7 is a usage arrangement diagram of address data bits showing another embodiment of the present invention.

FIG. 7 shows an example of how address data bits are used when the capacity of the memory element chip 22 is replaced with a smaller capacity one when reducing the memory capacity based on 64K bits/chip.

Case B in Figure 7 shows the usage for 64K bits/chip, and as explained in Case B in Figure 4, usage indication (ECS) 35, (ERS) 3
6, (CS) 37, and (MSS) 38 are basically equipped with a switching mechanism. Case F is when the memory element chip 22 is 16K bits/chip, and the usage indication (ECS) 31, (CS) 44, (ERS) 45,
(MSS) 34 is used for selecting a word row address in the memory element array, for selecting a chip, for selecting a word column address in the memory element array, and for selecting an MS.

As is clear from FIG. 7, the number of address data bits required to switch the usage between case B and case F is 2 ⁸ , 2 ¹⁶ , 2 ¹⁷ , 2 ²⁰ , and 2 ²¹ , which is a total of 5 bits.

In this way, by providing as many switching mechanisms as the number of bits that require switching of uses and allocating them in correspondence with the bits, it becomes possible to expand or reduce the storage capacity of the storage element chip and to increase the number of storage blocks.

FIG. 8 is a block diagram of an address/data/bit switching mechanism showing an embodiment of the present invention.

FIG. 8 shows the switching mechanism 1 shown in FIG. 5 as an example.
2 is configured so that it can be switched between case A and case C in FIG. 6 according to the intended use. That is, when used for case A, inputting the switching signal "1" opens AND gates A1, A3, A5, and A7, and 2 ¹⁶
The four bits ^.about.219 enter the decoder 16 as the (MSS) 34 signal, where they are decoded to select one of the 16 storage blocks.

Next, when using for case C, inputting the switching signal "0" opens AND gates A2, A4, A6, and A8, and the 4 bits ²¹⁸ to ²²¹ are set to (MSS). 38 signals are input to the decoder 16.

Therefore, the switching mechanism (G0 to G11) in Figure 3
10-12 and switching mechanism (G8-G11) 1 in Figure 5
2, it is possible to easily expand or reduce the maximum storage capacity by switching the memory block from 64K bytes to 256K bytes, or from 64K bytes to 16K bytes, without changing the design of the control unit 3. , and can be expanded in block units. In addition, cases A and C in Figure 6,
As shown in D, the memory element chip is 16K bits/
Address data bit (ECS) 3 for word (row and column) selection in memory element array when chip
1 and (ERS) 42 bits, or (ECS)
If the 14 bits of 31 and (ERS) 32 are set not to be switched, the number of bits to be switched will be reduced from 12 bits to 4 or 5 bits. This reduces the amount of hardware and eliminates delays in word (row and column) selection address data in the storage element array, thereby preventing an increase in memory access time delays.

As explained above, according to the present invention, even when expanding or reducing the maximum storage capacity per memory block in an existing storage device, it is possible to expand or reduce the maximum storage capacity per memory block without changing the design of the common control unit. Since this can be done easily, users can replace storage element chips as semiconductor storage devices progress, which is extremely convenient.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining types of control methods in a storage device, FIG. 2 is a storage device block diagram of a control method to which the present invention is applied, and FIG. 3 is an address/data/data block diagram showing an embodiment of the present invention. A block diagram of a storage device equipped with a bit switching mechanism.
FIG. 5 is a block diagram of a storage device showing another embodiment of the present invention, and FIG. 6 is an explanatory diagram showing the use of address data bits in the storage device shown in FIG.・An explanatory diagram showing the usage of bits; FIG. 7 is a usage arrangement diagram of address data bits showing another embodiment of the present invention;
FIG. 8 is a block diagram of an address/data/bit switching mechanism showing an embodiment of the present invention. 1: Processor, 2: Storage device, 3: Control unit,
4: Memory block, 5: Interface, 10~
12: Address/data/bit switching mechanism, 1
3: Address/data register, 14: Multiplexer, 15, 16: Decoder, 17: MS selection signal line, 18: Element enable line, 19: Address/data bus, 20: AND gate, 2
1: Buffer gate, 22: Memory element chip.

Claims (1)

[Claims] 1. In a storage device having a plurality of memory blocks each containing a plurality of chips each constituted by a memory element array, and a control section that commonly controls the memory blocks, the control section has an address that is composed of a plurality of bits. An address data bit register for storing data bits, and a predetermined bit of the address data bits inputted from the address data register without going through a switching means to select word rows and word columns in the storage element array. a multiplexer for outputting word row address selection bits and word column address selection bits; a first bit array that does not overlap with the predetermined bits of the address data bits; A second bit array including bits not used for array selection is input, and a memory block to be used for specifying the memory block is selected according to a switching signal indicating expansion or reduction of the memory capacity of the memory block. signal above the first or second
means for generating and outputting from one of the bit arrays of the memory chip, and using the word row address selection bit and the word column address selection bit multiplexed with the memory block selection signal, the memory chip is A storage device characterized by selecting a storage element array.