JPH0332927B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a logic circuit, and particularly to a logic circuit that performs a flip-flop operation.

(Prior art) Conventionally, register files used in high-speed clock systems have achieved high speed by incorporating a read address register in order to shorten read time. If used with a medium speed clock, the read clock will take one extra cycle. Therefore, such a high-speed register file incorporating a read address register using a conventional delay type flip-flop has the drawback that it is difficult to use it for medium-speed applications.

(Object of the Invention) An object of the present invention is to provide a logic circuit that performs a flip-flop operation, which can eliminate the above-mentioned drawbacks.

(Structure of the Invention) The circuit of the present invention includes a first logical sum signal obtained by inputting a clock pulse signal and a control pulse signal, and calculating a logical sum of the clock pulse signal and an inverted signal of the control pulse signal, and an inverted signal of the clock pulse signal. a second logical sum signal obtained by logically adding the signal and an inverted signal of the control pulse signal, a first logical product signal obtained by logically multiplying the inverted signal of the clock pulse signal and the control pulse signal, and the clock pulse. signal supply means for outputting a second logical product signal obtained by logically multiplying the signal and the control pulse signal; a first AND means having an input terminal; a second AND means having first and second input terminals and into which the first AND signal is input; a first logical sum means having first and second input terminals to which respective outputs of the first and second logical product means are input, and supplies an output to a second input terminal of the second logical product means; and a third AND means having first and second input terminals to which the second OR signal and the output of the first OR means are input, respectively;
and a fourth AND means having a second input terminal, the second AND signal is input to the first input terminal, and each output of the third and fourth AND means is inputted, respectively. and a second OR means having first and second input terminals and providing an output to the second input terminal of the fourth AND means.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. This embodiment uses AND gates 1, 2, 4 and 5 each having two input terminals.
and OR (logical sum) gates 3 and 6 each having two input terminals, each output of AND gate 1 and AND gate 2 is input to the first and second input terminal of OR gate 3, respectively, The output of the OR gate 3 is fed back to the second input terminal of the AND gate 2 and is also input to the second input terminal of the AND gate 4.
and each output of the AND gate 5 is input to the first and second input terminals of the OR gate 6,
The output of OR gate 6 is fed back to the second input terminal of AND gate 5. The first input terminal of the AND gate 1 is input with a signal (CP+) which is the logical sum of the clock pulse (CP) and the inverted control pulse (), and the first input terminal of the AND gate 2 is input with the clock pulse (CP+). A signal (・T) which is the logical product of an inverted clock pulse () having a polarity opposite to the inverted control pulse (CP) and a control pulse (T) having a reverse polarity to the inverted control pulse () is input, and the AND gate 4 is inputted. A signal (+.) which is the logical sum of the inverted clock pulse ( ) and the inverted control pulse ( ) is inputted to the first input terminal, and the clock pulse (CP ) and the control pulse (T) is inputted, and a desired signal D is inputted to the second input terminal of the AND gate 1.

Next, the operation of this embodiment will be explained. First, considering the case where the control pulse (T) is logic "1", this embodiment operates in exactly the same way as the circuit shown in FIG. 2. This circuit performs a delayed flip-flop operation according to the truth table shown in FIG. In other words, the value of input D at the time when the clock pulse (CP) changes from logic "1" to "0" appears at the output Q, and when the clock pulse (CP) is in any other state, the value of the input D appears at the output Q. Regardless, the value of Q determined as described above is maintained.
On the other hand, when the control pulse (T) is logic "0", the value of the input D appears at the output Q as is. That is, it operates in a through mode according to the truth table shown in FIG. As is clear from the table, the value of input D appears unchanged at output Q, regardless of the value of the clock pulse (CP). In this way, it is possible to realize a flip-flop circuit that operates in the delay type flip-flop mode when the control pulse (T) is set to logic "1", and operates in the through mode when the control pulse (T) is set to logic "0". Note that the OR control signal (CP+) applied to the first input terminal of AND gate 1
and the AND control signal (CP/T) applied to the first input terminal of AND gate 2, the OR control signal (CP+T) applied to the first input terminal of AND gate 4, and the first input terminal of AND gate 5. AND control signal (CP/T) added to
can be supplied from the circuit shown in FIG. 5 or a circuit that operates equivalently.

(Effects of the Invention) Hereinafter, since the present invention can be used by freely switching between the delayed flip-flop mode and the through mode using the control pulse, it is possible to use the readout mode of the register file, etc. as described above. As an address register, one type of register file can be used for both high-speed and low-speed applications by adjusting the clock speed and operating it as a delay type flip-flop when the clock speed is high, and using through mode when the clock speed is low. There is an effect that it can be done.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram for explaining the operation of this embodiment, FIGS. 3 and 4 are diagrams showing truth values used for explaining the operation of this embodiment, and FIG. 5 is a diagram of a circuit added to this embodiment. It is a circuit diagram. In the figure, 1, 2, 4, 5...and gate, 3, 6...or gate.

Claims (1)

[Claims] 1. A first logical sum signal obtained by inputting a clock pulse signal and a control pulse signal and calculating a logical sum of the clock pulse signal and an inverted signal of the control pulse signal, an inverted signal of the clock pulse signal and an inverted signal of the control pulse signal. a second logical sum signal obtained by calculating the logical sum of the inverted signal of the clock pulse signal and the control pulse signal; and a logical product of the clock pulse signal and the control pulse signal. and a first AND means having first and second input terminals to which the first AND signal and a desired input signal are respectively input. and a second logical product means having first and second input terminals, into which the first logical product signal is inputted to the first input terminal, and each of the first and second logical product means. a first OR means having first and second input terminals to which outputs are input, respectively, and providing an output to a second input terminal of the second AND means; and a second OR signal, respectively. and a third AND means having first and second input terminals to which the output of the first OR means is input;
and a fourth AND means having a second input terminal, the second AND signal is input to the first input terminal, and each output of the third and fourth AND means is inputted, respectively. and second OR means having first and second input terminals, and providing an output to the second input terminal of the fourth AND means.