JPH0334097B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an initial state setting device that sets an electronic circuit to an initial state when power is turned on.

Conventionally, electronic watches have been equipped with an automatic AC circuit using a CR circuit in order to perform all-clear processing such as clearing RAM (random access memory) and display contents when the power is turned on when the battery is stored. The power supply voltage rises due to
That is, it detects that the battery is installed, performs all-clear processing, and sets the electronic circuit to its initial state.

However, automatic AC circuits using CR circuits
It has the disadvantage that it may malfunction due to fluctuations in the power supply voltage, and is less reliable. That is,
If the capacity of C in the CR circuit is small, even if the installed battery comes off the electrode terminal at a momentary point due to an external impact, etc., the battery will not be installed in the same way as when replacing the battery. This has the disadvantage that it detects this and performs all-clear processing on the electronic circuit. Normally, in order to prevent electronic circuits from being affected by such instantaneous power interruptions, for example, a small capacitor is placed in parallel with the electronic circuit, and by providing such a small capacitor, The problem is that even if the battery is momentarily disconnected, the automatic AC circuit will automatically operate and perform an all-clear process even though the internal data of the electronic circuit is not damaged in any way. Therefore, if the capacitance of C in the CR circuit is increased to ensure reliability, the capacitor cannot be incorporated into the LSI (Large Scale Integrated Circuit) and must be externally attached to the LSI.

This invention was made to solve the above-mentioned problems, and its purpose is to provide an initial state setting device that operates reliably even with fluctuations in power supply voltage and does not require external components. It's about doing.

Hereinafter, the present invention will be specifically explained based on an embodiment shown in the drawings. Note that this embodiment is applied to an electronic watch with a translation function, and this electronic watch executes timekeeping operations according to a microprogram. In the figure, reference numeral 1 denotes an oscillation circuit that oscillates and outputs a reference clock signal, and the reference clock signal is input to a frequency dividing circuit 2 and frequency-divided. This frequency dividing circuit 2 outputs 1/16Hz and 1/32Hz from its predetermined frequency dividing stage.
It outputs a Hz signal, and the 1/16Hz signal is SR.
It is applied to the set input terminal S of the type flip-flop 3. Therefore, flip-flop 3 is 1/16
It is set every second, and its set output Q is input to the address section 5 via the AND gate 4, causing the address section 5 to output address data. This address data is output to the ROM (read only memory) 6 and specifies the address of the ROM 6. ROM 6 contains microprograms and 4 that control all operations of this electronic clock.
type of numerical data (for example, 2 bits of 4-bit data)
(digital data) is fixedly stored, and the address is changed according to the address specification in the address field.
Outputs AD, operation code OP, data DA, and next address data NA in parallel.
Address AD is output to RAM7, and RAM
Specify the address of 7. This RAM 7 is composed of various registers, including display and calculation registers, a clock data storage register, N1 to N4 registers that store four types of numerical data (for example, 4-bit binary data), and flags. It has storage areas F1, F2, etc.

In addition, the operation code OP is various command data, which is given to the operation decoder 8 and decoded, and is sent to the RAM 7 as a read/write signal R/W, an operation command C, a display command d, an input command e, etc. A control signal is generated and output from the operation decoder 8. Data DA
is given to the RAM 7 and the arithmetic section 9, and the next address NA is given to the address section 5, which causes the address section 5 to output an address and designate the next process following the process currently being executed.

The RAM 7 executes read or write operations in accordance with the read/write signal R/W from the operation decoder 8. The data read from the RAM 7 is then given to the arithmetic unit 9 and subjected to a predetermined arithmetic operation.

The calculation unit 9 performs a time measurement calculation according to the calculation command C.
Execute judgment calculations, etc. The above time measurement operation is performed in the address section 5 by the output of the AND gate 4 (i.e., 1/16
is executed every time a second period signal) is given,
+1 to the previous clock data input from RAM6
New timekeeping data is obtained by calculating seconds, and the new timekeeping data is transferred to the timekeeping data storage register of the RAM 7, and is also sent to the display unit 10 for digital display. In addition, the above judgment operation is to judge whether or not the numerical data stored in the N1 to N4 registers of the RAM 7 and the numerical data A to D fixedly stored in the ROM 6 match. Along with the calculation, judgment result data a and carry signal b are outputted and applied to the address section 5, which causes the address section 5 to output address data according to the contents. Furthermore, the calculation section 9
Key input data is given from the input section 11. The input unit 11 is provided with keys related to the clock function, such as a time adjustment key, as well as keys related to the translation function, such as an alphanumeric key.

Further, the operation decoder 8 applies a reset signal to the reset input terminal R of the SR type flip-flop 3, and also applies an OR gate 13 to the set input terminal S of the SR type flip-flop 12, which inputs the set output Q to the AND gate 4 as a gate control signal. Further, a reset signal is applied to the reset input terminal R of the SR type flip-flop 12 and the reset input terminal R of the timer circuit 14, respectively.

The timer circuit 14 is composed of, for example, a hexadecimal counter, and counts the 1/22 Hz signal inputted from the frequency dividing circuit 2, and outputs the SR type flip-flop 1 via the carry signal OR gate 13.
2 set input terminal S.

Next, the operation of the above embodiment will be explained with reference to the flowchart shown in FIG. When the battery is installed and the power is turned on, the frequency divider circuit 2 starts frequency dividing operation, outputs a 1/16 Hz signal from the time the power is turned on, and sets the flip-flop 3. When the set output Q of the flip-flop 3 is applied to the address section 5 via the AND gate 4, the ROM 6 executes the flow shown in FIG. 2 in accordance with the address data output from the address section 5.

That is, first, execute the process of step S1,
Reset flip-flop 3. Next, steps S2 to S5 are executed sequentially, and N1 to N4 of RAM7 are
Numerical data stored in registers and ROM
The numerical data A to D fixedly stored in the register 6 are sequentially read out and sent to the arithmetic unit 9, and it is checked whether they match or not. ₂ register data and data B, N in step S4 ₃ register data and data C, N4 in step S5
A determination is made as to whether the data in the register and data D match. In the present case (when the power is turned on), uncertain values are stored in registers N1 to N4, and the probability of a match being determined in all steps S2 to S5 is extremely small and approximately equal to zero. That is, the data of registers N1 to N4 and data A to
D is 4-bit data of "0 to 15 (decimal number)", and the probability of a match being determined in each step S2 to S5 is 1/16, so all steps S2 to S5 are
The probability of each being judged as a match in S5 is (1/16) ⁴ ,
Almost equal to zero. Therefore, when the power is turned on,
It is determined that there is no match (NO) in steps S2 to S5, and the process proceeds to step S6. In steps S6 to S9, processing is executed to set corresponding fixed data A to D in the ROM 6 in registers N1 to N4. That is, in step S6, data A is stored in the N1 register, and in step S7, data B is stored in the N2 register.
In step S8, data C is set in the N3 register, and in step S9, data D is set in the N4 register. Next, the process proceeds to step S10, where an all clear process is executed to clear a predetermined register of the RAM 7, a display register of the display unit 10, etc. That is, the electronic circuit is set to an initial state.

Next, the process advances to step S11, where it is determined whether the contents of the flag storage area F2 of the RAM 7 are "0" or "1". In this case, the content of the flag storage area F2 is "0", so the process advances to the next step S12.
In this step S12, it is determined whether the contents of the flag storage area F1 are "0" or "1". In this case,
Since the content of flag storage area F1 is "0"
Move to HALT (standby) state.

In this HALT state, when the next 1/16 Hz signal is output from the frequency divider circuit 2, the flip-flop 3 is set, and address data is output from the address section 5 in accordance with the set output Q. As a result, steps S1 to S5 are executed again. In this case, data A to D are stored in registers N1 to N4, so each step S2 to
In S5, it is determined that they match (YES), and the process proceeds to the next step S13. This step S13 is a flow for executing timekeeping processing, and timekeeping processing such as timekeeping operation, key input processing, display processing, etc. is performed. At this time, it is determined in step S14 whether additional function processing (translation function processing) has been designated by key input in the input unit 11. When the translation function process is specified, the process advances to the next step S15, sets "1" in the flag storage area F1, and then returns to step S15.
The process moves to translation function processing via S11 and S12. Also,
If it is determined in step S15 that translation function processing is not specified, steps S11 and S12 are performed.
It enters HALT state via .

However, when moving on to translation function processing, the step
Proceeding to S16, "1" is set in the flag storage area F2. Next, process A, which is part of the translation function process.
Proceed to step S17 to execute. This process A is
This is a process that can be interrupted at any time, and if a 1/16 Hz signal is output from the frequency divider circuit 2 during this process, the interrupt process returns to step S1 again and normal processes such as timekeeping process are performed. At this time, the content of the flag storage area F2 remains "1", so after executing the time measurement process, it becomes a return interrupt (REI) and returns to the next address where the interrupt occurred, and the rest of process A is executed. Execute processing.

Then, when processing A is finished, the next step
After proceeding to S18 and resetting the flip-flop 12, the process proceeds to step S19 in which another process B of the translation function process is executed. This process B is different from process A, and is a process that cannot be interrupted.
Before executing the process B, the flip-flop 12 is reset and the AND gate 4 is closed to prevent an interrupt from occurring during the program execution of process B. At the same time, the timer circuit 14 is also reset.

Then, when processing B is completed, the next step
Proceed to S20, set flip-flop 12,
Set to allow interrupts. Note that the timer circuit 14 counts the time during which process B is being executed, and if process B does not end even if this time exceeds a predetermined time, it is determined that the program being executed has run out of control, and the timer circuit 14 counts the time during which process B is being executed. A carry signal output from the flip-flop 12
is forcibly set, the state becomes interruptible, and the process returns to step S1.

Next, the process moves to step S21, and the remaining processing C of the translation function is executed. This process C is also process A
This is a process that can be interrupted in the same way as . Processing C
When the process is completed, the process advances to step S22, where "0" is set in the flag storage area F1, and then step S22 is started.
Proceeding to S23, "0" is set in the flag storage area F2. Then, when step S23 ends,
It is kept in HALT state.

In this way, since the CR circuit is not used to set the initial state of the electronic circuit, it operates reliably even in the face of fluctuations in power supply voltage, and no external components are required.

In the above embodiment, four types of data in the N1 to N4 registers are compared with the fixed data stored in the ROM, but if the number of bits of the numerical data to be compared is increased, one type of data can be used. It may be.

As explained in detail above, this invention compares arbitrary data preset in a first storage means from which data can be read and written with fixed data in a second storage means that stores data in a fixed manner. hand,
Since the electronic circuit is set to the initial state when the arbitrary data and fixed data do not match, a CR circuit is not used to detect power-on, so even if the power supply voltage fluctuates, it is reliable. It has excellent effects such as high performance, no external parts required, and cost advantages.

[Brief explanation of the drawing]

The drawings show an embodiment in which the present invention is applied to an electronic timepiece. FIG. 1 is a block circuit diagram of the electronic timepiece, and FIG. 2 is a flowchart showing its operation. 2... Frequency divider circuit, 6...ROM, 7...RAM,
9... Arithmetic circuit.

Claims (1)

[Claims] 1 An initial state setting device for an electronic circuit that executes a predetermined process according to a microprogram each time a clock signal of a predetermined period is output, and includes a first storage means capable of reading and writing data, and a predetermined storage means. a second storage means for fixedly storing data stored in the clock signal; and a second storage means for storing data stored in a predetermined area of the first storage means each time the clock signal is output. a comparison means for comparing fixed data stored in the first memory; and a comparison means for setting the electronic circuit to an initial state and setting the electronic circuit to an initial state when the comparison means does not detect a match between the data and the fixed data. The method is characterized by comprising a setting means for storing and setting the fixed data in the predetermined area of the means, and a control means for causing the predetermined process to be executed when a match is detected by the comparing means. Initial state setting device.