JPH0334160B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory such as an ultraviolet erasable type.

[Conventional technology]

Traditionally, erasable non-volatile semiconductor memory (hereinafter referred to as
It's called EPROM. ) is a failure mode in which "0" data is erroneously written to a memory cell in which the bit line is selected but the word line is not selected. One way to screen out this type of failure mode is to actually write "0" data to memory cells on some word lines, and then test whether there is any erroneous writing to memory cells on the remaining word lines. be.

However, this conventional method has several drawbacks: ) Must be erased again to actually write "0" data. )
As the capacity of EPROM increases, the number of bit lines increases and the time required to write "0" data increases.
) It is not possible to test memory cells to which data has been written. etc.

[Purpose of the invention]

The purpose of the present invention is to improve the shortcomings of conventional test methods for the above-mentioned erroneous write failure mode, and to provide a non-volatile method that allows testing of all memory cells without actually writing data. Our goal is to provide semiconductor memory.

[Configuration of the present invention]

The nonvolatile semiconductor memory of the present invention includes a first circuit that deselects all word lines, and a second circuit that electrically disconnects all bit lines from the read circuit and the write circuit and applies a write voltage to the bit lines.
and a test signal detection circuit that detects an external test signal and controls the operations of the first and second circuits.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention, and shows the peripheral part of a memory cell.

In this embodiment, a first circuit 14 that deselects a word line 8 and a bit line 12 are electrically separated from a read circuit 10 and an N-channel transistor (hereinafter referred to as NMOST) 1 for inputting write data. A second circuit 15 applies a write voltage to this bit line 12, and a test signal detection circuit detects an external test signal 13 and sends out a test signal 11 that controls the operation of the first and second circuits 14 and 15. The circuit 9 includes a circuit 9. The first circuit 14 is added to every word line, and the second circuit 15 is added to every bit line, and as a result, they are added to every memory cell.

The first circuit 14 consists of an NMOST 4 whose drain is connected to the word line 8, whose source is connected to the ground potential, and whose gate is connected to the test signal 11.

The drain of the second circuit 15 is the Y decoder output.
NMOST 2 whose source is connected to the ground potential, gate connected to the test signal 11 output from the test signal detection circuit 9, buffer 7 whose input is connected to the test signal 11, drain connected to the bit line 12, and source connected to the bit line 12. It consists of NMOST3 whose gates are respectively connected to the write voltage terminal VPP (the write voltage is VPP) and the output of the buffer 7.

The memory cell 6 is composed of an N-channel nonvolatile memory transistor, and has a drain connected to the bit line 12, a source connected to the ground potential, and a gate connected to the word line 8.
and the bit line 12 has a gate connected to Y
For selecting bit line connected to decoder output Yi
The NMOST 5 is connected to the write voltage terminal VPP via the write data input NMOST1 whose gate is connected to the write signal Di, and the read circuit 10 is connected to the drain of the NMOST5.

Next, the operation of this embodiment will be explained.

Ao is normally an address signal input terminal, but 7V
When the above voltage is applied, the test signal detection circuit 9 operates and outputs a high level test signal 11.
NMOST4 turns on and X decoder output
Since Xi becomes low level, word line 8 becomes unselected. At the same time, NMOST2 is also turned on, so the Y decoder output Yi becomes low level.
NMOST5 turns off. Therefore, memory cell 6 is separated from read circuit 10 and write data input transistor 1. The test signal 11 is also input to the buffer 7, which outputs a voltage close to the write voltage VPP, turns on the NMOST3, and applies a voltage close to the write voltage VPP to the bit line 12.

As mentioned above, a first circuit 14 for every word line and a second circuit 15 for every bit line.
is added, all word lines are deselected and write voltages are applied to all bit lines. At this time, all memory cells are in a data unwritten state, but data "0" is written to defective memory cells as described in the above-mentioned prior art.

Next, the level of address input signal terminal Ao is 0~
When the voltage returns to 5V, the test signal detection circuit 9 outputs a low level test signal 11.
NMOST2, 3, 4 are turned off, normal writing,
Reading becomes possible. If a defective memory cell is included, it is no longer possible to read "1" data, so defective products are selected.

That is, according to this embodiment, there is no need to take the trouble to write "0" data in order to detect defective memory cells as in the prior art, and it is possible to test all memory cells.

Note that in the above embodiments, an N-channel MOS transistor was used as the transistor, but
It goes without saying that similar effects can be obtained by using a P-channel MOS transistor.

〔Effect of the invention〕

As explained above, according to the present invention, a first circuit that deselects all word lines, and a first circuit that electrically disconnects all bit lines from the read circuit and the write circuit and applies a write voltage to all bit lines. It has a second circuit for applying a test signal and a test signal detection circuit for detecting a test signal from the outside. When this test signal detection circuit detects a test signal, the first and second circuits operate and all The word line is deselected and a write voltage is applied to all bit lines, "0" data is written to the defective memory cell, and a "1" data read test is performed to select defective products. A non-volatile semiconductor memory is obtained in which it is possible to do this, and its effects are significant.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention. 1 to 5...N channel MOS transistor, 6...
Memory cell, 7... Buffer, 8... Word line, 9...
Test signal detection circuit, 10...Readout circuit, 11...
Test signal, 12...Bit line, 13...Test signal, 14...First circuit, 15...Second circuit, Ao
...Address input signal terminal, VPP...Write voltage terminal, Xi...X decoder output, Yi...Y decoder output.

Claims (1)

[Claims] 1 A first circuit that deselects all word lines, a second circuit that electrically disconnects all bit lines from the read circuit and write circuit and applies a write voltage to the bit lines, and an external test. A nonvolatile semiconductor memory comprising: a test signal detection circuit that detects a signal and sends out a test signal for controlling operations of the first and second circuits.