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JPH0334236B2 - - Google Patents
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JPH0334236B2 - - Google Patents

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Publication number
JPH0334236B2
JPH0334236B2 JP61024966A JP2496686A JPH0334236B2 JP H0334236 B2 JPH0334236 B2 JP H0334236B2 JP 61024966 A JP61024966 A JP 61024966A JP 2496686 A JP2496686 A JP 2496686A JP H0334236 B2 JPH0334236 B2 JP H0334236B2
Authority
JP
Japan
Prior art keywords
superconducting
electrode
integrated circuit
metal film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61024966A
Other languages
Japanese (ja)
Other versions
JPS62183573A (en
Inventor
Mikio Hirano
Hideaki Nakane
Yoshinobu Taruya
Ushio Kawabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP61024966A priority Critical patent/JPS62183573A/en
Publication of JPS62183573A publication Critical patent/JPS62183573A/en
Publication of JPH0334236B2 publication Critical patent/JPH0334236B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、超電導集積回路用端子電極に係り、
特にジヨセフソン接合素子を搭載した超電導集積
回路の外部接続に用いる超電導突起電極用下地金
属膜に関するものである。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a terminal electrode for a superconducting integrated circuit,
In particular, the present invention relates to a base metal film for a superconducting bump electrode used for external connection of a superconducting integrated circuit equipped with a Josephson junction element.

〔発明の背景〕[Background of the invention]

トンネル型ジヨセフソン接合素子は、2つの超
電導薄膜の間に厚さ数nmの極めて薄い絶縁膜を
挾んだサンドイツチ構造で、極低温(〜4K)に
おける超電導トンネル現象を応用したスイツチン
グ素子である。この素子は、従来の半導体素子に
比べ、スイツチング速度は約1桁早く、消費電力
は約3桁小さいという特長があり、将来の超高速
計算機用の論理演算素子、記憶素子として期待さ
れている。これらの素子を構成するための超電導
薄膜には、主にPb合金、Nb、NbNなどが用いら
れている。また極薄のトンネル障壁層にはPb及
びInの酸化物あるいはNbの酸化物が用いられて
いる。ところでこれらのジヨセフソン接合素子を
超高速計算機用の素子として用いるためには、そ
れらをLSIレベルに集積化したチツプを多数用い
て実装し、モジユール化した論理演算回路、記憶
回路を開発する必要がある。LSIチツプをモジユ
ール基板に実装する場合、留意すべきことは、 (1) 超電導LSIチツプと他の超電導LSIチツプを
配線を介して接続する場合、それの配線、接続
用電極(入、出力信号の取出し電極)は、全て
超電導金属で構成する必要のあること。
A tunnel-type Josephson junction device has a sandwich structure in which an extremely thin insulating film several nanometers thick is sandwiched between two superconducting thin films, and is a switching device that applies the superconducting tunnel phenomenon at extremely low temperatures (~4K). This device has a switching speed that is about one order of magnitude faster and a power consumption that is about three orders of magnitude lower than conventional semiconductor devices, and is expected to be used as a logic operation element and a memory element for future ultra-high-speed computers. Pb alloys, Nb, NbN, etc. are mainly used for the superconducting thin films used to construct these devices. In addition, oxides of Pb and In or oxides of Nb are used for the extremely thin tunnel barrier layer. By the way, in order to use these Josephson junction devices as devices for ultra-high-speed computers, it is necessary to implement them using a large number of chips integrated at the LSI level and to develop modular logic operation circuits and memory circuits. . When mounting an LSI chip on a module board, the following points should be kept in mind: (1) When connecting a superconducting LSI chip to another superconducting LSI chip via wiring, the wiring and connection electrodes (input and output signal All of the lead-out electrodes must be made of superconducting metal.

(2) 超電導LSIチツプの端子電極上に形成する接
続用突起電極(バンプ)は十分な接着強度を有
すること。
(2) The connecting protruding electrodes (bumps) formed on the terminal electrodes of the superconducting LSI chip must have sufficient adhesive strength.

(3) LSIチツプの実装基板へのボンデイングは薄
膜のトンネル障壁層の劣化防止のため極力低温
で行う必要がある。その際LSIチツプとモジユ
ール基板とのボンデイング強度は、300〜4Kの
熱サイクルに十分耐えるだけの強度を有するこ
と。
(3) Bonding of the LSI chip to the mounting board must be performed at as low a temperature as possible to prevent deterioration of the thin tunnel barrier layer. In this case, the bonding strength between the LSI chip and the module board must be strong enough to withstand thermal cycles of 300 to 4K.

などである。etc.

従来、LSIチツプと外部電極との接続はAl電極
−Al細線による超音波ワイヤボンデイング、Au
電極−Au細線、Al電極−Au細線による熱圧着ワ
イヤボンデイング、Au電極−Snメツキリードあ
るいは半田電極−半田電極によるリフローボンデ
イングなどが使用されている。これらの方法のう
ち、超電導LSIの組立に適用が可能な方法は、半
田電極によるリフローボンデイングである。これ
は半田電極自身が超電導特性を示すこと、またチ
ツプ実装による配線長は他の方法に比べ短くで
き、高密度実装に適しているなどによる。半田電
極を用いたリフローボンデイング方式を超電導
LSIチツプの実装基板への搭載法として採用した
場合次のような問題が生ずる。すなわち前述の突
起電極を超電導LSIの端子部に形成する場合、機
械的に十分な大きさの接着強度が得られ、かつ電
気的には超電導接続が要求される。一般に突起電
極と超電導LSIの端子部の間に接続用金属膜(突
起電極下地金属膜)を設けている。そのような金
属膜はAu/Pd膜(上層Au、下層Pd)が用いら
れている。(シイー・ワイ・テイング他、ジヤー
ナル・オブ・エレクトロケミカル・ソサイアテ
イ:ソリツド−ステート・サイエンス・アンド・
テクノロジー 第129巻、第4号(1982)〔C.Y.
Ting et al J.Electrochem.Soc.:Solid−State
Science and Technology Vol.129、No.4
(1982)〕。Au膜は突起電極と下地のPd膜、Pd膜
は超電導LSIチツプに設けた端子電極(一般に
Nb膜を用いる)との接着及び突起電極材がLSI
チツプの端子電極内部に拡散するのを防止する役
割を各々担つている。超電導LSIに使用している
Pb/Au二層膜の厚さは夫々100nmである。この
二層膜は極低温(〜4K)では超電導特性を示さ
ないため、わずかな抵抗(コンタクト抵抗)を示
し、ジユール熱による発熱が生ずる。このため極
低温冷媒である液体ヘリウムが気化して発泡し、
超電導LSIの冷却効率を低下させる原因になる。
またそのようなコンタクト抵抗があるため、高速
で伝送される信号の波形に歪みが生じ、超電導の
高速伝搬特性が低下するなど問題になる。このよ
うな問題を改善するには、突起電極用下地膜に超
電導特性を示す接続用金属膜を使用する必要があ
る。
Conventionally, connections between LSI chips and external electrodes were made using ultrasonic wire bonding using Al electrodes and thin Al wires, or using Au.
Thermocompression wire bonding using an electrode-Au thin wire, Al electrode-Au thin wire, reflow bonding using an Au electrode-Sn plating lead, or a solder electrode-solder electrode, etc. are used. Among these methods, the method applicable to superconducting LSI assembly is reflow bonding using solder electrodes. This is because the solder electrode itself exhibits superconducting properties, and because chip mounting allows for shorter wiring lengths than other methods, it is suitable for high-density mounting. Superconducting using reflow bonding method using solder electrodes
If this method is used to mount an LSI chip on a mounting board, the following problems will occur. That is, when forming the above-mentioned protruding electrodes on the terminal portions of a superconducting LSI, it is necessary to obtain a mechanically sufficient adhesive strength and to electrically make a superconducting connection. Generally, a metal film for connection (metal film underlying the protruding electrode) is provided between the protruding electrode and the terminal portion of the superconducting LSI. As such a metal film, an Au/Pd film (upper layer Au, lower layer Pd) is used. (C.Y. Taing et al., Journal of Electrochemical Society: Solid State Science and
Technology Volume 129, No. 4 (1982) [CY
Ting et al J.Electrochem.Soc.:Solid−State
Science and Technology Vol.129, No.4
(1982)]. The Au film is the protruding electrode and the underlying Pd film, and the Pd film is the terminal electrode (generally used) provided on the superconducting LSI chip.
Adhesion with (using Nb film) and protruding electrode material are LSI
Each plays a role in preventing diffusion into the terminal electrodes of the chip. Used in superconducting LSI
The thickness of each Pb/Au bilayer film is 100 nm. Since this two-layer film does not exhibit superconducting properties at extremely low temperatures (~4K), it exhibits a slight resistance (contact resistance) and generates heat due to Joule heat. As a result, liquid helium, a cryogenic refrigerant, vaporizes and foams.
This causes a decrease in the cooling efficiency of superconducting LSI.
In addition, such contact resistance causes distortion in the waveform of signals transmitted at high speed, resulting in problems such as deterioration of the high-speed propagation characteristics of superconductors. In order to improve such problems, it is necessary to use a connecting metal film exhibiting superconducting properties as the base film for the protruding electrodes.

〔発明の目的〕[Purpose of the invention]

本発明は、前述の問題点を解消するためになさ
れたもので、その目的は機械的に十分な大きさの
接着強度が得られ、コンタクト抵抗の生じない突
起電極下地金属膜を提供することにある。
The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a metal film underlying protruding electrodes that has a mechanically sufficient adhesive strength and does not cause contact resistance. be.

〔発明の概要〕[Summary of the invention]

本発明は、超電導集積回路から延在された端子
電極面に、突起電極接着用の下地金属膜を端子電
極面に対して部分的に、例えば島状に散在させて
形成し、超電導電極面と下地金属膜を混在させ、
超電導電極面と突起電極の接続界面では、超電導
コンタクトを、一方下地金属膜は超電導電極と突
起電極の間の接着強度維持を、各々同時に達成さ
せようとするものである。以上述べた方法によ
り、超電導集積回路の端子電極と、接続用の突起
電極の間の超電導臨界電流は、少くとも600mA
以上、突起電極の接着強度は剪断強度で少くとも
50g以上が得られることが判明した。
The present invention forms a base metal film for bonding protruding electrodes on a terminal electrode surface extending from a superconducting integrated circuit by scattering it partially, for example, in the form of islands, so that the superconducting electrode surface and Mixing the base metal film,
At the connection interface between the superconducting electrode surface and the protruding electrode, a superconducting contact is established, while the underlying metal film is intended to maintain the adhesive strength between the superconducting electrode and the protruding electrode at the same time. By the method described above, the superconducting critical current between the terminal electrode of the superconducting integrated circuit and the protruding electrode for connection is at least 600 mA.
As mentioned above, the adhesive strength of protruding electrodes is at least the shear strength.
It was found that more than 50g could be obtained.

なお前記突起電極を形成する超電導集積回路の
端子部に形成する下地金属膜は、前述のような島
状に点在させる方法のほか、格子縞状に形成する
方法もあり、接着界面の超電導臨界電流、接着強
度共に十分初期の目的を達成できることを確認し
た。
The base metal film formed on the terminal part of the superconducting integrated circuit that forms the protruding electrodes can be dotted in the form of islands as described above, or it can be formed in the form of a lattice stripe to reduce the superconducting critical current at the adhesive interface. It was confirmed that both adhesive strength and adhesive strength were sufficient to achieve the initial objectives.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を第1図〜第4図により
詳細に説明する。
Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 4.

実施例 1 あらかじめ清浄化処理したシリコン単結晶基板
1上に熱酸化により厚さ約600nmのSiO2層2を
形成する。再び基板を清浄化処理したのち、真空
装置内に入れ、5×10-8Torr以下の高真空中で
Nbを約300nmの厚さに蒸着する。なお、Nb膜は
前述の真空蒸着法のほかにスパツタ法によつても
良い。つぎにフオトエツチング法によりNbを所
望のパターンに加工し、グランドプレーン3を形
成する。化学エツチング法では、一般にHF−
HNO3混合液が、また物理エツチング法では、
Ar、CF4などの反応性イオンエツチング法を用い
る。このグランドプレーンは、超電導LSIの能動
素子部に形成したジヨセフソン接合のための外部
磁気の遮へいの効果、及び制御線から発生する磁
束のミラー効果のほか、LSI内のアース端子、な
らに突起電極用の端子4の役割を担う。つぎに前
述のNb膜上の、アース端子部及び突起電極形成
領域を除いたそれ以外のNb膜上に第1層間絶縁
膜5を形成する。つぎにMoNx膜からなる抵抗
6を、さらにNb/NbN二層膜からなる配線接続
層7及び下部電極膜8を形成する。つぎにSiO膜
からなる第2層間絶縁膜9を形成する。その際下
部電極の一部に開口部を設けNbN面を露出させ
る。つぎにプラズマ酸化法により開口部のNbN
下部電極表面にトンネル障壁層10の形成し、引
続いてPb合金からなる上部電極11を形成する。
さらにSiO膜からなる第3層間絶縁膜12を、つ
づいて制御線13及び第4層間絶縁膜14を形成
する。つぎに突起電極用の端子4のNb表面の所
望の領域に、リフトオフ用のレジストパターンを
島状に散在させ形成する。ついでTi21を100n
m、Pd22を200nm、更にAu23を300nm堆積
させたうえリフトオフを行い、突起電極用端子部
4上の所望の部分にTi−Pd−Au膜15を形成す
る(第2図および第3図参照)。その後、前記突
起電極用端子部4を露出させて突起電極形成用レ
ジストテンシルパターンを形成する。つぎにTi
−Pd−Au膜が形成されていないNb表面の清浄
化のため10-3Torrに減圧されたAr雰囲気中でrf
スパツタエツチングを行つた。rf放電電圧は
250Vp−p、放電時間は30分間である。その後引
続いて突起電極の材料であるPb、Sn、Biを順次
蒸着する。蒸着は10-7Torr以下の真空中で行い、
直径は150μmφ、蒸着膜厚は30μmとした。つい
でリフトオフを行い不用部分の蒸着膜を除去した
のち、基板1を5%の水素ガスを含む窒素ガス雰
囲気中で200℃に加熱し、前記突起電極材をリフ
ローさせ、表面張力を利用して半球状の突起16
とした。なお、球状の突起電極の直径はおよそ
100μmである。
Example 1 A SiO 2 layer 2 with a thickness of about 600 nm is formed by thermal oxidation on a silicon single crystal substrate 1 that has been previously cleaned. After cleaning the substrate again, it is placed in a vacuum device and placed in a high vacuum of 5×10 -8 Torr or less.
Nb is deposited to a thickness of about 300 nm. Note that the Nb film may be formed by a sputtering method in addition to the above-mentioned vacuum evaporation method. Next, the Nb is processed into a desired pattern by photoetching to form a ground plane 3. In the chemical etching method, HF-
HNO 3 mixed solution and physical etching method
A reactive ion etching method such as Ar or CF 4 is used. This ground plane has the effect of shielding external magnetism for the Josephson junction formed in the active element part of the superconducting LSI, and the mirror effect of the magnetic flux generated from the control line. It plays the role of terminal 4. Next, a first interlayer insulating film 5 is formed on the Nb film described above except for the ground terminal portion and the protrusion electrode formation region. Next, a resistor 6 made of a MoNx film, and a wiring connection layer 7 and a lower electrode film 8 made of a Nb/NbN double layer film are then formed. Next, a second interlayer insulating film 9 made of a SiO film is formed. At this time, an opening is provided in a part of the lower electrode to expose the NbN surface. Next, plasma oxidation is used to remove NbN at the opening.
A tunnel barrier layer 10 is formed on the surface of the lower electrode, and subsequently an upper electrode 11 made of a Pb alloy is formed.
Furthermore, a third interlayer insulating film 12 made of a SiO film, followed by a control line 13 and a fourth interlayer insulating film 14 are formed. Next, a resist pattern for lift-off is formed in a desired region on the Nb surface of the terminal 4 for the protruding electrode in an island-like manner. Then Ti21 for 100n
After depositing 200 nm of Pd22 and 300 nm of Au23, lift-off is performed to form a Ti-Pd-Au film 15 at a desired portion on the protruding electrode terminal section 4 (see Figs. 2 and 3). . Thereafter, the protruding electrode terminal portion 4 is exposed to form a resist tencil pattern for forming protruding electrodes. Next, Ti
−RF in Ar atmosphere at reduced pressure to 10 -3 Torr to clean the Nb surface on which no Pd−Au film is formed.
I did spatuta etching. The rf discharge voltage is
250Vp-p, discharge time is 30 minutes. Thereafter, Pb, Sn, and Bi, which are materials for the protruding electrodes, are sequentially deposited. Vapor deposition is performed in a vacuum below 10 -7 Torr.
The diameter was 150 μmφ, and the deposited film thickness was 30 μm. Next, after performing lift-off to remove unnecessary portions of the deposited film, the substrate 1 is heated to 200°C in a nitrogen gas atmosphere containing 5% hydrogen gas, and the protruding electrode material is reflowed to form a hemisphere using surface tension. shaped protrusion 16
And so. The diameter of the spherical protruding electrode is approximately
It is 100 μm.

以上述べた方法により作製した突起電極下地金
属膜を用いた場合の超電導集積回路の電極端子と
の接続は、4.2Kの極低温下で超電導状態を示し
た。100μm□内の端子部に40μm2および30μm2
下地金属膜を各々5個及び4個形成した場合、得
られた超電導臨界電流は700mAであり、また突
起電極1個当りの剪断強度は60gが得られた。
Connection with electrode terminals of a superconducting integrated circuit using the protruding electrode base metal film produced by the method described above exhibited a superconducting state at an extremely low temperature of 4.2K. When 5 and 4 base metal films of 40 μm 2 and 30 μm 2 are formed on the terminal area within 100 μm square, the obtained superconducting critical current is 700 mA, and the shear strength per protruding electrode is 60 g. Obtained.

尚、本実施例では下地金属膜を島状に散在させ
て形成したが、第4図に示すように、下地金属膜
を格子縞状に形成した場合でも同様の効果が得ら
れることを確認している。
In this example, the base metal film was formed in an island-like manner, but as shown in FIG. 4, it was confirmed that the same effect could be obtained even when the base metal film was formed in a checkered pattern. There is.

また、本実施例では下地金属膜材料としてTi
−Pd−Auについて示したが、Ti−Pd−Ag、Cr
−Cu−Au、Cr−Cu−Ag、などを用いても同じ
効果が得られることを確認している。
In addition, in this example, Ti is used as the underlying metal film material.
-Pd-Au is shown, but Ti-Pd-Ag, Cr
It has been confirmed that the same effect can be obtained using -Cu-Au, Cr-Cu-Ag, etc.

〔発明の効果〕〔Effect of the invention〕

以上説明したごとく、本発明によれば、超電導
LSIの外部接続用突起電極金属が安定に形成で
き、コンタクト抵抗ゼロの超電導特性を示し、し
かも接着強度の大きな電極構造が再現良く作製で
きるようになつた。
As explained above, according to the present invention, superconducting
It has become possible to stably form protruding electrode metals for external connections in LSIs, exhibit superconducting properties with zero contact resistance, and produce electrode structures with high adhesive strength with good reproducibility.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明に係る超電導LSIの外部接続
用突起電極部の断面図、第2図は改良された突起
電極下地金属膜の構造を示す断面図、第3図およ
び第4図は、突起電極下地金属膜の構造を示す平
面図である。 1……基板、2……絶縁層(SiO2層)、3……
グランドプレーン、4……超電導LSIの端子電
極、5……第1層間絶縁膜、6……抵抗、7……
配線層、8……下部電極、9……第2層間絶縁
膜、10……トンネル障壁層、11……上部電
極、12……第3層間絶縁膜、13……制御線、
14……第4層間絶縁膜、15,15′……突起
電極下地金属膜、21……Ti膜、22……Pd膜、
23……Au膜。
FIG. 1 is a cross-sectional view of a protruding electrode portion for external connection of a superconducting LSI according to the present invention, FIG. 2 is a cross-sectional view showing the structure of an improved protruding electrode base metal film, and FIGS. 3 and 4 are: FIG. 3 is a plan view showing the structure of a protruding electrode base metal film. 1...Substrate, 2...Insulating layer (SiO 2 layer), 3...
Ground plane, 4... terminal electrode of superconducting LSI, 5... first interlayer insulating film, 6... resistor, 7...
Wiring layer, 8... lower electrode, 9... second interlayer insulating film, 10... tunnel barrier layer, 11... upper electrode, 12... third interlayer insulating film, 13... control line,
14... Fourth interlayer insulating film, 15, 15'... Protrusion electrode base metal film, 21... Ti film, 22... Pd film,
23...Au film.

Claims (1)

【特許請求の範囲】 1 2つの超電導薄膜の間に極薄のトンネル障壁
層を挾んだサンドイツチ構造を主要素子とし、こ
の素子に超電導性の突起電極を接続してなる超電
導集積回路において、上記突起電極と超電導集積
回路の端子電極の間に突起電極接着用の下地金属
膜を上記端子電極面に対して部分的に形成し、上
記突起電極と上記端子電極とが部分的に直接接続
していることを特徴とする超電導集積回路。 2 特許請求の範囲第1項に記載の超電導集積回
路において、前記下地金属膜を、前記端子電極面
に島状に散在させて形成した超電導集積回路。 3 特許請求の範囲第1項に記載の超電導集積回
路において、前記下地金属膜を、前記端子電極面
に格子状に散在させて形成した超電導集積回路。 4 特許請求の範囲第2項若しくは第3項に記載
の超電導集積回路において、前記下地金属膜は前
記端子電極を露出させるために設けた絶縁開口部
に延在させ、この絶縁開口部を包囲して形成させ
た超電導集積回路。
[Scope of Claims] 1. A superconducting integrated circuit whose main element is a Sanderch structure in which an ultra-thin tunnel barrier layer is sandwiched between two superconducting thin films, and a superconducting protruding electrode is connected to this element. A base metal film for adhering the protruding electrode is partially formed on the terminal electrode surface between the protruding electrode and the terminal electrode of the superconducting integrated circuit, and the protruding electrode and the terminal electrode are partially directly connected. A superconducting integrated circuit characterized by: 2. The superconducting integrated circuit according to claim 1, wherein the base metal film is formed in an island-like manner scattered over the terminal electrode surface. 3. The superconducting integrated circuit according to claim 1, wherein the base metal film is formed so as to be scattered in a grid pattern on the terminal electrode surface. 4. In the superconducting integrated circuit according to claim 2 or 3, the base metal film extends into an insulating opening provided to expose the terminal electrode, and surrounds the insulating opening. A superconducting integrated circuit formed using
JP61024966A 1986-02-08 1986-02-08 Terminal electrode for superconducting integrated circuit Granted JPS62183573A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61024966A JPS62183573A (en) 1986-02-08 1986-02-08 Terminal electrode for superconducting integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61024966A JPS62183573A (en) 1986-02-08 1986-02-08 Terminal electrode for superconducting integrated circuit

Publications (2)

Publication Number Publication Date
JPS62183573A JPS62183573A (en) 1987-08-11
JPH0334236B2 true JPH0334236B2 (en) 1991-05-21

Family

ID=12152711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61024966A Granted JPS62183573A (en) 1986-02-08 1986-02-08 Terminal electrode for superconducting integrated circuit

Country Status (1)

Country Link
JP (1) JPS62183573A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS616882A (en) * 1984-06-21 1986-01-13 Agency Of Ind Science & Technol Terminal electrode for superconducting integrated circuit and manufacture thereof

Also Published As

Publication number Publication date
JPS62183573A (en) 1987-08-11

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