JPH0334639B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a Josefson positive latch circuit.
In particular, it is an attempt to obtain a positive logic latch circuit with high sensitivity and a wide operating margin by using a current injection Josephson gate.

<Prior art> In general, a current injection type Josephson gate is
The present applicant is JP-A-56-32830 and JP-A-57-99034.
Not only the four-junction closed leap type (generally abbreviated as "4JL") whose basic switching gate has been disclosed, but also those with other configurations are basically three-terminal circuits. One is the common terminal or ground terminal, the other is the control terminal, and the remaining one is the power input terminal or gate terminal, and the power supply current or gate current is supplied from the gate terminal to the common terminal. When an input current flows into the control terminal in a state where the input current flows into the control terminal, it changes from the zero voltage state to a voltage state or a resistance state, and operates to commutate the gate current to the load resistance side.

This operation is a so-called latching operation, which is one of the characteristics of this type of current injection Josephson gate.

In other words, once the signal current flowing into the control terminal is detected and the control terminal transitions to a voltage state, the gate current will not continue even if the signal current falls, unless the gate current is cut off and the entire gate is reset. is designed to maintain the voltage state.

Therefore, if each current flowing corresponds to logic "1", the corresponding input logic "1"
As long as the output is positive logic and the gate current is maintained, the output logic will remain latched.

However, this operation generally does not hold if the order of application of the input signal current and gate current is reversed from the above.

This is because, as is already well known, this type of current injection Josephson gate has an operation mode dependence on the current application sequence.
This is because a so-called "dead zone" occurs in the threshold characteristic under the condition that the gate current is applied after the signal current is applied.

Therefore, although it is true that this type of current injection Josephson gate has high gain and a wide operating margin, it is a desirable gate in itself, but it is difficult to use it as is as a positive latch circuit. I can't.

This is because, in general, a latch circuit must detect the logical value of the input signal current at that time and latch it when a timing current is intentionally supplied at the timing when the signal is to be latched. This is because the switching operation will not occur if the basic gate described above is used as is, the gate current is simply replaced with a timing current, and this is applied at the required timing after a signal is input.

Therefore, when constructing a positive latch circuit, a unique configuration is required, but conventionally, even if you search for such a positive latch circuit, it is possible to satisfy this requirement by using a current injection type gate configuration. There is nothing that could have been done.

However, of course, such a positive latch circuit will become one of the essential circuit elements in the future realization of Josephson computers.

However, it is not a current injection type, but a magnetic flux quantum interference type,
It is possible if it is based on the so-called skid configuration.

This is called a DC latch, and it holds a logical value of "1" or "0" depending on whether or not persistent current is stored in the superconducting closed loop. Each Josefson junction gate and an input line magnetically coupled thereto are required.

<Problems to be Solved by the Invention> A DC latch circuit using a persistent current loop requires a Josephson single-junction gate section for writing and reading, and a signal line magnetically coupled thereto, and therefore requires a large In addition to requiring inductance, the loop itself also requires a certain amount of area.

Therefore, even in the future, considering that Josephson computers of this type inherently require an extremely high level of integration, this DC latch circuit will be desirable from that point of view alone. do not have.

Additionally, circuit elements that generally adopt other current injection Josephson gate configurations, such as logic circuits, etc., as already disclosed by the present applicant,
In the future, polyphase shunt drive will be used, but a DC power system, which is a special power system for this power supply configuration, will be used.
It is also not desirable to require a separate circuit just for this DC latch circuit.

The present invention has been made in view of these circumstances, and as a basic problem, it meets the following objectives.

Power-injected Josephson, which occupies a small area and can theoretically be expected to operate at high speed.
To provide a Josefson positive latch circuit according to a gate configuration.

And it must be able to exhibit high sensitivity and wide operating margins.

<Means for Solving the Problems> In order to achieve the above object of the present invention, as a result of intensive research, the following findings were first obtained.

The present applicant has already disclosed a Josephson negation latch circuit based on the current injection principle in JP-A No. 58-162132, but by modifying or adding an additional configuration to this, it can be made into an affirmation latch circuit. There are some things that cannot be transformed into a circuit.

This is because the Josefson negation latch circuit has high sensitivity, a wide operating margin, and can occupy a very small area.

In practice, as will be explained below, it has been proven that such an idea can be realized by the present invention. For this purpose, the Josephson negation latch circuit will first be explained with reference to FIG.

In the same publication, gate terminal tg, control terminal
tc, three-terminal basic gate part Gj with common terminal te
are the four Josephson junctions proposed by the applicant.
Although the illustration is limited to a four-junction closed loop type consisting of J1, J2, J3, and J4, the terminals of the negative latch circuit 10 are signal input terminals.
Ts and a timing input terminal Tt.

A Josefson single junction Js is connected in series between the signal input terminal Ts and the control terminal tc of the basic gate section Gj.
is inserted, a resistor R3 is inserted between the ground and the timing input terminal Tt, and a resistor R2 is inserted between the timing input terminal Tt and the basic gate section.
A resistor R1 is inserted between Gj and the gate terminal tg. Load resistor RL is inserted in parallel to basic gate section Gj.

In such a configuration, when the signal input current is is supplied, when the timing current it is supplied from the timing input terminal Tt at the specified timing, the signal input current is and the timing current
The input Josephson junction Js transitions to a voltage state due to the mutual effect of the shunt ir2 through the resistor R2 of it, and from then on, both currents (is + ir2) are prevented from flowing into the basic gate section Gi. and is dropped to ground via input bypass resistor R3.

Therefore, if only the shunt ir1 (gate current) of the timing current is applied via the resistor R1, the basic gate section Gj
cannot be made to transition to a voltage state, and therefore, no output current io appears at the load resistance RL either.

Conversely, when a predetermined timing is reached in a state where the signal current is is not being supplied, and the timing current it is supplied, the shunt ir2 through the resistor R2 flows through the input Josefson junction Js to the basic gate section Gj.
flows into the gate from the control terminal tc of The output current io appears at the load resistor RL. This state is maintained as a latching state until the timing current it falls.
Follow the mode.

As can be understood from this operating mechanism, if the current flowing corresponds to a logic "1", a logic "1" input is latched as a logic "0" at a predetermined timing, and a logic "0" is latched at a predetermined timing. Since the input of `` is latched as a logic ``1'' and output, this circuit performs a negative latch function.

And again, if I had to say it, the above operation is
This is not satisfied only when the four-junction closed-loop type disclosed in the above publication is used for the basic gate part Gj, but also when using a current injection type Josefson basic gate with other configurations. To establish.

As described in the above-mentioned publication, the advantage of such a negative latch circuit is that it has high sensitivity and a wide operating margin, and that it latches only at the rising edge of the timing signal, and the subsequent signal current The reason for this change is that since it has no effect, it will not cause a runaway accident called "racing" even if it is placed in a cascade circuit.

In the present invention, as a result of reviewing the configuration and operation of previously developed negative latch circuits, a Josephson positive latch circuit having the following configuration is provided.

A Josephson positive latch circuit that has a signal input terminal, an output terminal, a first phase power supply terminal, and a second phase power supply terminal, and operates according to the current injection principle; It has three terminals: a gate terminal, a control terminal, and a common terminal. , a Josephson basic gate section that operates according to the current injection principle, a first resistor inserted between the second phase power terminal and the gate terminal of the basic gate section, and a first resistor inserted between the second phase power terminal and the reference potential plane. second and third series resistors inserted between the second and third series resistors, and a first Josephson junction inserted between the connection node of the second and third series resistors and the control terminal of the basic gate section. and a second Josephson junction inserted between the connection node of the second and third series resistors of the negation latch circuit and the signal input terminal; and the signal input terminal. a fourth resistor inserted between the input terminal and the first phase power supply terminal; and a fifth resistor connected between the signal input terminal and the reference potential plane. Josephson positive latch circuit featuring:

(Operation) The Josefson positive latch circuit having the above configuration operates as follows.

When the second phase power supply current is applied after the first phase power supply current is applied, the rising point of the second phase power supply current becomes the latch point of the signal input.

Therefore, regarding the input and output currents, if the fact that they are flowing corresponds to logic "1", after the first phase power supply current is applied and before the second phase power supply current is applied, When a logic "1" signal is applied to the signal input terminal, the sum of the signal current corresponding to the logic "1" and the first phase power supply current via the fourth resistor causes the The second Josefson junction transitions to the voltage state, and from then on, the signal current and the first phase power supply current are passed through the fifth resistor to the reference potential plane (generally ground, which is equal to the common terminal potential of the basic gate section). The signal is passed to the terminal, and cannot be input to the subsequent NOT latch circuit section.

When the second phase power supply current rises while this state is occurring, the input of the negative latch circuit section is logic "0", so its output becomes logic "1", and therefore, this affirmation is confirmed. Regarding the relationship with the signal logic input to the signal input terminal of the latch circuit as a whole, a logic "1" will be outputted by a logic "1" input, resulting in the expected result.

The operation of the negative latch circuit section itself at this time is substantially the same as the operation of the negative latch circuit described in the aforementioned Japanese Patent Laid-Open No. 162132/1983.

That is, in terms of the negative latch circuit section, only the power supply current from the second phase power supply terminal is applied, and moreover, the shunt through the second resistor is applied as a control current to the control terminal of the basic gate section. Since the shunt through the first resistor is supplied to the gate terminal as a gate current, by indicating the gain with respect to the control input current, the basic gate section changes to the electric state. This represents the output current obtained by commutating the gate current to the output terminal.

On the other hand, if no signal current is applied to the signal input terminal within the time from the rise of the first phase power supply current to the rise of the second phase power supply current, that is, if the signal logic is "0", , the first phase supply current flows through the second Josephson junction,
It reaches the connection node of the second and third resistors as inputs of the negative latch circuit section.

Therefore, this current is equivalent to receiving a logic "1" input from the negative latch circuit section, and its output becomes a logic "0".

In other words, the first phase power supply current passing through the second Josephson junction flows into the basic gate section from its control terminal via the first Josephson junction, and when the second phase power supply starts up in this state, the second phase power supply current flows into the basic gate section through the first Josephson junction. Since the shunt flow through the second resistor and the first phase power supply current that has already been input causes the first Josefson junction to transition to a voltage state, the basic gate section is subsequently Only the divided portion of the second phase power supply current flows from the gate terminal, and the basic gate section does not transition to a voltage state.

Therefore, even for a logic "0" input, a positive latch result of a logic "0" output is obtained as expected.

And, as is clear from the above mechanism,
In the case of the positive latch circuit of the present invention, the operating time is at most the sum of the operating times of one Josefson junction and the basic gate section, each of which is sufficiently short, so that
Compared to existing DC latch circuits, this circuit provides sufficient high-speed performance, and since there is no upper limit to the signal current, an extremely wide operating margin can be achieved.

Of course, the area occupied by each part can be made sufficiently smaller than that of a DC latch circuit, as no inductance is required.

Note that the reference potential plane for each of the common terminal of the basic gate part, the third resistor, and the fifth resistor is generally used as a common ground plane, but in special cases, they may be different potential planes. Naruko can also be considered. However, even in such a case, as described above, the third and fifth resistors can each function as bypass resistors, and as long as the circuit of the present invention operates normally, this is fine.

<Embodiment> FIG. 1 shows a Josephson positive latch circuit 11 as a basic embodiment constructed in accordance with the gist of the present invention described above, and FIG. 2 shows the operation of its main parts. It explains the waveform.

In FIG. 1, the negative latch circuit section 10 included in the positive latch circuit 11 may have substantially the same configuration as the known and existing negative latch circuit 10 shown in FIG. 5 for the reasons already explained. Therefore, corresponding components are given the same reference numerals as in FIG. 5, except for the following reference numerals.

Regarding the items whose signs have been changed, the timing input terminal Tt in Fig. 5 is the second phase power supply terminal P.
2, and the signal input terminal Ts is the second,
At the connection node P3 of the third resistors R2 and R3, the Josephson junction Js has become Js1, meaning the first Josephson junction, and the terminal To is newly shown as the output terminal of the positive latch circuit. There is.

And, as explained earlier, the basic gate part
Gj is not limited to the four-junction closed-loop type shown in Figure 5, but any three-terminal type that follows the current injection principle is acceptable, so it is simply shown surrounded by a large circle, and only the terminals are marked with tg, tc, and te. It is shown as follows.

The portions added according to the present invention to the mechanism of Josephson negation latch circuit section 10 are substantially as follows.

There is a first phase power supply terminal P1, and a series circuit of a fourth resistor R4 and a fifth resistor R5 is inserted between this and a reference potential plane (in the case shown, ground as a general form). The connection node between the resistors of this series circuit has a signal input terminal Ti as a positive latch circuit.
is provided.

A second Josephson junction Js2 is inserted between the signal input terminal Ti and the node P3 corresponding to the input terminal of the negative latch circuit. However, in order to satisfy the effect of the present invention described above, the critical current value of this second Josefson junction is as follows.
It must be at least smaller than that of the first Josephson junction Js1. This point is also clear from the explanation of the operation of this embodiment described below.

Referring also to FIG. 2, the operation of the positive latch circuit shown in FIG. 1 can be explained as follows.

The first phase power supply current is φ1, and the second phase power supply current is φ2.
In this circuit, the first phase power supply current φ1 is first raised in each operation cycle. For convenience, the case where the current is flowing including the signal logic is shown as "1", but as shown by the arrow I in the second row of FIG. 2, when the first phase power supply current φ1 rises, It is the fourth resistor R from terminal P1
4, the negative latch circuit section 10 is connected to the path of the second Josephson junction Js2 and the first Josephson junction Js1.
It flows into the control terminal tc of the basic gate Gj inside.

After this state, if the signal logic "1" is given to the signal input terminal Ti before the second phase power supply current φ2 rises, as shown by the arrow in FIG. Due to the power supply current φ1, the second Josephson junction Js2, which had maintained the superconducting state until then, as shown by the arrow ′
transitions to the voltage state (in the figure, this is OFF)
).

Therefore, from this point on, both the first phase power supply current φ1 and the signal current is are bypassed only through the fifth resistor R5.

Therefore, as shown by the arrow, when the second phase power supply current φ2 flows in from the terminal P2, the shunt portion φ22 passing through the second resistor R2 becomes a critical current that cannot be brought into a voltage state by itself. value
The gate current φ2 flows from the control terminal tc of the basic gate section 10 into the gate section through the Josefson junction Js1 of Ios1, and on the other hand flows through the first resistor R1.
1 flows into the gate from the gate terminal tg, the elementary gate section Gj switches to a voltage state.

As a result, the gate current φ21 is changed to the output terminal To
The current is commutated to the load resistor RL side through the output current io, and the output logic "1" is expressed as the output current io, as shown by the arrow in FIG.

This series of operations is defined in the latch mode, and in other words, the reset of this circuit is accomplished under the following conditions.

First, regarding the second Josefson junction js2, as shown by the arrow in Fig. 2, the signal current
This is performed when both is and the first phase power supply current φ1 fall.

As for the basic gate portion Gj, as shown by the arrow, the operation is performed at the time when the second phase power supply current φ2 falls.

As described above, it has been proven that according to this circuit 11, a logic "1" input can be positively latched as a logic "1" output, but similarly, a logic "0" input can be latched as a logic "0" output. What can be latched will be explained below.

After the first phase power supply current φ1 is again applied to the terminal P1, as shown by the arrow ′ to the right of the part previously mentioned regarding the input of logic “1” in FIG. If logic “0” is applied to the signal input terminal Ti of this circuit 11 before the second phase power supply current φ2 rises as shown by arrow ′,
That is, when no significant signal current is is applied, the first phase power supply current φ1 is transferred from the second Josephson junction Js2, which does not transition to a voltage state, to the first Josephson junction Js1, and then flows through the control terminal tc.
It is in a state that it has already flowed into the basic gate section Gj.

Therefore, when the second phase power supply current φ2 is applied here and its shunt φ22 is added, the first Josephson junction Js1 transitions to the voltage state at this point, and therefore the remainder of the second phase power supply current φ2 Diversion of φ
21 simply flows into the basic gate section Gj from the gate terminal, this gate Gj cannot transition to the voltage state, and therefore, as shown by the arrow, the logic of the output terminal To becomes "0". keep.

In this circuit 11, if the symbols indicating each current are used to directly represent the magnitude of the current, various design conditions can be derived as is apparent from the above operation.

Among them, the main ones are the critical current value Ios1 of the first Josephson junction, the critical current value Ios2 of the second Josephson junction, the first phase power supply current φ1,
The relationship between the second phase power supply current shunt φ22 and the input signal current is may be designed so that the following group of equations holds true.

φ1＜Ios2＜φ1＋is; ∴is＞Ios2−φ1 ……(1) Ios2＜Ios1＜φ1＋φ22 ……(2) Therefore, as can be seen from equation (1) above, there is no upper limit to the input signal current is. .

On the other hand, since it is sufficient to transition the second Josefson junction Js2 to the voltage state with the surplus of the first phase power supply current φ1, it is sufficient to transition the second Josephson junction Js2 to the voltage state, so as in the conventional negative circuit shown in FIG. Compared to the case where the Josefson junction Js interposed in is caused to transition to a voltage state, the lower limit can also be set to a lower value.

This, of course, means that a wide operating margin is ensured regarding the input signal current.

Considering other important matters from a different point of view in terms of design, there is a phase relationship between the first phase power supply current φ1 and the second phase power supply current φ2.

However, as already explained and as shown in FIG. 2, after the rise of the first phase power supply current φ1, the second phase power supply current φ2
It is sufficient if there is a time difference Δt1 such that the second phase power supply current φ2 rises, and the first phase power supply current φ1 falls after a time Δt2 after the rise of the second phase power supply current φ2, and the signal current is is equal to the first phase power supply current φ1. It suffices if it can be applied after the rise of the second phase power supply current φ2 and before the rise of the second phase power supply current φ2.

This also means that there is a time when both phase currents φ1 and φ2 rise together, but as mentioned above, only the rise is significant for the second phase power supply current φ2. , similar to the known negative latch circuit 10 shown in FIG.
No runaway accidents such as this will occur.

The Josefson positive latch circuit 12 shown in FIG. 3 is an embodiment of the present invention in which a buffer section 13 having a current amplification function is added to the input stage.

The circuit components other than the buffer section 13 may be substantially the same as or the same as those in the basic embodiment shown in FIG. Some of them are appropriate.
Some explanations may be omitted.

Due to the addition of the buffer section 13, the signal input terminal of the circuit 12 shown in the third diagram has essentially shifted to the input terminal Ti' of the buffer section 13, but regarding the positive latch function, The connection node between the fourth and fifth resistors R4 and R5 can be considered to be the same as the signal input terminal Ti in the first illustrated circuit.

For the same reason, by considering the input signal current is' to the buffer section 13 as the current before amplification, the input current related to the positive latch function can be thought of as the input current is to the terminal Ti, in other words. Ba,
The output current of the buffer section 13 corresponds to the signal current is in FIG.

The buffer section 13 itself may have exactly the same structure as a known current injection Josephson switching gate.

That is, a part of the first phase power supply current φ1 is transferred to the resistor R.
It is only necessary that the gate current ig is supplied to the buffer gate section Gb as the gate current ig through the gate current ig through the gate current ig, and that the three-terminal basic gate section Gb changes to a voltage state upon input of the signal current is'.

As is well known, the resistor R7 controls the input current after the basic gate section Gb transitions to the voltage state.
This is to bypass is' and separate input and output.

In addition, the output current when the basic gate part Gb transitions to the voltage state is the load resistance RL2 in this circuit.
The connection node of the fourth and fifth resistors R4 and R5 through
This becomes the amplified signal current is given to Ti.

Therefore, the operation of the circuit shown in FIG. 3 is basically the same as that of the circuit shown in FIG.

To explain briefly, under the condition that the first phase power supply current φ1 is given, the signal current representing logic “1”
When is' is applied to terminal Ti', the basic gate section Gb of the buffer section 13 transitions to a voltage state, and a logic "1" signal current is amplified in analog current level appears at the load resistor RL2. .

Therefore, together with the first phase power supply current flowing through the fourth resistor R4, the second Josefson junction Js2 is brought into a voltage state. Therefore, when the second phase power supply current φ2 is applied thereafter, the negative latch circuit section 10
transitions to the voltage state, and a logic “1” appears at the output terminal To.
An output current io appears that represents .

On the other hand, when the signal logic "0" is applied, the buffer section 13 does not change to the voltage state, so that the shunt portion of the first phase power supply current via the fourth resistor R4 is the basic of the negative latch circuit section 10. When the second phase power supply current φ2, which is applied to the gate part Gj in advance and is subsequently applied, the first Josephson junction Js1 changes to the voltage state, so that the basic gate part Gj maintains the zero voltage state. ,
The output logic also becomes logic "0", which is represented by the fact that the output current io does not flow.

Thus, regarding the positive latch function,
The circuit system shown in the third diagram is also the same as that shown in the first diagram.

On the other hand, however, when considering a practical Josefson integrated circuit, it is extremely desirable to have a buffer function on the input side and, moreover, to have a current amplification function. In this sense, the circuit configuration shown in FIG. 3 will teach more practical circuit configurations in the future.

Furthermore, now that Josephson logic circuits are expected to generally adopt a dual-rail system, the present invention can be applied to A latch circuit, especially a circuit such as that shown in FIG. 3, appears to produce very practical and reasonable results. As is well known, the dual rail method means that when there is a logic signal a, when it is input to the logic circuit, a complementary signal is created and this signal is also input to the logic circuit simultaneously and in parallel. Tell me how to do it.

For example, suppose that two sets of almost the same circuits as shown in FIG. 3 are prepared and formed in parallel on an integrated circuit board as shown in FIG. 4.

However, what is different from the case shown in Fig. 3 is the second Josephson junction Js2, and in the circuit system shown at the bottom, the jumper wire portion JP that selectively shorts it.
JP is formed as it is, whereas in the upper circuit system constituting the buffered positive latch circuit 12 shown in FIG. Either by patterning processing up to this stage or by selective overlapping mask processing only for this part,
As shown by the space JC between the facing arrows,
In the lower circuit system, as shown by the space JC between the opposite arrows, the fourth and fifth resistors R4 and R5 are cut at the jumper wire JP. Two points are that it is physically separated from the circuit.

Therefore, the upper circuit system is no different from the circuit shown in FIG. The applied signal logic a is latched in the affirmative and the logic a is output to the output terminal To.

However, in the lower circuit system, the second Josefson junction Js2 is shorted, and the fourth and fifth resistors R4 and R5
By disabling it, it has been changed to a buffered NOT latch circuit 14, and a NOT logic latch result is obtained at the output terminal To.

That is, by applying the first phase power supply current φ1,
The signal logic a amplified by the buffer section 13 is
In the lower circuit system, the second phase power supply current φ2 is directly applied to the node P3 corresponding to the signal input terminal Ts of the negative latch circuit already explained with reference to FIG. It functions in the same way as the timing current described above, and as a result, a negative logic is output to the output terminal To.

Therefore, a dual rail signal consisting of the complementary pair a of the input change a can be extracted from the output terminal To of the upper circuit system and from the output terminal To of the lower circuit system.

Such a relationship can also be satisfied by the relationships shown in FIG. 5 and FIG. 1, and in that case, almost the same patterning can be achieved on the positive side and the negative side.

This kind of pattern configuration is especially convenient because if you prepare a separate pattern mask for cutting the jumper wire JP or forming a predetermined space JC, you can easily change the upper part by simply replacing it. By changing the circuit system to a negative latch circuit and the lower circuit system to a positive latch circuit, or by making both positive latch circuits according to the present invention, the number of parallel outputs for one input (so-called fan-out) can be effectively reduced. Processing such as increase can be easily performed without major changes to the mask pattern.

In addition, even in the case shown in FIG. 4, the buffer section 13 at the previous stage may be common to the upper and lower circuits.

<Effects of the Invention> According to the present invention, the Josephson positive latch circuit, which is one of the important circuit elements that will be needed in the future to realize the Josephson computer, can be
It can be provided by a configuration that follows current injection management.

Therefore, it inherently provides high-speed operation, wide operating margin, and occupies a small area, making it ideal for high-density integration, as well as simple circuit configuration and high operational reliability. .

Furthermore, it is possible to rationally and without contradiction support the multiphase pulsating current power supply type, which is expected to become the most common power supply type in the future.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a basic embodiment of a Josefson positive latch circuit according to the present invention, and FIG.
3 is a schematic diagram of a positive latch circuit with a buffer as a second embodiment of the present invention, and FIG. 4 is a diagram of a negative latch circuit as a more practical embodiment of the present invention. FIG. 5 is a schematic diagram of a conventional current injection type Josefson negation latch circuit when combined with a circuit. In the figure, 10 is a current injection Josephson negation latch circuit or a negation latch circuit used in the present invention;
11 is the current injection type Josephson positive latch circuit as a whole, 12 is the buffered Josephson positive latch circuit, 13 is the buffer section, Gj is the basic gate of the current injection type Josephson switching gate, Js1 and Js2 are Josephson junctions, P1
is the first phase power terminal, P2 is the second phase power terminal, Ti
is the signal input terminal, and Yo is the output terminal.

Claims (1)

[Claims] 1. Signal input terminal, output terminal, first phase power supply terminal,
A Josephson positive latch circuit having a second phase power supply terminal and operating according to the current injection principle; A first resistor inserted between the second phase power terminal and the gate terminal of the basic gate section, and second and third resistors inserted between the second phase power terminal and the reference potential surface. a series resistor, and a first Josephson junction inserted between the connection node of the second and third series resistors and the control terminal of the basic gate section; a second Josefson junction inserted between the connection node of the second and third series resistors of the latch circuit section and the signal input terminal; and between the signal input terminal and the first phase power supply terminal. A Josephson positive latch circuit comprising: a fourth resistor inserted; and a fifth resistor connected between the signal input terminal and the reference potential plane.