JPH0334651B2 - - Google Patents
Info
- Publication number
- JPH0334651B2 JPH0334651B2 JP58224746A JP22474683A JPH0334651B2 JP H0334651 B2 JPH0334651 B2 JP H0334651B2 JP 58224746 A JP58224746 A JP 58224746A JP 22474683 A JP22474683 A JP 22474683A JP H0334651 B2 JPH0334651 B2 JP H0334651B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- chip
- circuit board
- conductive
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
Landscapes
- Wire Bonding (AREA)
- Liquid Crystal (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は各種電子機器に使用される半導体装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device used in various electronic devices.
従来例の構成とその問題点
従来、半導体装置を最も小さく回路基板に実装
する手段として半導体素子をチツプで取扱う方法
が各種考案されている。その一つとしてフリツプ
チツプがあり、これは半導体素子チツプの電極
部、すなわちアルミパツド上に金属薄膜とハンダ
メツキにより突起電極(バンプ)を設け、この半
導体素子チツプを回路基板上へフエイスダウンで
実装するものである。このフリツプチツプの製造
はまずアルミパツドを含む素子全面にチタンまた
はクロムなどアルミと密着性の良好な金属を蒸着
によつて形成する。次に銅などの良導体を同一面
に蒸着した後、フオトレジストを全面にかけ先の
アルミパツド部のみを除去し下の金属を電極とし
てスズと鉛の電気メツキを適当の厚みにメツキす
る。メツキ後レジストを剥離して次にスズと鉛の
部分にフオトレジストをかけ下地の金属膜をエツ
チングで除去する。このフオトレジストを剥離
後、スズと鉛のメツキ層を溶融させハンダとす
る。このようにして作られた半導体素子チツプは
回路基板に載置、加熱することによつて回路基板
上の電極へハンダ付けされ、電気的結合が成され
る。この方法によれば蒸着法による薄膜形成、電
気メツキによるハンダ形成、フオトリソによるレ
ジスト膜形成とエツチング等、複雑な工程を必要
とすることと回路基板上の電極と十分なハンダ付
け強度を得るためハンダ量を多く必要とし、アル
ミパツド間隔も200〜300ミクロンが必要となる。
以上のようにフリツチツプはチツプそのままの実
装面積となり高密度実装には有効な手段である反
面、先ほどのように製造プロセスが非常に複雑で
あるため製品歩どまりの低下やチツプコストのア
ツプをまねく。一方、このフリツプチツプは半導
体メーカー側での処理が必要であり、ユーザー側
では不可能である。また、フリツプチツプは回路
基板上へハンダ付けによつて実装するもので回路
基板、例えば液晶パネルの如きITO上へ直接実装
する場合などは先にITOをハンダ付けできるよう
にメタライズしておかなければならず液晶パネル
製造においてもパネルコストのアツプとなる。Conventional Structures and Their Problems Conventionally, various methods have been devised for handling semiconductor elements in chips as a means of packaging semiconductor devices on circuit boards in the smallest size possible. One of these is the flip chip, in which protruding electrodes (bumps) are provided on the electrode portion of a semiconductor chip, that is, an aluminum pad, using a metal thin film and solder plating, and the semiconductor chip is mounted face-down onto a circuit board. be. To manufacture this flip chip, first, a metal that has good adhesion to aluminum, such as titanium or chromium, is formed on the entire surface of the device including the aluminum pad by vapor deposition. Next, after depositing a good conductor such as copper on the same surface, photoresist is applied to the entire surface, only the aluminum pad is removed, and tin and lead are electroplated to an appropriate thickness using the underlying metal as an electrode. After plating, the resist is peeled off, and then a photoresist is applied to the tin and lead parts and the underlying metal film is removed by etching. After peeling off this photoresist, the tin and lead plating layer is melted to form solder. The semiconductor element chip produced in this manner is placed on a circuit board and heated to be soldered to the electrodes on the circuit board to establish an electrical connection. This method requires complicated processes such as thin film formation by vapor deposition, solder formation by electroplating, and resist film formation and etching by photolithography. A large amount is required, and the spacing between aluminum pads must be 200 to 300 microns.
As mentioned above, flip chips have the same mounting area as the chip, making them an effective means for high-density packaging. However, as mentioned earlier, the manufacturing process is extremely complex, leading to lower product yields and higher chip costs. On the other hand, flip-chip processing requires processing by the semiconductor manufacturer and is not possible by the user. In addition, flip chips are mounted on a circuit board by soldering, and when mounting directly on a circuit board, such as an ITO such as a liquid crystal panel, the ITO must first be metalized so that it can be soldered. First, panel costs will also increase in LCD panel manufacturing.
発明の目的
本発明は半導体素子チツプのコスト低減と回路
基板、特に液晶パネルに使用される透明導電膜上
へメタライズすることなく直接実装できる半導体
装置を提供することを目的とする。OBJECTS OF THE INVENTION An object of the present invention is to reduce the cost of semiconductor element chips and to provide a semiconductor device that can be directly mounted on a transparent conductive film used in a circuit board, particularly a liquid crystal panel, without metallization.
発明の構成
本発明は半導体素子チツプのアルミ電極パツド
部上に感光性ポリイミド樹脂と導電性金属酸化物
粉からなる導電性塗料をパツシベーシヨン膜より
も高く形成したことを特徴とするものである。Structure of the Invention The present invention is characterized in that a conductive paint made of a photosensitive polyimide resin and a conductive metal oxide powder is formed on the aluminum electrode pad portion of a semiconductor element chip to be higher than the passivation film.
実施例の説明
以下、本発明の実施例について説明する。ま
ず、本発明の特徴とする点について述べると、最
も大きな特徴は導電性樹脂によつてバンプを形成
し、樹脂の接着効果を利用して回路基板の回路導
体をメタライズすることなく電気的、機械的に結
合することである。感光性樹脂はアクリレート化
したポリイミド樹脂が良く、導体粉は酸化スズ、
酸化インジユウムの微粉末で粒子径が0.1ミクロ
ン以下のものが本発明で特に有効である。これは
酸化スズ、酸化インジユウムの微粉末は粒径が小
さく光の波長よりも小さいことから透光性を有
し、感光性樹脂の光硬化の障害とならなく、高精
度にバンプを形成することが可能となるためであ
る。一般に良く用いられる金属粉は0.1ミクロン
以下の微粒子にすることは困難であるため本発明
には使用できない。Description of Examples Examples of the present invention will be described below. First, to describe the features of the present invention, the most significant feature is that bumps are formed using conductive resin, and by utilizing the adhesive effect of the resin, electrical and mechanical connections can be made without metalizing the circuit conductors of the circuit board. It is to combine in a specific manner. The photosensitive resin is preferably acrylated polyimide resin, and the conductive powder is tin oxide,
Fine powder of indium oxide with a particle size of 0.1 micron or less is particularly effective in the present invention. This is because the fine powder of tin oxide and indium oxide has a small particle size and is smaller than the wavelength of light, so it has translucency and does not interfere with the photocuring of photosensitive resin, making it possible to form bumps with high precision. This is because it becomes possible. Generally used metal powders cannot be used in the present invention because it is difficult to make them into fine particles of 0.1 micron or less.
次に本発明の一実施例について図面を用いて説
明する。 Next, one embodiment of the present invention will be described using the drawings.
図において、1はシリコン基板であり、このシ
リコン基板1上には蒸着などの方法によりアルミ
パツド部2が形成され、さらにプラズマナイトラ
イドなどのパツシベーシヨン膜3が形成されて半
導体素子チツプが構成されている。また、上記ア
ルミパツド部2上には感光性ポリイミド樹脂と導
電性金属酸化物粉からなる導電性塗料を塗布して
形成されるバンプ4が上記パツシベーシヨン膜3
よく高く形成されている。 In the figure, 1 is a silicon substrate, and on this silicon substrate 1, an aluminum pad portion 2 is formed by a method such as vapor deposition, and a passivation film 3 such as plasma nitride is further formed to constitute a semiconductor element chip. . Further, bumps 4 are formed on the aluminum pad portion 2 by applying a conductive paint made of photosensitive polyimide resin and conductive metal oxide powder, and the bumps 4 are formed on the aluminum pad portion 2.
Well formed and high.
このような構成の半導体装置についての製造方
法を以下に述べる。まず、ポリイミド樹脂と溶剤
からなるワニスの樹脂分100重量部にアンチモン
ドープの酸化スズ粉を40重量部加えボールミルで
分散させ塗料化する。これを半導体素子チツプ上
に厚みを5〜50ミクロンになるよう塗布し、フオ
トマスクでアルミパツド部2を露光し、未露光部
を現像除去して半導体装置を得る。この半導体装
置を回路基板として液晶パネルのガラス上に形成
された透明電極上にアライメントした後、半導体
装置の裏面から350℃30sec35Kg/cm2の条件にて
接着させる。このとき透明電極のITOは何らメタ
ライズする必要もなく、加熱することによつて樹
脂の硬化が完全となり、強固な接着と電気的結合
が得られる。バンプ4の高さは上記圧着時にこの
バンプ4に圧力が十分加わる高さがあれば良く、
通常半導体素子チツプはプラズマナイトライドな
どのパツシベーシヨン膜3で保護されているのが
普通である。その厚みは0.8〜1.0ミクロンであ
り、本発明によるバンプ4はこれ以上の厚み、理
想的には回路基板の凹凸を吸収できる厚みが必要
である。具体的には各種基板について実験の結
果、バンプ4の厚みは5ミクロン以上あれば良好
な接続が得られることが明らかとなつた。また、
5ミクロン以上で50ミクロンの範囲が良くこれ以
上厚くなると、パツド間隔が例えば100ミクロン
程度になつたときシヨートする危険性もある。こ
れは露光時のかぶり現象によりパターン精度が悪
くなるためである。 A method of manufacturing a semiconductor device having such a configuration will be described below. First, 40 parts by weight of antimony-doped tin oxide powder is added to 100 parts by weight of the resin of a varnish made of polyimide resin and a solvent, and dispersed in a ball mill to form a paint. This is applied onto a semiconductor chip to a thickness of 5 to 50 microns, the aluminum pad portion 2 is exposed using a photomask, and the unexposed portion is removed by development to obtain a semiconductor device. This semiconductor device is used as a circuit board and aligned on a transparent electrode formed on the glass of a liquid crystal panel, and then bonded from the back side of the semiconductor device at 350° C. for 30 seconds and 35 kg/cm 2 . At this time, there is no need to metalize the ITO of the transparent electrode, and the resin is completely cured by heating, resulting in strong adhesion and electrical connection. The height of the bump 4 should be such that sufficient pressure is applied to the bump 4 during the above-mentioned crimping.
Normally, a semiconductor chip is protected with a passivation film 3 made of plasma nitride or the like. The thickness is 0.8 to 1.0 microns, and the bump 4 according to the present invention needs to have a thickness greater than this, ideally a thickness that can absorb the unevenness of the circuit board. Specifically, as a result of experiments on various substrates, it has become clear that a good connection can be obtained if the thickness of the bump 4 is 5 microns or more. Also,
If the pad is thicker than 5 microns, the range of 50 microns is good, and if the pad spacing becomes, for example, about 100 microns, there is a risk of it being shot. This is because pattern accuracy deteriorates due to a fogging phenomenon during exposure.
実施例
導電塗料の材料と配合を以下の通りとしボール
ミルで混合、分散させ塗料化した。Example The materials and formulations of the conductive paint were as follows, and they were mixed and dispersed in a ball mill to form a paint.
ポリイミド樹脂(東レ(株)フオトニース)
……100重量部
酸化スズ粉(三菱金属(株)T−1)……35重量部
この塗料をスピンナーでCMOSが形成された
4インチウエハー上に厚み10ミクロンになるよう
にコーテイングし85℃60分の予備乾燥した。この
ウエハーにフオトマスクを密着露光(120W/cm
2UVランプで20秒)し、未露光部を現象除去し
た。さらにウエハーを100℃60分の乾燥した後、
ダイシングソーでで所定のチツプ寸法に切断し完
成半導体装置とした。この半導体装置を回路基板
としてガラス上の透明電極で形成した回路パター
ンにアライメントした後、半導体装置の裏面から
400℃、30Kg/cm2、30秒の条件でガラス板に圧着
すると同時に電気的接続を行つた。この時のチツ
プサイズは5mm角でパツド数64で横方向の押し強
度は3.9Kg、垂直方向の引張り強度は、2.1Kgであ
つた。回路を電気的動作させたところ所定の動作
であることを確認した。Polyimide resin (Toray Industries, Inc. Photonice)
...100 parts by weight tin oxide powder (Mitsubishi Metals Co., Ltd. T-1) ...35 parts by weight This paint was coated on a 4-inch wafer on which CMOS was formed using a spinner to a thickness of 10 microns at 85℃60 Pre-dried for a minute. Close exposure of photomask to this wafer (120W/cm
2) using a UV lamp for 20 seconds) to remove the unexposed areas. After further drying the wafer at 100°C for 60 minutes,
The chips were cut into predetermined chip dimensions using a dicing saw to produce completed semiconductor devices. After aligning this semiconductor device with a circuit pattern formed with transparent electrodes on glass as a circuit board,
Electrical connection was made at the same time as pressure bonding to the glass plate under the conditions of 400° C., 30 Kg/cm 2 , and 30 seconds. At this time, the chip size was 5 mm square, the number of pads was 64, the pushing strength in the lateral direction was 3.9 kg, and the tensile strength in the vertical direction was 2.1 kg. When the circuit was operated electrically, it was confirmed that it operated as expected.
発明の効果
本発明は導電性でしかも感光性を有する塗料を
ウエハー上に一定厚み塗布しアルミパツド部にバ
ンプを形成した構成であり、この半導体装置を回
路基板に熱圧着することによつて良好な接着と接
続が得られる。この方法によれば液晶パネルのよ
うなガラス上に透明導電薄へメタライズすること
なく直接実装することが可能となる。さらに簡単
なプロセスによつてバンプが形成できコストの大
巾な低減が可能となることと、特殊な技術を必要
としないため今まで半導体メーカー側で処理しな
ければならなかつたバンプ技術がユーザー側で処
形成できるようになつたことは今後の半導体産業
に貢献するものである。特に、本発明は、感光性
ポリイミド樹脂と、粒子径が0.1ミクロン以下の
酸化スズまたは酸化インジユウムの微粉末とから
なる導電性塗料を用いており、酸化スズまたは酸
化インジユウムは粒径が小さく光の波長よりも小
さいことから透光性を有し、感光性樹脂の光硬化
の障害とならないため、高精度にバンプを形成す
ることができる。Effects of the Invention The present invention has a structure in which a conductive and photosensitive paint is applied to a certain thickness on a wafer and bumps are formed on the aluminum pad, and this semiconductor device is thermocompression bonded to a circuit board to achieve a good quality. Adhesion and connection are obtained. According to this method, it is possible to directly mount the device on glass such as a liquid crystal panel without metalizing it into a transparent conductive thin film. In addition, bumps can be formed using a simple process, making it possible to significantly reduce costs, and because no special technology is required, bump technology that previously had to be processed by semiconductor manufacturers can now be handled by users. The fact that it is now possible to process semiconductors will contribute to the future semiconductor industry. In particular, the present invention uses a conductive paint consisting of a photosensitive polyimide resin and fine powder of tin oxide or indium oxide with a particle size of 0.1 micron or less. Since it is smaller than the wavelength, it has translucency and does not interfere with photocuring of the photosensitive resin, so bumps can be formed with high precision.
図面は本発明の半導体装置の一実施例を示す断
面図である。
1……シリコン基板、2……アルミパツ部、3
……パツシベーシヨン膜、4……バンプ。
The drawing is a sectional view showing an embodiment of the semiconductor device of the present invention. 1...Silicon substrate, 2...Aluminum parts, 3
... Passivation film, 4... Bump.
Claims (1)
ポリイミド樹脂と0.1ミクロン以下の酸化スズま
たは酸化インジユウムの導電性金属酸化物粉とか
らなる導電性塗料によるバンプをパツシベーシヨ
ン膜よりも高く形成したことを特徴とする半導体
装置。1. A bump made of a conductive paint made of a photosensitive polyimide resin and a conductive metal oxide powder of tin oxide or indium oxide of 0.1 micron or less is formed on the electrode pad portion of a semiconductor chip at a height higher than the passivation film. semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58224746A JPS60116150A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58224746A JPS60116150A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60116150A JPS60116150A (en) | 1985-06-22 |
| JPH0334651B2 true JPH0334651B2 (en) | 1991-05-23 |
Family
ID=16818584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58224746A Granted JPS60116150A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60116150A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61287625A (en) * | 1985-05-29 | 1986-12-18 | Kaneko Agricult Mach Co Ltd | Grain filling device in grain drying machine |
| JPS63181450A (en) * | 1987-01-23 | 1988-07-26 | Matsushita Electric Ind Co Ltd | Bump for semiconductor device and its manufacture |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5826121B2 (en) * | 1974-04-24 | 1983-06-01 | セイコーエプソン株式会社 | Transparent conductive film precision pattern formation method |
| JPS5650539A (en) * | 1979-09-29 | 1981-05-07 | Sharp Corp | Semiconductor device |
-
1983
- 1983-11-29 JP JP58224746A patent/JPS60116150A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60116150A (en) | 1985-06-22 |
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