JPH0335686B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an optical coordinate input device including a light emitting element array and a light receiving element array.

(Technical background of the invention) Optical coordinate input devices are
It is attached to the front of the display surface of an LCD (liquid crystal display), etc., and uses a scanning method in which the light signals output from each light emitting element of a light emitting element array are received by each light receiving element of a light receiving element array. Furthermore, when the optical signal is interrupted by a finger or the like, the position is outputted to a personal computer or the like as indicated coordinates.

FIG. 5 shows a circuit configuration for processing optical signals of a conventional optical coordinate input device. That is, in the figure, 10 indicates a light receiving element array, and this light receiving element array is formed from a plurality of phototransistors _PT1 to PTn. Each phototransistor PT ₁ ~
The emitters of PTn are commonly grounded, and the collectors are connected to the switches SW ₁ to SWn of the switching circuit 12. Each switch _SW1 to SWn is connected to an NPN transistor 14 via a coupling capacitor _C1 .
connected to the base of. This transistor 1
The collector of 4 is connected to the power supply Vcc via resistors R ₁ and R ₂ .
is also connected to the output terminal 16 via a coupling capacitor _C3 . The base of transistor 14 is connected to the power supply via base resistor _R3 .
Vcc is connected. Phototransistors PT _{1 to} PT are connected between resistors R ₁ and R ₂ via a switching circuit 12.
A resistor _R4 is connected to apply voltage to PTn. In addition, the power supply Vcc is connected between resistors _R1 and _R2 .
A capacitor _C2 is connected to bypass the fluctuations in .

Next, the light reception processing operation of the optical coordinate input device will be explained.

When the synchronizing pulse shown in FIG. 6a is input to the switching circuit 12, the switch _SW1 is closed and a voltage is applied to the collector of the phototransistor _PT1 via the resistors _R1 and _R4 . On the other hand, the light emitting element array (not shown) is scanned in response to the input of the synchronization pulse, and the LED corresponding to the phototransistor _PT1 emits light.
Therefore, since the optical signal Sp from the LED is received by the phototransistor _PT1 , the phototransistor _PT1 becomes conductive.

When the phototransistor PT ₁ becomes conductive, a negative pulse voltage is applied to the base of the transistor _{14 via the coupling capacitor C 1} and the transistor 14 is switched to the OFF state.
Since base current Ib stops flowing, its collector voltage rises. Therefore, the collector voltage is converted to the coordinate signal { _6th
It can be taken out from the output terminal 16 as shown in Figure e}. Note that since the LED corresponding to the phototransistor PT ₁ outputs at least two or more optical signals Sp during one scan, the coordinate signal is composed of two or more pulse signals.

Similarly, each time a synchronization pulse is input, the switches SW ₂ to SWn of the switching circuit 12 are closed, and the phototransistors PT ₂ to PTn receive the optical signal Sp from the corresponding LED, indicating each coordinate position. Coordinate signals can be obtained continuously. Therefore,
If the optical signal is blocked by a finger or the like and, for example, the optical signal Sp is not received by the phototransistor PT ₃ , the coordinate signal will not be output from the output terminal 16, so the scanning (phototransistor PT ₃ )
The indicated coordinates can be known from the relationship with the position.

(Problems with the Background Art) Now, light emitting and light receiving elements such as phototransistors PT ₁ to PTn and LEDs that output optical signals Sp have variations in characteristics with respect to optical signals. Furthermore, the phototransistors PT ₁ to PTn are affected by changes in light intensity from a CRT display, etc., and by ambient light. Therefore, the collector voltage Vp of each phototransistor varies greatly. Therefore, as shown in FIG. 6b, if the collector voltage Vp of the phototransistor PT ₂ is significantly reduced due to disturbance light or the like at the time when the phototransistor PT ₂ receives the optical signal Sp, the base of the transistor 14 is Since the voltage Vb also decreases as shown in FIG. 6c, the transistor 14 may be kept in the OFF state during the scanning period of the phototransistor _PT2 . Therefore, as shown in FIG. 6e, the coordinate signal remains rising, so even though the phototransistor PT ₂ is receiving the optical signal Sp, the personal computer etc. does not receive the coordinate input. I mistakenly think it's something. Also, since a voltage is applied to the base of the transistor 14 via the resistor _R3 , the coupling capacitor
As shown in FIG. 5, charging current Ic flows into _C1 . Therefore, when the collector voltage Vp of the phototransistor decreases, PT ₂ and
As shown by PT _(o-1) , the falling level of the base voltage Vb of the transistor 14 is increased. However, since the base voltage Vb only increases gradually based on the time constant of the resistor _R3 and the coupling capacitor _C1 , if the collector voltage Vp of the phototransistor decreases significantly, the coordinate signal will change as described above. Stay on your feet. For example, as shown in FIG. 6b, if the optical signal Sp is received at the time when the collector voltage Vp of the phototransistor PT ₃ has slightly increased, a low-level base current Ib flows through the transistor 14. Since distortion may occur in the rise of the current Ib {see waveform in FIG. 6d}, it becomes difficult to determine whether or not the coordinate signal is output as a pulse waveform. Therefore, in this case as well, there is a risk that the personal computer or the like may make an erroneous judgment.

Moreover, when the switches SW ₁ to SWn of the switching circuit 12 are switched by the synchronization pulse, each phototransistor PT ₁ to
The collector voltage Vp of PTn falls momentarily,
The base voltage Vb of the transistor 14 also drops instantaneously. For this reason, switch SW ₁ ~
When SWn is switched, the base current Ib of the transistor 14 instantly falls or is cut off, and the noise signal N is added to the coordinate signal. Therefore, there is a risk that a personal computer or the like will determine this noise signal N as a coordinate signal, which may also cause erroneous determination.

As explained above, the region between the base and emitter of the transistor 14 acts as a diode and forms a clamp circuit together with the coupling capacitor _C1 and the resistor _R3 , so that when the base voltage Vb decreases, the voltage Vb is adjusted to a specified level. Correct by clamping to match the level. However, as mentioned above, if the base voltage Vb fluctuates significantly due to variations in the optical characteristics of the light-emitting and light-receiving elements, disturbance light, and switching noise, the base voltage Vb cannot be maintained at a predetermined level even by clamping.
It is not possible to correct up to Vbl.

If the resistance value of resistor R ₃ is set to a small value, a large correction can be made by the clamp operation, but if the resistance value of resistor R ₃ is small, transistor 1
The excess accumulated carriers accumulated in the base of transistor 14 will increase and the impedance on the base side of transistor 14 will decrease. Therefore, with respect to the fall and rise of the collector voltage Vp of the phototransistor, the base voltage of the transistor 14
The fall and rise of Vb are delayed, and the waveform of base voltage Vb is distorted. Therefore,
In the case where the light emitting and light receiving elements are scanned at high speed, this may similarly cause erroneous judgments.

(Object of the Invention) An object of the present invention is to provide an optical coordinate input device that is not affected by ambient light or switching noise, and that accurately sends out coordinate signals even when operated at high speed.

(Summary of the Invention) The present invention applies a predetermined voltage by a switching means to the base of a bipolar transistor for amplifying and outputting a coordinate signal when switching a switching circuit, and also adjusts the level of the coordinate signal applied to the bipolar transistor. is fixed at a predetermined level by a clamping means, and excess accumulated carriers at the base of the bipolar transistor are discharged to the collector side by a diode.

(Embodiments of the Invention) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows the overall configuration of an optical coordinate input device according to the present invention. That is, this coordinate input device includes a light emitting element array 20 and a light receiving element array 30. The light emitting element array 20 includes a plurality of LEDs ₁ to
It consists of LEDn and is arranged in an L-shape in front of the display surface of a CRT display (not shown). Further, the light receiving element array 30 includes a plurality of phototransistors.
These phototransistors consist of PT ₁ to PTn.
PT ₁ to PTn are arranged in an L-shape at opposite positions on the front surface of the display surface, facing LED ₁ to LEDn, respectively. The anode sides of LED ₁ to LEDn are connected to each switch of the switching circuit 22.
2 is connected to a drive circuit 24. A drive signal Sd from the CPU 40 is supplied to the drive circuit 24.

Phototransistors PT ₁ to PTn are switching circuits 12
It is connected to the amplifying section 50 via. That is, the emitters of the phototransistors PT ₁ to PTn are connected to the first
As shown in the figure, each collector is connected to a respective switch SW ₁ to SWn of the switching circuit 12, which is commonly grounded.
It is connected to the. Each switch SW ₁ -SWn is connected to the base of the NPN transistor 14 via a coupling capacitor C ₁ . A power supply is connected to the collector of the transistor 14 via resistors R ₁ and R ₂ .
Vcc is connected. In addition, the transistor 14
An output terminal 16 is connected to the collector of the output terminal ₁₆ via a coupling capacitor C3. Output terminal 1
The coordinate signal Sxy from 6, which will be described later, is input to the CPU 40 as shown in FIG. The base of the transistor 14 is connected to the power supply Vcc via the base resistor _R3 .
is connected. Phototransistors PT ₁ to PTn are connected between resistors R ₁ and R ₂ via a switching circuit 12.
A resistor R4 is connected to apply a voltage to the resistor _R4 , and a capacitor _C2 is connected between them to bypass fluctuations in the power supply Vcc.

The emitter and collector of a PNP transistor 52 used as switching means are connected to the collector and base of the transistor 14, respectively, and the pulse processing circuit 60 is connected to the base of the PNP transistor 52. This pulse processing circuit 60 receives the drive signal Sd output from the CPU 40, and similarly
The drive signal is input at the input of the synchronization pulse output from
Since Sd becomes “L” level, this drive signal Sd
is supplied to the base of the PNP transistor 52 as a switching signal Ss. Also, transistor 1
The cathode side of a diode 54 is connected to the base of 4. The anode side of this diode 54 is grounded, and together with the coupling capacitor _C1 , it constitutes a lower end clamp circuit. A discharge diode 56 is arranged between the base and collector of the transistor 14.

Next, the operation of the optical coordinate input device according to the present invention will be explained with reference to the waveform diagram of FIG.

First, the synchronization pulse from the CPU 40 {Figure 3a
Reference} is input to the switching circuits 12 and 22,
Switch SW 1 of the switching circuit 12 and switch SW ₁ of the switching circuit 22
Since the switch corresponding to LED ₁ is closed, the collector voltage Vp of phototransistor PT ₁ drops instantaneously due to switching noise, as shown in FIG. 3c. On the other hand, at the time when the synchronization pulse is input to the switching circuit, the drive signal Sd is held at the "L" level, and the synchronization pulse is simultaneously input to the pulse processing circuit 60. Therefore, the pulse processing circuit 60 outputs the "L" level drive signal Sd as the switching signal Ss to PNP only from the fall of the synchronizing pulse to the rise of the drive signal Sd.
Since the voltage is supplied to the base of the transistor 52 and the transistor 52 is turned on, a voltage is applied to the base of the transistor 14 via the resistors R ₁ and R ₂ and the emitter and collector of the PNP transistor 52, and as shown in FIG. As shown, a current Is flows. Therefore, the base voltage of transistor 14
As shown in FIG. 3d, Vb is a predetermined voltage, and the base-emitter voltage Vbe of the transistor 14 (≒
0.6V) and is held at a voltage slightly greater than the base bias voltage set by resistor _R3 . As a result, as shown in FIG. 3e, the transistor 14
Base current Ib (shaded waveform) flows through the base current Ib (shaded waveform), and its collector voltage falls, so the coordinate signal has a third
The noise signal N indicated by the broken line in FIG. f is no longer added.

This operation of erasing the noise signal N is performed by a pulse processing circuit 6 that performs an AND process between the drive signal Sd output from the CPU 40 and the synchronization pulse shown in FIG. 3a.
According to the switching signal Ss output from 0,
Even though the light-emitting element is switched and connected by the switching circuit 22 in the off state, the noise signal N generated when the switching circuit 12 switches and connects the light-receiving element corresponding to this light-emitting element, and this light-receiving element receives light. The transistor 52 generates disturbance light and the operating voltage that varies between the light receiving elements from the time the light receiving element is switched and connected until just before the light emitting element switched at the same time as the light receiving element starts lighting. Noise is eliminated by forcibly increasing the base voltage Vb and passing the base current Ib through the transistor 14 for dynamic clamping.

The drive signal Sd for lighting the light emitting element is
According to the synchronizing pulse shown in FIG. 3a output from the CPU 40, one selected light emitting element and one light receiving element are selected and connected by the pair of switching circuits 12 and 22. It consists of three pulse signals that repeat a set of "L" and "H" levels three times in order to cause the element to turn off and turn on only three times. When this drive signal is supplied to the drive circuit 24, the LED ₁ is driven and three optical signals Sp are output, so the phototransistor PT ₁ receives these optical signals and becomes conductive. That is, the resistances R ₁ , R ₄ ,
A current flows through the switch _SW1 and the collector/emitter of the phototransistor _PT1 , and the collector voltage Vp of the phototransistor _PT1 falls continuously in a pulsed manner. Therefore, ₃ is connected to the base of the transistor 14 via the coupling capacitor C1.
Since the negative pulse voltage {see FIG. 3 d} is applied, the base current Ib falls continuously in a pulsed manner as shown in FIG. 3 e. Therefore, the collector voltage of the transistor 14 rises, and a coordinate signal consisting of three pulse signals is output from the output terminal 16. The CPU 40 counts pulses by inputting this coordinate signal, and counts the pulses to a predetermined number of "3".
is obtained, so it is determined that there is no coordinate input.

When the collector voltage Vp of the phototransistor PT ₂ to be scanned next is reduced due to its characteristics, ambient light, etc. (see Figure 3c),
When the synchronization pulse is output from the CPU 40, the collector voltage Vp further drops significantly due to switching noise. In this case, the pulse processing circuit 6
Since the PNP transistor 52 is switched to the ON state by the switching signal Ss from 0, the current Is is applied as described above. On the other hand, when the level of the collector voltage Vp of the phototransistor PT ₂ decreases significantly, the cathode side of the diode 54 changes to the negative side, and the voltage that changes to the negative side from this anode-cathode voltage Vd (≒0.6V) Correspondingly, a current Id flows as shown in FIG. That is, the diode 54 has a forward Zener voltage value between the base and emitter of the transistor 14.
The base current Ib of the transistor 14 is lower than Vbe by the forward Zener voltage value Vd of the diode 54.
In order to reach a clamp voltage value sufficient to cut off the voltage, a clamp operation is performed in which the base voltage Vb of the transistor 14, which has become too low, is corrected by supplying a clamp current Id. Therefore, the base voltage Vb of the transistor 14 is corrected by the currents Is and Id as shown in FIG. 3d, and is maintained at a predetermined voltage higher than its base bias voltage. Therefore, as shown in Figure 3e, the base current
Ib flows, and the noise signal N is no longer included in the coordinate signal.

Next, the CPU 40 outputs a pulse signal forming the drive signal Sd, and when the LED ₂ emits light, the phototransistor PT ₂ becomes conductive and its collector voltage Vp falls, so that the base voltage Vb of the transistor 14 also falls. In this case, the current Id flows through the diode 54 due to the clamping operation, as shown in FIG. 3d, and the voltage Vd is corrected.
The falling level of base voltage Vb is clamped (lower end clamp). Furthermore, when the pulse signal forming the drive signal Sd falls and the collector voltage Vp of the phototransistor PT ₂ rises, this rising voltage is applied to the base of the transistor 14 via the coupling capacitor C ₁ by the clamping operation of the diode 54. and also raises the base voltage Vb. Therefore, even when the collector voltage Vp level of the phototransistor PT ₂ is lowered, the base current flows through the transistor 14, so that the output terminal 16 outputs a coordinate signal consisting of three pulse signals. By the way, CPU4
On the 0 side, it can be accurately determined that there is no coordinate input.

By the way, when the base current Ib flows through the transistor 14, the potential of the base increases due to excessively accumulated carriers, so that the rise and fall of the base current Ib are delayed, as shown by the dashed line in FIG. 3e. Furthermore, the clamping current Id flows into the coupling capacitor _C1 due to the clamping operation of the diode 54, but since there are variations in the amount of this current Id flowing into it, the rise of the base current Ib becomes even more unstable. However, in the device of the present invention, since the diode 56 is disposed between the base and collector of the transistor 14, the excess clamp current Id flowing into the coupling capacitor _C1 flows into the collector of the transistor 14 via the diode 56. , is discharged from the emitter. Excess accumulated carriers at the base of transistor 14 also flow through diode 56 to its collector and are discharged from its emitter. Therefore, since the potential of the base of the transistor 14 with respect to the collector can always be held constant, the base current Ib having a predetermined waveform can be obtained and its rise time is also constant. Therefore, the coupling capacitor C ₁ ,
Reduce the capacitance of C ₃ and reduce the pulse width of the optical signal Sp.
Even if the pulse period is set to a small value of 30 μsec (usually 1 msec), the base current Ib is supplied to the transistor 14 with a predetermined waveform. And diode 54
When the base voltage Vb of the transistor 14 is clamped at the lower end by the coupling capacitor _C1 , the base current Ib is always supplied to the transistor 14 in response to the optical signal Sp, so that the input device of the present invention can operate at high speed ( The presence or absence of coordinate input can be reliably and accurately detected even by scanning).

Here, when the coordinate input operation is performed, for example, the LED ₂ which is a light emitting element and the phototransistor PT ₂ which is a light receiving element are connected to each SW ₂ of a pair of switching circuits 22 and 12.
When the phototransistor PT2 is closed and selected, a photo signal is generated via the switching circuit 12, which is a detection signal when three light pulses are intermittently generated between the LED ₂ and the phototransistor _PT2 , and the light is blocked by a finger or the like. The collector voltage Vp of the transistor PT ₂ is in a state in which the rectangular voltage waveform portion shown as oscillating at three points in the voltage decreasing direction in response to the light pulse of the LED ₂ shown in Figure 3c has been removed. . The collector voltage Vp in a state in which the three rectangular wave components caused by this optical pulse are removed is lower than the operating level of the phototransistor PT ₁ when it does not receive the optical pulses from the LEDs ₁ and ₃ shown in Figure 3c. A state is reached in which the noise signal N generated in the voltage drop direction at the time of switching the light receiving element is synthesized with a voltage component that has relatively little fluctuation due to disturbance light higher than the operating level of transistor PT _{3 or} variations in elements between phototransistors. .

The collector voltage Vp of the phototransistor PT ₂ via the switching circuit 12 when the optical path of this optical pulse is blocked is the capacitor that is the AC coupling means.
The waveform is shaped via _C1 in the following steps.

First, when LED ₂ is connected with SW ₂ in the off state and the switching signal Ss is supplied at low level, the LED will turn off according to the low level switching signal Sd.
Positive power supply terminal Vcc → resistor R ₁ → resistor R ₂ → emitter to collector of transistor 52 → base to emitter of transistor 14 → base current Ib that follows the path of ground wire, and positive power supply terminal Vcc → resistor
R ₁ → Resistor R ₂ → Emitter to collector of transistor 52 → Anode to cathode of diode 56 → Collector to emitter of transistor 14 →
A dynamic clamp current Is is applied, which is divided into two parts: an adjustment current for suppressing excessively accumulated carriers following the path of the ground line. When this dynamic clamp current Is is applied, disturbance light, etc. and components of the noise signal N are transmitted to the transistor 1.
Forward Zener voltage value between base and emitter of 4
It is corrected to a constant base voltage Vb that is slightly higher than Vbe. The transistor 14 to which the base current Ib is supplied is connected from the positive power supply terminal Vcc to the resistor R ₁
→ Resistor R ₂ → Collector current continues to flow through the path from the collector of the transistor 14 to the emitter → ground line. Therefore, the voltage value of the output terminal 16 of the amplifier section 50 becomes low level.

Next, when the LED ₂ is turned on and the switching signal Ss changes from low level to high level, the dynamic clamp current of the transistor 52 is cut off in accordance with the switching signal Ss changed to high level. However, the light pulse from the LED ₂ is blocked by the coordinate input operation, and the collector signal Vp of the phototransistor PT ₂ supplied via the switching circuit 12 consists only of components such as disturbance light. The base voltage Vb of the transistor ₁₄ is made sufficient for the clamp voltage Vd clamped by the diode 54 due to the voltage component of this disturbance light etc. via the capacitor C1 and the base bias voltage via the resistor _R3 . It drops towards the higher forward Zener voltage Vbe of transistor 14. However, the base voltage Vb when no optical pulse is received does not fall below the forward Zener voltage Vbe due to the base bias voltage via the resistor _R3 . Therefore, the base current Ib of the transistor 14 is not blocked by voltage components such as disturbance light. Then, the collector current of transistor 14 continues to be energized, and LED ₂ and phototransistor
During the period when PT ₂ is selected, the voltage output from the output terminal 16 of the amplifier circuit 50 remains at a low level indicating a state in which the optical pulse is cut off and does not change.

Another embodiment is shown in FIG. That is,
In this embodiment, instead of the diode 56,
NPN transistor 58 and Zener diode 5
9 is used. The collector and emitter of this NPN transistor 58 are connected to the base and collector of the transistor 14, respectively. The Zener diode 59 is connected to the base of the NPN transistor 58. Therefore, the excess Id of the clamp current and the excess accumulated carriers at the base of transistor 14 flow through NPN transistor 58 to the collector of transistor 14 and are discharged from its emitter.

In the above embodiment, the PNP transistor 52
An FET can also be used instead. In this case, it is possible to further operate the input device at high speed.

(Effects of the Invention) According to the present invention, when switching the switching circuit connecting the base of the bipolar transistor and the light receiving element array, a predetermined voltage is applied to the base by the switching means, and the coordinates applied to the base of the bipolar transistor are By fixing the signal level to a predetermined level using a clamping means and holding the potential of the base of the bipolar transistor to the collector constant by the discharging operation of the diode, switching noise that occurs when switching the switching circuit is reduced. In addition, even if the level at which the light receiving element receives the optical signal changes due to the influence of external light, etc., the base current of the predetermined waveform at the base of the bipolar transistor will not be included in the coordinate signal. It will definitely be added as. Therefore,
It is possible to provide an optical coordinate input device that can send coordinate signals to a personal computer or the like at high speed and accurately.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the optical coordinate input device according to the present invention, FIG. 2 is a diagram showing the entire device of FIG. 1, and FIG. FIG. 4 is a diagram showing signal waveforms of each part, and FIG. 4 is a circuit configuration diagram according to another embodiment of the present invention, and FIGS.
The figure is a diagram showing a circuit configuration of a conventional optical coordinate input device and signal waveforms of each part thereof. 12, 22...Switching circuit, 14...PNP transistor, 52, 58...NPN transistor,
20... Light emitting element array, 30... Light receiving element array, 54, 56... Diode, _C1 , _C3 ... Coupling capacitor, _PT1 to PTn... Phototransistor.

Claims (1)

[Scope of Claims] 1. A plurality of light emitting elements; a plurality of light receiving elements arranged in correspondence to receive optical signals from the light emitting elements; a drive circuit that performs a drive operation to supply drive power based on a drive signal in order to blink the light emitting element; and the drive signal of the drive circuit causes the light emitting element to blink.
a first switching circuit that performs a switching operation to select a specific light emitting element only while the light emitting element is blinked at least once; a second switching circuit that switches and selects an element and outputs a detection signal from the light receiving element; an AC coupling means that removes a DC component from the detection signal via the second switching circuit; a bipolar transistor whose base is connected to a coupling means to amplify the detection signal; and detection via the AC coupling means of an undesired state occurring at the time of switching of the second switching circuit and/or the time of turning off the light emitting element. pulse processing means for generating a switching signal for correcting the signal based on the drive signal; and according to the switching signal of the pulse processing means, applying waveform correction to the connection point between the base of the bipolar transistor and the AC coupling means. dynamic clamping means for applying a voltage for voltage correction in a switching operation and shaping the waveform to a desired constant voltage value; An optical coordinate input device comprising: base current adjusting means for adjusting a base current value in order to adjust the amount of carrier accumulated in the base of the optical coordinate input device. 2. In the optical coordinate input device according to claim 1, the pulse processing means combines the drive signal with a synchronous pulse signal supplied to instruct the second switching circuit to perform a switching operation. an AND circuit that performs AND processing and outputs a switching signal, and the dynamic clamp means converts the voltage applied to the amplifying bipolar transistor into the waveform according to the switching signal from the AND circuit. a switching transistor that performs a switching operation as a voltage source for correction and supplies the voltage for waveform correction from the time when the second switching circuit is switched until just before the light emitting element is next turned on; Characteristic optical coordinate input device. 3. In the optical coordinate input device according to claim 1, the base current adjusting means starts the shunting operation from a forward Zener voltage value and an approximate value between the base and emitter of the amplifying bipolar transistor. An optical coordinate input device characterized in that it is configured to: 4. In the optical coordinate input device according to claim 1, the AC coupling means is constituted by a capacitive element for AC coupling, and between the capacitive element and the base and emitter of the bipolar transistor for amplification. An optical coordinate input device characterized in that the connected diodes constitute a clamp circuit that is activated when the light emitting element is turned on.