JPH0335757B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a sense circuit in a Josephson memory circuit, and more particularly to an AC-driven sense circuit.

(Prior Art) In Josephson memory circuits, a sense gate circuit that reads out stored information plays an important role. Several sense circuits have been proposed in the past, and one example of a sense circuit aiming at higher speed is the sense circuit shown in FIG. Regarding this circuit, please refer to IE Transaction on Electron Devices ED-32.
Volume 3, 1985 (IEEE Transaction on Electron
Devices Vol ED-32 No. 3, 1985). In FIG. 2, 11 is an AND circuit;
12 and 13 are first and second load resistors, 18 is a multi-input OR circuit, 14 is a gate current supply line, 15 is an input line for cell selection, 17 is a memory cell column including a sense gate circuit, and 19 is a logic circuit. Other input lines of the product circuit are shown, and in this figure, one column of the memory cell array is extracted. Furthermore, the sense gate circuits are connected in series.

The operation of this sense circuit is as follows. When an alternating current is applied to the gate current line 14, all of the gate current constantly flows through the sense gate array, which is a superconducting line. In this state, line selection input line 15
When a signal is applied to the memory cell, the sense gate circuit of the selected memory cell switches to a voltage state depending on the information within the memory cell. As a result, the gate current is transferred to the AND circuit 11 through the first load resistor 12. At this time, the sense gate circuit of one memory cell is selected by inputting a column selection signal to the other input line 19 of the AND circuit 11. Therefore, the AND circuit 11 switches and the second load resistor 13
An input signal is applied to the OR circuit 18 through the OR circuit 18, and the OR circuit switches. In this way, sensing of information within the memory cell is performed.

In this circuit, when viewed dynamically, part of the gate current flows to the AND circuit 11 through the first load resistor 12 when the gate current rises. However, since the signal to the input line 19 is normally applied through the decoder circuit, no signal is applied to the input line 19 when the gate current rises. Therefore, the AND circuit will not switch due to dynamic current leakage during the rise of the gate current.

As can be seen from the above operation, in this circuit there is no point where an input signal is applied at any particular timing. Therefore, a high-speed sense circuit can be realized.

(Problems to be Solved by the Invention) However, this circuit has the following drawbacks.
When reading information from a memory cell, there are cells that can be read with one selection signal and cells that require both row and column selection signals. In the former case, it is necessary to input another selection signal like the sense circuit described in this conventional example, and the present sense circuit is optimal. In the latter case, the other inputs of the AND circuit 11 of this sense circuit become useless. Moreover, other inputs are required to switch the AND circuit 11 even though a memory cell has already been selected, which also hinders speeding up.

SUMMARY OF THE INVENTION An object of the present invention is to overcome the drawbacks of the prior art and provide a high speed sense gate circuit.

(Means for Solving the Problems) According to the present invention, in a memory cell array composed of a plurality of memory cells including sense gate circuits, the sense gate circuits in each column are connected in series, and the sense gate columns are connected in series. One end is connected to a reference point, the other end is connected to a gate current supply line and one end of a first resistor, and the other end of the first resistor is connected to a first Josephson junction whose one end is connected to the reference point. the other end and the second
A Josephson sense circuit is obtained which is characterized in that it is connected to the input line of the multi-input OR circuit through the resistor.

(Function) In a memory circuit using memory cells that require both row and column selection when reading information, a selection signal line is not required in the sense circuit. On the other hand, to increase speed, it is desirable to eliminate input signals that require timing. For this purpose, one of the best methods is to use AC drive. In this case, it is necessary to take measures to absorb the leakage current to the output side when the current rises. In the conventional example, an AND circuit played this role, but in the present invention, a Josephson junction plays this role. This eliminates unnecessary input signals and increases speed.

(Embodiment) FIG. 1 is a diagram for explaining an embodiment of the present invention, in which 1 is a Josephson junction, 2 and 3 are first and second load resistors, 4 is a gate current supply line, 5, 6
1 is a cell selection input line, 7 is a memory cell column including a sense gate circuit, and 8 is a multi-input OR circuit. In this figure, one column of the memory cell array is extracted.
Furthermore, the sense gate circuits are connected in series.

The operation of this circuit is as follows. When an alternating current is applied to the gate current supply line 4, all of the gate current constantly flows through the sense gate array, which is a superconducting line. When a signal is applied to the cell selection input lines 5 and 6 in this state, the sense gate circuit of the selected memory cell is switched to a voltage state according to the information in the memory cell. As a result, the gate current is transferred to Josephson junction 1 through the first load resistor 2,
The Josephson junction 1 switches. As a result, the gate current flows into the multi-input OR circuit 8 through the second load resistor 3, switches the OR circuit 8, and the information in the memory cell is read out. However, in this circuit, when viewed dynamically, a portion of the gate current leaks to the first load resistor when the gate current rises. If Josephson junction 1 were not present, the leaked current would flow directly to OR circuit 8, causing OR circuit 8 to switch and malfunction. If the gate current value of the OR circuit 8 is controlled so as not to switch the OR circuit 8 at this time, the operating margin of the OR circuit 8 becomes extremely narrow. In order to prevent the above problem, Josephson junction 1 is necessary. In this circuit, the leakage current flows into Josephson junction 1 and is not input to the OR circuit. Further, the value R of the first load resistance must be set in consideration of the compatibility between the magnitude of the leakage current and the impedance _ZO of the sense gate array. For example, R=
When _ZO is selected, the following relationship holds between the gate current value _Ig , the critical current value _IO of Josephson junction 1, and the leakage current value. i=Z _O /Z _O +RI _g 1/2I _g . Furthermore, since I _O is selected so that i < I _O < I _g , 1/2 I _g < I _O < I _g , and the operating margin of Josephson junction 1 is approximately ±33%. At this time, the first load resistance is
Since impedance matching is achieved with the sense gate array, after the sense gate switches,
Signals propagate with almost no reflections. On the other hand, if we choose R = 2Z _O, for example, some signal reflection will occur because impedance matching is not achieved, but i = 1/3I _g , and the operating margin of Josephson junction 1 is wide at ±50%. be able to. However, since the first load resistance value is a factor that determines the magnitude of the input signal to the Josephson junction 1, if it is chosen too large, the input signal to the Josephson junction 1 will become too small. Here, R= _ZO is set.

In this way, the leakage current when the gate current rises can be absorbed by Josephson junction 1, making it possible to realize a sense circuit with a wide operating margin as described above. As can be seen from the above operation, in this circuit there is no point where an input signal is applied at any particular timing. Therefore, a high-speed sense circuit is realized.

(Effects of the Invention) This circuit is an optimal sense circuit for memory cells that require both row and column selection signals during reading. In this circuit, the dynamic leakage current at the rise of the gate current is absorbed by the Josephson junction, so there is no malfunction, and on the other hand, no extra input signal is required, making it suitable for high-speed operation. Further, the circuit configuration can be simplified, and the yield can be improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention,
FIG. 2 is a circuit diagram showing a conventional example of the present invention. In the figure, 1... Josephson junction, 2,
3, 12, 13...Load resistance, 4, 14...Gate current supply line, 5, 6, 15, 19...Signal input line, 7, 17...Storage cell column including sense gate circuit, 8, 18 ...Multi-input OR circuit, 11...
A logical sum circuit is shown.

Claims (1)

[Claims] 1. In a memory cell array composed of a plurality of memory cells including sense gate circuits, the sense gate circuits in each column are connected in series, one end of the sense gate column is connected to a reference point, and the other end is connected to a gate current supply line and The other end of the first resistor is connected to one end of the first resistor, and the other end of the first Josephson junction is connected to the reference point, and the multi-input OR circuit is connected through the second resistor. Josephson sense circuit, characterized in that it is connected to the input line of.