JPH0335821B2 - - Google Patents
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- Publication number
- JPH0335821B2 JPH0335821B2 JP56152681A JP15268181A JPH0335821B2 JP H0335821 B2 JPH0335821 B2 JP H0335821B2 JP 56152681 A JP56152681 A JP 56152681A JP 15268181 A JP15268181 A JP 15268181A JP H0335821 B2 JPH0335821 B2 JP H0335821B2
- Authority
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- Japan
- Prior art keywords
- silicon layer
- layer
- temperature
- sio
- insulating layer
- Prior art date
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2926—Crystal orientations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H10P14/3808—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/22—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3238—Materials thereof being insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3451—Structure
- H10P14/3452—Microstructure
- H10P14/3458—Monocrystalline
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H10P14/382—Scanning of a beam
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- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係り、特にレ
ーザアニーリングされる非晶質又は多結晶シリコ
ン基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an amorphous or polycrystalline silicon substrate subjected to laser annealing.
従来からシリコン１００基板上に0.25μｍ程度
の熱酸化膜、即ち絶縁層をウエツトO2、1000℃
40分で形成し、更にその上にCVD法（SiH4：630
℃）等によつて多結晶シリコン層を形成してレー
ザビームを照射することで多結晶シリコン層を単
結晶化するレーザアニーリング方法が知られてい
る。 Conventionally, a thermal oxide film of about 0.25 μm, that is, an insulating layer, is deposited on a silicon 100 substrate using wet O 2 at 1000°C.
Formed in 40 minutes, and then CVD method (SiH 4 :630
A laser annealing method is known in which a polycrystalline silicon layer is formed using a method such as 0.degree.
更にシリコン基板上に0.6−1μ厚の熱酸化膜を
形成し、該熱酸化膜上にCVD法により多結晶シ
リコン層を0.1〜0.5μ積層し、該多結晶シリコン
層をキヤプとして熱酸化（〜1000〓）するか、
Si2N4（200〓）層を設けるようになし、このよう
に積層した半導体基板上にレーザを照射して多結
晶シリコン層を単結晶化するレーザアニーリング
方法も知られている。 Furthermore, a thermal oxide film with a thickness of 0.6-1μ is formed on the silicon substrate, a polycrystalline silicon layer of 0.1-0.5μ is laminated on the thermal oxide film by the CVD method, and thermal oxidation (~ 1000〓) or
A laser annealing method is also known in which a Si 2 N 4 (200〓) layer is provided and a laser beam is irradiated onto the semiconductor substrate laminated in this way to convert the polycrystalline silicon layer into a single crystal.
これらレーザアニールによつて多結晶シリコン
層を単結晶化する際に多結晶シリコン層が酸化膜
から剥離してしまう弊害を生じる。この原因につ
いては熱酸化膜と多結晶シリコン又は非晶質シリ
コン層との熱膨張率の違いによつてストレスが掛
つた状態でCVD法等で積層された層にレーザエ
ネルギを与えて多結晶又は非晶質シリコン層を融
解状態とした時にストレスが元に戻ることによつ
て生じるものと説明されている。 When the polycrystalline silicon layer is made into a single crystal by such laser annealing, the polycrystalline silicon layer may be peeled off from the oxide film. The cause of this is that laser energy is applied to the layers stacked by CVD method under stress due to the difference in thermal expansion coefficient between the thermal oxide film and the polycrystalline or amorphous silicon layer. It is explained that this occurs when the stress returns to its original state when the amorphous silicon layer is brought into a molten state.
本発明は上述のような欠点を除去した半導体基
板の製造方法を提供するものであり、その特徴と
するところは基板上に形成する絶縁層、即ち熱酸
化膜と該熱酸化膜上に積層する多結晶シリコン層
又は非晶質シリコン層をスパツタリングにより少
なくとも500℃以下の低温で堆積させるようにし
た半導体基板の製造方法を提供するもので、この
ような方法で得られた半導体基板はレーザアニー
ルに於て酸化膜より非晶質又は多結晶シリコン層
が剥離しない基板を得ることができるものであ
る。 The present invention provides a method for manufacturing a semiconductor substrate that eliminates the above-mentioned drawbacks, and its features include an insulating layer formed on the substrate, that is, a thermal oxide film, and an insulating layer laminated on the thermal oxide film. The present invention provides a method for manufacturing a semiconductor substrate in which a polycrystalline silicon layer or an amorphous silicon layer is deposited by sputtering at a low temperature of at least 500°C or less, and the semiconductor substrate obtained by such a method is not subjected to laser annealing. It is possible to obtain a substrate in which the amorphous or polycrystalline silicon layer does not peel off from the oxide film.
本発明は、500℃以下の低温で非単結晶のSi膜
をSiO2膜上に被着することがSiの溶融時に剥離
を防止する上で必須であるということを本発明者
が新たに見い出すことによつて、なされたもので
ある。そこで、「500℃以下の低温」とした根拠を
以下に述べる。 The present invention is based on the inventor's new discovery that depositing a non-single-crystal Si film on a SiO 2 film at a low temperature of 500°C or less is essential to prevent peeling when Si melts. It was done because of this. Therefore, the rationale for setting the temperature as "low temperature below 500℃" is explained below.
まず、Si薄膜面内応力は、室温（約23℃）で引
張応力が小さく、溶融直前（約1420℃）で圧縮応
力が大きいことが望ましいと言える。そのために
は、第３図に示したSi及びSiO2の伸び（ΔL）対
温度（Ｔ）の関係において、Siの曲線とSiO2の
曲線との交点−堆積温度（Td）に対応−が、で
きるだけ原点に近い方が良い。なお、上述した溶
融直前で圧縮応力が大きいことが望ましいのは、
溶融直前に圧縮応力が充分でないと、Siの溶融に
よる体積収縮の融液の表面張力によつて融液の分
離が生じ易くなるためである。もし、この際に圧
縮応力が充分ならば、融液周辺の未溶融Siが溶融
部へ膨張することにより、体積収縮を補償して融
液の分離を防ぐことができる。 First, it can be said that it is desirable that the Si thin film in-plane stress has a small tensile stress at room temperature (approximately 23°C) and a large compressive stress just before melting (approximately 1420°C). To this end, in the relationship between the elongation (ΔL) and temperature (T) of Si and SiO 2 shown in Figure 3, the intersection of the Si curve and the SiO 2 curve - which corresponds to the deposition temperature (T d ) - must be , it is better to be as close to the origin as possible. In addition, it is desirable that the compressive stress is large just before melting as mentioned above.
This is because if the compressive stress is not sufficient just before melting, separation of the melt tends to occur due to the surface tension of the melt due to volume contraction due to melting of Si. If the compressive stress is sufficient at this time, unmolten Si around the melt expands into the melted area, compensating for the volumetric contraction and preventing separation of the melt.
上記の要求を満足するためには、堆積温度
（Td）を低温化すればよいと言える。ところが、
次の２点により制約が生じる。 In order to satisfy the above requirements, it is sufficient to lower the deposition temperature (T d ). However,
Restrictions arise due to the following two points.
() CVDポリSiは、500℃以下では実際上成長
しない。() CVD poly-Si practically does not grow below 500℃.
() CVDとスパツタリングは、共に低温ほどSi
の膜質が劣化するので、低温化は必要最小限に
しなければならない。() For both CVD and sputtering, the lower the temperature, the higher the Si
Since the film quality deteriorates, lowering the temperature must be kept to the minimum necessary.
一方、上記第３図から、次のことが前提とな
る。 On the other hand, from FIG. 3 above, the following is assumed.
(イ) Ｔ＝23℃〜1420℃で、SiとSiO2は共に熱膨
張と膜内応力（剪断応力）が比例する。(a) At T=23°C to 1420°C, the thermal expansion and internal stress (shear stress) of both Si and SiO 2 are proportional.
(ロ) Siの膨張係数α0は、Ｔ＝23℃〜1420℃で一定
である。(b) The expansion coefficient α 0 of Si is constant at T=23°C to 1420°C.
(ハ) SiO2の膨張係数は、転移点Tg（＝約500℃）
の前後で異なり、Ｔ＜Tgでの膨張係数をα1、
Ｔ＞Tgでの膨張係数をα2とする。(c) The expansion coefficient of SiO 2 is the transition point T g (= about 500℃)
The expansion coefficient at T<T g is α 1 ,
Let α 2 be the expansion coefficient when T>T g .
(ニ) α1＜α2＜α0の関係にある。(d) There is a relationship of α 1 < α 2 < α 0 .
そこで、次に、TdがTgよりも低温領域と高温
領域の各々にある２つの場合において、各々その
領域内でTdをΔTだけ低温化した場合につき、第
４図に基づき考えてみる。すると、それによるSi
とSiO2の単独の収縮は各々、
Si：ΔL0＝α0ΔT
SiO2ΔL1＝α1ΔT（Td＜Tg）
ΔL2＝α2ΔT（Tg＜Td）
となるから、Si／SiO2系でのSiの収縮は、
ΔL0−ΔL1（Td＜Tg）
ΔL0−ΔL2（Tg＜Td）
となり、ΔL1＜ΔL2であるから、常に低温領域で
の収縮（ΔL0−ΔL1）の方が高温領域での収縮
（ΔL0−ΔL2）よりも大きくなる。 Therefore, next, let's consider two cases in which T d is in a lower temperature region and a higher temperature region than T g , and the case where T d is lowered by ΔT in each region, based on Figure 4. . Then, the resulting Si
The individual contractions of SiO 2 and SiO 2 are as follows , respectively : The contraction of Si in the Si/SiO 2 system is ΔL 0 −ΔL 1 (T d < T g ) ΔL 0 − ΔL 2 (T g < T d ), and since ΔL 1 < ΔL 2 , it is always in the low temperature region. The contraction (ΔL 0 −ΔL 1 ) in the high temperature region is larger than the contraction (ΔL 0 −ΔL 2 ) in the high temperature region.
すなわち、このことは、同じ低温化ΔTに対
し、Td＜Tgの場合の方が、より大きな圧縮応力
を約1400℃近辺で生じさせることを意味する。逆
に、Tg＜Tdとした場合には、TdをΔTだけ下げ
ても余り効果は期待できない。また、上述した２
つの制約（）及び（）があるので、余りΔT
を大きくすることもできない。 That is, this means that for the same temperature reduction ΔT, a larger compressive stress is generated near about 1400° C. when T d <T g . Conversely, when T g <T d , even if T d is lowered by ΔT, no significant effect can be expected. In addition, the above-mentioned 2
Since there are two constraints () and (), the remainder ΔT
cannot be made larger.
以上のことから、Td＜Tg＝約500℃とすること
が必須となる。 From the above, it is essential that T d <T g = approximately 500°C.
以下、本発明の１実施例を図面について詳記す
る。 Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図はシリコンウエハー基板１としてＰ型
（100）シリコンを選択し、該基板１上に絶縁層２
として二酸化シリコン（SiO2）をマグネトロン
スパツタリングによつて低温500℃以下（好まし
くは100℃以下）で0.6〜1μを成長速度100〜200
Å／分で形成する。更に該絶縁層２上に同じく非
晶質シリコン層３を形成する。該非晶質シリコン
層はアモルフアスシリコンを選択し、0.5μ厚程度
の好ましくは100℃以下でマグネトロンスパツタ
リングされ、成長速度も絶縁層と同様の100〜200
Å／minに選択する。 In FIG. 1, P-type (100) silicon is selected as a silicon wafer substrate 1, and an insulating layer 2 is placed on the substrate 1.
As silicon dioxide (SiO 2 ) is grown by magnetron sputtering at a low temperature below 500℃ (preferably below 100℃) at a growth rate of 0.6 to 1μ to 100 to 200℃.
Formed at Å/min. Further, an amorphous silicon layer 3 is similarly formed on the insulating layer 2. The amorphous silicon layer is made of amorphous silicon, and is magnetron sputtered to a thickness of about 0.5μ, preferably at 100℃ or less, and the growth rate is 100 to 200℃, which is the same as that of the insulating layer.
Select Å/min.
上記実施例では非晶質シリコン層を選んだがこ
れは多結晶シリコン層３であつてもよく、この場
合も非晶質シリコン層と同様に低温のスパツタリ
ングで積層させることができる。 In the above embodiment, an amorphous silicon layer is selected, but this may also be a polycrystalline silicon layer 3, and in this case as well, it can be laminated by low-temperature sputtering like the amorphous silicon layer.
尚、上記非晶質シリコン層又は多結晶シリコン
層３上に必要に応じてキヤプ用の絶縁層４として
二酸化シリコン層（SiO2）を上述の絶縁層２と
同様に形成することもできる。 Incidentally, a silicon dioxide layer (SiO 2 ) may be formed as a cap insulating layer 4 on the amorphous silicon layer or polycrystalline silicon layer 3, if necessary, in the same manner as the above-described insulating layer 2.
上述のように構成した半導体基板上にcwレー
ザ５等を照射してＡ方向に走査すれば非晶質シリ
コン層又は多結晶シリコン層は融解して単結晶化
がなされる。こうして得られた半導体基板では全
層２，３（又は４）が低温のマグネトロンスパツ
タリングで形成されるためにレーザ照射時に絶縁
層２から単結晶化したシリコンが剥離することが
なくなることを確認した。 When the semiconductor substrate configured as described above is irradiated with a CW laser 5 or the like and scanned in the A direction, the amorphous silicon layer or polycrystalline silicon layer is melted and made into a single crystal. In the semiconductor substrate thus obtained, all layers 2, 3 (or 4) were formed by low-temperature magnetron sputtering, so it was confirmed that the single crystal silicon did not peel off from the insulating layer 2 during laser irradiation. did.
第２図は本発明の他の実施例を示すものであ
り、第１図で示したレーザアニーリングによつて
多結晶シリコン層又は非晶質シリコン層３を単結
晶化した単結晶化層６にダイオード、トランジス
タ、コンデンサ等のデイバイスの上方に層間絶縁
として二酸化シリコン（SiO2）等の絶縁層７を
低温スパツタリングによつて形成し、更に該絶縁
層７上に非晶質又は多結晶シリコン層８を同じく
低温スパツタリングによつて第１図と同様に成長
速度100〜200Å／min程度で成長させる。９は必
要に応じて形成されるキヤプ用絶縁層であり、同
じく低温スパツタリングで形成する。 FIG. 2 shows another embodiment of the present invention, in which the polycrystalline silicon layer or the amorphous silicon layer 3 is made into a single crystallized layer 6 by the laser annealing shown in FIG. An insulating layer 7 of silicon dioxide (SiO 2 ) or the like is formed as interlayer insulation above devices such as diodes, transistors, capacitors, etc. by low-temperature sputtering, and an amorphous or polycrystalline silicon layer 8 is further formed on the insulating layer 7. is grown by low-temperature sputtering at a growth rate of about 100 to 200 Å/min in the same manner as shown in FIG. Reference numeral 9 denotes an insulating layer for a cap, which is formed as necessary, and is also formed by low-temperature sputtering.
次に同じ様にレーザ５を照射して多結晶シリコ
ン層又は非晶質シリコン層８を単結晶化し、更に
該単結晶化したシリコン層に２層目のデイバイス
を形成し、同じ様な工程で３層目、４層目、…の
絶縁層、非晶質（多結晶）シリコン層等の層を形
成することで多層LSIを構成することができる。 Next, the polycrystalline silicon layer or the amorphous silicon layer 8 is made into a single crystal by irradiating the laser 5 in the same way, and a second layer of devices is formed on the single crystal silicon layer, and the same process is performed. A multilayer LSI can be constructed by forming a third layer, a fourth layer, etc. layers such as an insulating layer, an amorphous (polycrystalline) silicon layer, etc.
第２図で示す多層LSI構成の場合には従来の構
成のように、各層をCVD法や熱酸化などで高温
処理しないために多層LSIに必要な低温プロセス
をそのまま利用できるものである。 In the case of the multilayer LSI configuration shown in FIG. 2, unlike conventional configurations, each layer is not subjected to high-temperature processing using CVD or thermal oxidation, so the low-temperature processes necessary for multilayer LSI can be used as is.
本発明は上述のように構成したので絶縁層と多
結晶シリコン層又は非晶質シリコン層とがレーザ
アニーングに於て剥離しないだけでなく、多層
LSI化が極めてスムーズに行なえ、２回、３回の
熱処理によつても低温で絶縁層や非晶質又は多結
晶シリコン層が形成されるために一層目のデバイ
ス等に与える熱的ダメージを低減できる利点を有
するものである。 Since the present invention is configured as described above, not only does the insulating layer and the polycrystalline silicon layer or the amorphous silicon layer not peel off during laser annealing, but also the multilayer
LSI fabrication can be carried out extremely smoothly, and the insulating layer and amorphous or polycrystalline silicon layer are formed at low temperatures even after two or three heat treatments, reducing thermal damage to first-layer devices, etc. It has the advantage of being able to
第１図は本発明の半導体基板の側断面図、第２
図は本発明の半導体基板を用いて多層LSIを作る
工程を説明するための半導体装置の側断面図、第
３図はSi及びSiO2の伸び（ΔL）対温度（Ｔ）の
関係を示す図、第４図はTd＜Tg及びTg＜Tdの２
領域においてTdをΔTだけ低温化した場合におけ
る各々のSiの収縮を示す図である。
１……シリコン基板、２，７……絶縁層
（SiO2）、３，８……多結晶又は非晶質シリコン
層、４，９……キヤプ用絶縁層（SiO2）、５……
レーザビーム、１０……デバイス。
FIG. 1 is a side sectional view of a semiconductor substrate of the present invention, and FIG.
The figure is a side sectional view of a semiconductor device to explain the process of making a multilayer LSI using the semiconductor substrate of the present invention, and Figure 3 is a diagram showing the relationship between elongation (ΔL) and temperature (T) of Si and SiO 2 , Figure 4 shows the two cases of T d < T g and T g < T d.
FIG. 7 is a diagram showing the contraction of each Si when T d is lowered by ΔT in the region. 1... Silicon substrate, 2, 7... Insulating layer (SiO 2 ), 3, 8... Polycrystalline or amorphous silicon layer, 4, 9... Insulating layer for cap (SiO 2 ), 5...
Laser beam, 10...device.
Claims (1)
コン層にエネルギー線を照射して単結晶化する半
導体装置の製造方法において、該二酸化シリコン
層および該非単結晶シリコン層を、スパツタリン
グにより500℃以下の低温であつて前記エネルギ
ー線の照射時に単結晶化されたシリコン層の剥離
が生じない温度で形成することを特徴とする半導
体装置の製造方法。1. In a method for manufacturing a semiconductor device in which a non-single-crystal silicon layer grown on a silicon dioxide layer is irradiated with energy rays to form a single crystal, the silicon dioxide layer and the non-single-crystal silicon layer are sputtered at a low temperature of 500°C or less. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is formed at a temperature that does not cause peeling of a single crystal silicon layer during irradiation with the energy beam.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56152681A JPS5853824A (en) | 1981-09-26 | 1981-09-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56152681A JPS5853824A (en) | 1981-09-26 | 1981-09-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5853824A JPS5853824A (en) | 1983-03-30 |
| JPH0335821B2 true JPH0335821B2 (en) | 1991-05-29 |
Family
ID=15545783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56152681A Granted JPS5853824A (en) | 1981-09-26 | 1981-09-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5853824A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60167352A (en) * | 1984-02-09 | 1985-08-30 | Agency Of Ind Science & Technol | Semiconductor element |
| US5123975A (en) * | 1989-03-28 | 1992-06-23 | Ricoh Company, Ltd. | Single crystal silicon substrate |
| US5372860A (en) * | 1993-07-06 | 1994-12-13 | Corning Incorporated | Silicon device production |
| US5985700A (en) * | 1996-11-26 | 1999-11-16 | Corning Incorporated | TFT fabrication on leached glass surface |
-
1981
- 1981-09-26 JP JP56152681A patent/JPS5853824A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5853824A (en) | 1983-03-30 |
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