JPH0335855B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flip-flop circuit and a frequency divider circuit, and more particularly to a flip-flop circuit and a frequency divider circuit that can easily form a variable frequency divider circuit.

In recent years, as devices such as electronic clocks and brake motor controls have become increasingly integrated (IC), different frequency dividing circuits have been used. Among these, there is a strong desire to realize a variable frequency divider circuit that can easily change the frequency division ratio.

Conventionally, variable frequency divider circuits have configurations such as those that use a resettable counter or those that prepare multiple frequency dividers in advance and switch between them, but both require a large number of elements and are difficult to integrate into an IC. It has the disadvantage of being

SUMMARY OF THE INVENTION An object of the present invention is to provide a flip-flop circuit (referred to as FF) and a frequency divider circuit using the flip-flop circuit, which can easily constitute a variable frequency divider circuit that eliminates the above-mentioned drawbacks.

The FF of the present invention includes a basic flip-flop section formed including first and second gate circuits whose respective inputs and outputs are cross-connected, and a gate circuit of one of the first and second gate circuits. and a control circuit that always sets the circuit to an open state by a control signal regardless of the input signal.

The frequency divider circuit of the present invention includes a basic flip-flop section formed including first and second gate circuits whose respective inputs and outputs are cross-connected, and one of the first and second gate circuits. The flip-flop circuit is constructed by cascading a plurality of flip-flop circuits each including a control circuit that always keeps the gate circuit in an open state by a control signal regardless of the input signal.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the FF of the present invention.

NAND circuit _N1 as the first and second gate circuits whose respective inputs and outputs are cross-connected;
The NAND circuit _N2 has an R-S type FF configuration, and the NAND circuit _N3 and NAND circuit _N4 are added to its input to form a J-K type basic flip-flop section FF1, and the input of N2 is further connected to the NAND circuit _N2 . The FF of the first embodiment is constructed because the output of the gate circuit _G1 is connected to form the control circuit 2 which keeps _N2 open regardless of the input signal.

Next, the operation of this FF will be explained.

First, when "0" is given as a control signal, the output of _G1 becomes "1" and this is given to _N2 . In this case, J-K type FF1 has J=K=
When it is “0”, the output Q maintains its initial state regardless of the input signal pulse Cp, and when J = “0” and K = “1”, it becomes stable at Q = “0” and = “1”, and J = “1”, K
When = “0”, Q = “1” and = “0” are stable, and J =
“1”, K=“1”, Q for each input signal pulse,
It operates as a normal J-K type FF where the FF is reversed.

Next, when "1" is given as the control signal, the output of _G1 becomes "0" and this is given to the input of _N2 . As a result, the output of _N2 is always "1", that is, an open circuit state, regardless of the input signal pulse Cp. As a result, the inverted pulse corresponding to Cp is outputted to the output Q of _N1 .

That is, the FF of this first embodiment operates as a normal JK type FF when the control signal N is "0", and operates as a simple inverter circuit when the control signal N is "1".

When the FF of this first embodiment is viewed as a frequency dividing circuit,
It can be seen that the circuit becomes a type of variable frequency dividing circuit that divides the frequency by 1/2 when N=“0” and does not divide the frequency when N=“1”.

FIG. 2 is a circuit diagram showing a second embodiment of the FF of the present invention.

The circuit of this embodiment has I ² L as shown in FIG.
(Integrated Injection Logic)
It is made up of a FF 11 and a control circuit 12.
This T-type FF 11 is known from Japanese Patent Application Laid-Open No. 55-78622 entitled "I ² L Flip-Flop Circuit" by Kent F. Smith.

In this T-type FF, first and second gates G ₁₁ and G ₁₂ whose respective inputs and outputs are cross-coupled constitute a basic flip-flop section, and include gates G ₁₃ to _{G 17} as control means thereof, Furthermore, a reset input gate _G18 is provided. And this T shape
In FF11, the states of cross-coupling gates G ₁₁ and G ₁₂ are controlled according to the input signal pulse, and outputs Q, ₁ , ₂ are output.
A pulse with a frequency divided by 1/2 of the input signal pulse is output for each.

The control circuit 12 consists of a gate _G19 , one of its two output terminals is connected to the output terminal of the reset gate _G18 and the input terminal of the FF control gate _G13 , and the other output terminal is connected to the cross gate G13. Connected to ₁₂ input terminals.

Next, the operation of the FF in this second embodiment will be explained.

First, when "0" is given as the control signal, the two outputs of gate _G19 are both "1", that is, the open circuit state, so even if this gate _G19 is added, the operation of T-type FF11 will not change. do not.

Next, when "1" is given as the control signal, both outputs of gate _G19 become "0" (almost short-circuited to the ground), so the gate
The outputs of G ₁₃ and G ₁₂ are always in the "1" state (open circuit state) regardless of the input signal. This result gate
Since G ₁₄ and G ₁₁ simply operate as inverters, output signals having inverted waveforms corresponding to the input signals are sent out from ₁ and ₂ .

That is, the FF of this second embodiment operates as a normal T-type FF when the control signal N is "0", and operates as a simple inverter circuit when the control signal N is "1".

Similarly to the FF of the first embodiment described above, the FF of this second embodiment also divides the frequency by 1/2 when = "0".
When N=“1”, it becomes a type of variable frequency dividing circuit that does not divide the frequency.

FIG. 4 is a circuit diagram showing a third embodiment of the FF of the present invention. This FF consists of a T-type FF 21 using I ² L and a control circuit 22, as in the second embodiment described above. The difference from the circuit of the second embodiment is that this T-type FF 21 does not have a reset circuit (gate G ₁₈ in FIG. 2). Accordingly, a gate with three output terminals is used as the gate _G28 of the control circuit, which is connected to the input terminals of the gates _G21 , _G24 , and _G26 , respectively.

The operation of the FF of this embodiment is similar to the FF of the second embodiment described above, when the control signal = "0", the output of the gate _G28 becomes "1" (open state), and the T-type FF operates.
The FF21 operates normally, and when the control signal is "1", the output of the gate _G28 becomes "0", and this is added to the gates _G21 , _G24 , and _G26 , so the outputs of these gates are always "1". (open circuit state),
The input signal passes through gates G ₂₇ , G ₂₅ and G ₂₂ and the inverted version of the signal is obtained as output Q.

Therefore, it can be seen that the FF of this third embodiment is also a type of variable frequency dividing circuit that divides the frequency by 1/2 and does not divide the frequency by half.

The FF of the present invention has been described above in detail using three embodiments, but as is clear from the explanations so far, the FF of these embodiments of the present invention is a normal FF.
By simply adding one gate as a control circuit to the FF, one gate circuit that constitutes the basic flip-flop section of the FF can be put into a circuit state by a control signal, and the normal FF can be converted into an original FF.
It is possible to switch between operation as an inverter and operation as a simple inverter using a control signal.

That is, the FF of the present invention has the effect of providing a FF with multifunctional characteristics with a simple configuration.

Next, a frequency dividing circuit of the present invention configured using the above-described FF of the present invention will be explained.

FIG. 5 is a circuit diagram showing a first embodiment of the first frequency dividing circuit of the present invention.

The first embodiment of the FF of _the present invention shown in _FIG . , the input terminal of the control circuit is grounded to keep the input of the control circuit at a low level.
One of the K-type FF FF ₁ is the output terminal Q and the input terminal Cp.
are connected in sequence to form a cascade circuit, thereby forming the circuit of this embodiment.

Next, the operation of the circuit of this embodiment will be explained.

First, it is assumed that all J and K terminals are kept at the "1" level and a reset signal is applied so that they are reset at the trailing edge of the input signal pulse. In this state, when "0" is first given as the control signal, the output of the control circuit becomes "1" (open circuit state) as described above, and since the control terminal of FF ₁ is grounded, the control circuit Since the output of FF is also “1” (open circuit state), FF ₁ ~
FF ₄ operates normally as a J-K type FF. Therefore, the input signal pulse ei is divided by 1/2 by the FF of each stage, and as a result, the output signal pulse eo is 1/2 of the input signal pulse ei.
The frequency is divided by 16.

Next, when "1" is given as the control signal, the output of the control circuits of FF ₂ to FF ₄ becomes "0" as described above.
Then, one side of the FF cross circuit is opened, so
FF ₂ to _{FF 4} operate as mere inverter circuits, while FF ₁ is always in the state of ="0" and therefore operates normally as a JK type FF regardless of the control signal.

Therefore, in this case, the output signal pulse eo is the input signal pulse ei divided by 1/2.

That is, the frequency dividing circuit of this first embodiment divides the frequency by 1/16 when the control signal = "0", and by 1/2 when the control signal = "1".
It becomes a variable frequency divider circuit.

As described above, by using the FF of the present invention, a variable frequency dividing circuit can be obtained extremely easily.

FIG. 6 is a circuit showing a second embodiment of the first frequency dividing circuit of the present invention.

The difference from the circuit of the first embodiment shown in FIG. 5 is that instead of the FF ₁ shown in FIG. - _FF'1 , which is a K-type FF, is used. In this way, since FF′ ₁ is not related to the control signal at all, the circuit of this embodiment becomes a variable frequency divider circuit of 1/2 frequency division/1/16 frequency division, similar to the circuit of the first embodiment. . Compared to the first embodiment, this embodiment has the advantage that a normal JK type FF can be used as _FF'1 .

FIG. 7 is a circuit diagram showing a third embodiment of the first frequency dividing circuit of the present invention.

The circuit of this embodiment uses FF ₁₁ and FF ₁₂ which are FFs of the present invention using the I ² L inverter shown in FIG.

However, the input gate _G27 in FIG. 4 is combined into one input gate _G31 . Gates _G32 to _G34 are reset control circuits of the circuit, and _FF11 and _FF12 form a known 1/3 frequency divider circuit. The control circuit terminal of FF ₁₁ is grounded to maintain the input of the control circuit at a low level, and the control circuit terminal of FF ₁₂ is connected so that a control signal can be applied directly to the circuit of this embodiment. is made of.

Next, the operation of this circuit will be explained.

First, when the control circuit signal is "0", as is clear from the previous explanation, both FF ₁₁ and FF ₁₂ are in the open circuit state, so the normal T
Since it operates as a type FF and the output of gate _G34 also becomes "1" (open circuit state), the input signal pulse ei
A 1/3 frequency divided wave is output as the output signal pulse eo.

Next, when the control circuit signal is “1”,
FF ₁₂ operates as a simple inverter circuit, and the output of gate G ₃₄ is "0", and the output of gate G ₃₂ is "1" regardless of the outputs of FF _{11 and} FF _12. Therefore, the output of gate G ₃₃ is "0". ”, and FF ₁₁ and F ₁₂ are no longer reset. (The circuit configuration is such that it is reset when the Q outputs of FF ₁₁ and F ₁₂ are both “1”.) Therefore, FF ₁₁ operates as a normal 1/2 frequency divider, and FF ₁₂ operates as a non-frequency divider. Since it operates as a frequency dividing circuit, the 1/2 frequency divided wave of the input signal pulse ei is output from the output of this circuit as the output signal pulse eo.

That is, the circuit of this third embodiment also provides a variable frequency dividing circuit of 1/2 frequency division/1/3 frequency division with an extremely simple configuration.

FIG. 8 is a circuit diagram showing an embodiment of the second frequency dividing circuit of the present invention.

The difference between the first frequency dividing circuit shown in FIG. 5 and the circuit of the first embodiment is that the gates forming the control circuits included in FF ₂ to _{FF 4} in FIG. are combined into a gate G ₄₀ , and FF' ₂ to FF' ₄ are provided with an external control input terminal ₁ to either the first circuit or the second circuit forming the FF cross circuit. A control signal can be applied via the gate circuit _G40 . Therefore, like the circuit of the first embodiment described above, this circuit also becomes a variable frequency dividing circuit that divides the frequency by 1/16 when the control signal is "0" and divides the frequency by 1/2 when the control signal is "1".

In the circuit of this example, each gate of the control circuit is
Since it is not provided in the FF but is provided in one, it is limited to the number of fan-outs of gate G ₄₀ , but if the number of stages is small, it is easier to implement an IC in terms of reducing the overall number of elements. It has the effect of becoming

The frequency divider circuit of the present invention has been explained in detail using four embodiments, but in each case, the frequency divider circuit of the present invention has been explained in detail using four examples.
The use of FFs has the advantage that circuits can be configured extremely easily.

In addition, in the explanation so far, it is assumed to be FF.
Although a J-K type FF and an ^I2LT type FF using a NAND circuit are used as examples, the gist of the present invention is not limited thereto.
-It is applicable to other types of FF such as K-type FF and D-type FF, and although a gate circuit is used as the simplest example of the control circuit, this is also another circuit with the same function. Needless to say, it's a good thing.
Furthermore, although a grounding circuit is simply used as a holding circuit for holding the output of the control circuit in an open state, it is of course possible to use another circuit having the same effect. Furthermore, it goes without saying that the number of FFs used in the frequency dividing circuit is not limited to that of the embodiment, and that the number of FFs corresponding to the frequency division ratio may be used.

As explained in detail above, the FF of the present invention is extremely simple in that one of the cross-connected first and second gate circuits forming the FF can be opened by a control signal regardless of the input signal. Since it has a control circuit (in principle, one gate), it has the effect of providing a multifunctional FF that performs normal FF operation and operation as a mere inverter.

Furthermore, the frequency divider circuit using the FF of the present invention can easily configure a variable frequency divider circuit due to the multifunctionality of the FF. Since there is no need to prepare a peripheral circuit and provide a switching circuit, it has the effect that it can be easily integrated into an IC, which has been difficult in the past.

[Brief explanation of the drawing]

1, 2 and 4 respectively show the first, second and third flip-flop circuits of the flip-flop circuit of the present invention.
FIG. 3 is an explanatory diagram of an I ² L gate, and FIGS. 5, 6, and 7 are a circuit diagram showing an embodiment of the invention, respectively. FIG. 8 is a circuit diagram showing an embodiment of the second frequency dividing circuit of the present invention. In the figure, 1...J-K type FF, 2, 12, 2
2...Control circuit, 11, 21...T-type FF, _N1 to _N4 ...
NAND circuit, _G1 , _G11 ~ _G19 , _G21 ~ _G28 , _G31 ~
G ₃₄ ...Gate, FF ₁ to FF ₄ , FF' ₁ , F' ₂ to F' ₄ ...Flip-flop circuit (FF),...Control signal (control signal terminal), ₁ ...External control input terminal, ei...Input signal pulse , eo…output signal pulse.

Claims (1)

[Scope of Claims] 1 comprising a first and a second logic gate;
a flip-flop unit in which the output of the logic gate is connected to the input of the second logic gate and the output of the second logic gate is connected to the input of the first logic gate, and a flip-flop unit receives a pulse signal and receives the pulse signal; circuit means for inverting the output holding state of the flip-flop section at each flip-flop section; means for fixing the output to a predetermined logic level, and while the first logic gate maintains the open state, a signal having the same period as the pulse signal appears at the output of the first logic gate. A flip-flop circuit featuring: 2 A plurality of flip-flop circuits, the first
and a flip-flop unit including a second logic gate, wherein the output of the first logic gate is connected to the input of the second logic gate, and the output of the second logic gate is connected to the input of the first logic gate, respectively.
an input terminal, an output terminal connected to the output of the first logic gate, circuit means for inverting the output holding state of the flip-flop section every time a pulse signal arrives at the input terminal, a control terminal, and a control terminal connected to the control terminal. While the control signal is being supplied, the first
the second logic gate remains open.
each has means for fixing the output of the first logic gate to a predetermined logic level, and while the first logic gate remains open, a signal having the same period as the pulse signal to the input terminal is applied to the output terminal. a plurality of flip-flop circuits appearing at the terminals; means for supplying a signal to be frequency-divided to the input terminal of the first-stage flip-flop circuit; means for cascading a plurality of flip-flop circuits; means for supplying the control signal to a control terminal of one or a predetermined number of flip-flop circuits selected from the plurality of flip-flop circuits; and an output terminal of a final stage flip-flop circuit. and means for obtaining an output signal from the frequency dividing circuit.