JPH0337194B2 - - Google Patents

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention provides a display device having a plurality of pixels regularly arranged in the horizontal and vertical directions.
The present invention relates to a linear display device that smoothly displays diagonal straight lines.

[Conventional technology]

BACKGROUND ART In raster scanning cathode ray tube displays and flat panel displays such as liquid crystal and plasma displays, a plurality of pixels are regularly arranged in the horizontal and vertical directions. Image storage circuit (frame memory) that stores display information
Since each memory location corresponds one-to-one with each pixel of the display device, the brightness of the corresponding pixel of the display device is modulated according to the stored contents of this memory circuit to perform display. By the way, since the total number of pixels in these displays is limited to, for example, 1280 x 1024, the calculated display position of the bright spot and the actual display position deviate, causing diagonal straight lines to be displayed jaggedly. .
This is generally called jiaggi.

Several proposals have been made in the past in order to improve this jaginess. Among them, the first prior art is JP-A-55-95986 and JP-A-56-95986.
As disclosed in Japanese Patent No. 156873, the brightness of these two pixels is modulated depending on the distance between the calculated display position and the two pixels that sandwich this display position. The second prior art, as disclosed in Japanese Unexamined Patent Publication No. 58-37685, is to provide a sub-deflection circuit in addition to the main deflection circuit in a cathode-ray tube, and to set the bright spot on the cathode-ray tube at a calculated display position. It's getting closer. Japanese Patent Publication No. 59-99486
A third conventional technique disclosed in the publication delays the readout signal from the storage circuit by half a pixel when reading out the storage contents from the image storage circuit in synchronization with raster scanning and generating a brightness control signal. The brightness control signal is obtained by combining the delayed signal and the non-delayed signal. Furthermore, in a fourth prior art disclosed in Japanese Patent Application Laid-Open No. 60-2987, the display performs interlaced display, and the image storage circuit is divided into a color data area and a light emission control data area corresponding to this area. There is. Then, the stored contents of these areas are simultaneously read out, and according to the light emission control data, color data is selectively supplied to the display in fields 1 and 2, and the color data is selectively delayed to horizontally change the pixels. It's shifting.

[Problem that the invention seeks to solve]

In the above-mentioned first conventional technique, since the brightness is proportionally distributed, a plurality of arithmetic operations are required, and the circuit configuration becomes complicated or the calculation time of the central processing unit (CPU) increases. Furthermore, the second prior art requires a highly accurate deflection circuit, making the circuit configuration complicated and expensive. Furthermore, in the third conventional technology, the delay of the readout signal from the storage circuit allows the pixels of the display device to be shifted only in the horizontal direction. Ta. Further, in the fourth conventional technique, an extra storage capacity of the image storage circuit is required.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a linear display device for displaying diagonal straight lines with improved jaggies through a simple circuit configuration and easy control.

[Means for solving problems]

The present invention includes a display having a plurality of pixels arranged regularly in the horizontal and vertical directions, and a memory circuit having a memory location corresponding to each pixel of the display, each memory location of the memory circuit having a memory location corresponding to each pixel of the display. In a display device that performs display by selectively modulating the brightness of the pixels of a display device according to the memory contents of A vector generator that sequentially specifies the memory location of the memory circuit connected to the memory circuit, and a vector generator that stores this luminance signal when the value of the luminance signal from the luminance control circuit is larger than the memory content of the memory location of the memory circuit specified by this vector generator. It is equipped with a comparison control circuit that writes to a memory location of the circuit, and an offset circuit that selectively offsets the horizontal component or vertical component of the output signal of the vector generator depending on the magnitude of the horizontal and vertical components of the straight line, and performs brightness control. The luminance signal from the circuit is characterized by a greater value when the output signal of the vector generator is not offset than when it is offset.

[Effect]

According to the present invention, first, each storage location between the starting point and the ending point of a straight line is sequentially specified, and a luminance signal having a value of, for example, binary "11" is written therein. Next, depending on the magnitude of the horizontal and vertical components of the straight line, shift the storage location where the luminance signal of "11" has been written in the horizontal or vertical direction,
For example, write a brightness signal with a value of binary "01". At this time, the memory location where the value "11" has already been written is left as is. After these processes are completed, a straight line is displayed on the display according to the memory content of each memory location, so the part where jaggies occurred with only the brightness signal of "11" will be replaced by the brightness signal of "01". be compensated.

〔Example〕

FIG. 1 is a block diagram of a first preferred embodiment of the present invention. The vector data generator 100 is, for example, a computer, and generates start point address data (XS, YS), end point address data (XE, YE), and luminance data (Z) of a straight line to be displayed. This is a latch circuit that holds these start point and end point address data. The vector generator 140 is a circuit that repeatedly generates address data for each point connecting the start point and the end point three times in accordance with the start point and end point address data.
This vector generator 14 may be a circuit described in the above-mentioned prior art patent publication, and is configured as follows, for example. That is, the horizontal and vertical generation parts of the vector generator have the same configuration,
It includes a register, a counter, and an adder that adds the contents of these registers and the counter and loads the result into the counter. Also, the horizontal component of the straight line △X
(=XE-XS) and a vertical component ΔY (=YE-YS), and a circuit that determines the magnitude relationship and ratio of these ΔX and ΔY. First, start point address data XS and YS are loaded into respective counters. If ΔX is larger than ΔY, “1” (corresponding to one pixel) is loaded into the horizontal component register, and ΔY/ΔX is loaded into the vertical component register. If ΔY is greater than or equal to ΔX, “1” and ΔX/ΔY are loaded into the vertical and horizontal component registers, respectively. Next, the adder and counter operate every clock, and the integer part of each counter becomes address data (XD, YD). This operation is
This is repeated until the address data (XD, YD) reaches the end point data (XE, YE), and when the address data reaches the end point data, the vector end signal ES is generated. Note that the result of comparing the magnitudes of ΔX and ΔY becomes the offset control signal OS.

Offset circuit 160 includes vector generator 14
Depending on the offset control signal OS from 0, △X
If △Y is larger than △Y, address data XD is selected, and if △Y is larger than △X, address data
Select data YD. Then, in the first vector generation, XD and YD are passed through as they are, and the second vector is generated.
When the vector is generated for the first time (when the first vector end signal ES is received), the selected one of XD and YD is offset by +1. When the vector is generated for the third time (when the second vector end signal ES is received), the selected XD or YD is offset by -1, and the offset is stopped when the third vector end signal ES is received. △X and △Y
When these are equal, this circuit 16 performs no offset. Therefore, the offset circuit 160 includes a ternary counter that counts the vector end signal ES, a multiplexer that selects XD or YD based on the offset control signal OS, and a ternary counter that changes the output of the multiplexer to +1, -1 or +0
It can be constructed from an adder. Note that in this embodiment, the vector generator 140 generates a vector end signal.
Until ES occurs three times, that is, the same address
Holding circuit 120 will not accept new start point and end point address data until the data has been generated three times.

Brightness control circuit 180 receives brightness data from vector data generator 100 and vector generator 14.
Luminance signal according to vector end signal ES from 0
Generate ZC. This luminance signal ZC initially has the same value as the luminance data Z, but the first vector end signal ES reduces its value to half Z, and the third vector end signal changes the value to the new luminance data Z.
accept. Therefore, the brightness control circuit 180
a ternary counter that counts the vector end signal ES;
Depending on the count contents of this ternary counter, it can be constructed from a shift register that loads or shifts the luminance data Z.

The image storage circuit 200, which is a frame memory, is, for example, a random access memory, and has a storage location corresponding to each pixel of the display, and each storage location has a storage capacity of 2 bits. Address data (XO, YO) from offset circuit 160 addresses a storage location in storage circuit 200 and provides read signal ZF to comparison control circuit 220. This comparison control circuit 220 compares the luminance signal ZC and the read signal ZF, and when the value of the luminance signal ZC is larger than the read signal ZF, the luminance signal ZC is
Write to the storage location in storage circuit 200 currently designated as ZO. The combination of storage circuit 200 and comparison control circuit 22 is a conventional circuit similar to the circuit used in the conventional depth buffer method.

The display control circuit 240 addresses the memory location of the memory circuit 20 corresponding to the display position designation of the display 260, and the digital-to-analog (D/A) converter 280 converts the read signal ZF from the memory circuit 200 into an analog signal. Convert. Then, the brightness of the display 260 is controlled by the output signal of the D/A converter 280. When the display device 260 is a raster scanning cathode ray tube, the display control circuit 240 includes a synchronization circuit that controls raster scanning synchronization, and a counter that counts clocks related to this synchronization circuit and generates an address signal for the storage circuit 200. It is equipped with.

Next, the operation shown in FIG. 1 will be specifically explained with reference to FIGS. 2 to 4. FIG. 2 is a diagram showing some of the pixels of the storage circuit 200 and the display device 260, with each circle corresponding to one pixel. Start point address data (XS, YS) and end point address data (XE, YS) generated by the vector data generator 100
The case where YE) corresponds to pixels 2 and 25, respectively, will be explained. These address data are stored in the holding circuit 12.
0, and the vector generator 140 generates the first vector. As mentioned above, in the first vector generation, the offset circuit 160 does not perform offset, so the address data (XO, YO) is applied to pixels 2, 5, 6, 9, 10, 1.
Specify 3, 14, 17, 18, 21, 22 and 25. Since the memory circuit 200 is initially reset, the comparison control circuit 220 stores the luminance signal ZO in the memory locations of the memory circuit 200 corresponding to these pixels.
Write. If the brightness data Z of the vector data generator 100 is "11", the brightness signal ZO is also "11"
It is.

When the first vector generation is completed, the luminance signal
ZC will be "01". Furthermore, since ΔX is larger than ΔY, the offset circuit 160 increases only XD by 1 in the second vector generation. Therefore, the address data (XO, YO) in the second vector generation is pixels 3, 6, 7, 10, 11,
Specify 14, 15, 18, 19, 22, 23 and 26. The pixels that overlap with the pixels at the time of the first vector generation are 6, 10, 14, 18, and 22, and the memory contents of these pixels are not rewritten by the operation of the comparison control circuit 220, and the other pixels 3,
"01" is written in 7, 11, 15, 19, 23 and 26.

When the second vector generation is completed, the vector generator 140 generates a third vector, but at this time the offset circuit 160 offsets only XD by -1. Therefore, the address data (XO, YO) is for pixels 1, 4, 5, 8, 9, 1.
Specify 2, 13, 16, 17, 20, 21 and 24. Some pixels overlap with the pixels at the first vector generation, but pixels 1, 4, 8, 12, 16,
Since pixels 20 and 24 do not overlap, a luminance signal "01" is written to these pixels. Therefore, the display on the display 260 becomes as shown in FIG. Here, the crossed diagonal lines are pixels with a brightness of "11," and the single diagonal lines are pixels with a brightness of "01." A straight line that does not compensate for jaggies is represented by a pixel with a brightness of "11", but in the present invention, this jaggy is compensated for using a pixel with a brightness of "01".

2 and 3 show the case where ΔX is greater than ΔY, but when ΔY is greater than ΔX, the display on the display 260 becomes as shown in FIG. 4. In this case, the offset circuit 160
Optionally shift YD by +0, +1 or -1. In addition, if △X and △Y are equal,
The offset operation of offset circuit 160 is stopped. In this case, vector generator 140 need only generate the same vector of address data once.

FIG. 5 is a block diagram of a second preferred embodiment of the present invention. This embodiment differs from the embodiment shown in FIG. 1 only in that the connection positions of vector generator 140 and offset circuit 160 are reversed. In other words, the offset circuit 160 does not offset the start point and end point address data when the vector is generated for the first time, but offsets the start point and end point address data for the second and third vector generation.
Offset control signal at the second vector occurrence
The start and end address data of the horizontal or vertical components selected by the OS are offset to +1 and -1 to obtain the same effect as the embodiment of FIG.

In the above-described embodiment, when compensating for jaggies,
Although vector generator 140 generated the vector three times, this number could be two (with only a +1 or -1 offset) or four or more times. 4 the same vector
If this occurs more than once, it is necessary to lower the brightness signal as the amount of offset increases. but,
It must be noted that if the amount of offset increases too much, the displayed straight line will become thicker and the resolution will decrease.

〔Effect of the invention〕

As described above, according to the present invention, jaggies are compensated for simply by offsetting the address data generated by the vector generator and changing the luminance signal, so the circuit configuration becomes simple and inexpensive. Moreover, even if these are controlled by the CPU using software, the control can be easily performed. Furthermore, the comparison control circuit 220 can also be used for hidden surface processing etc. using the depth buffer method.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a preferred first embodiment of the present invention, FIG. 2 is a diagram showing pixels, FIGS. 3 and 4 are diagrams showing display examples, and FIG. 5 is a diagram of a preferred first embodiment of the present invention. FIG. 2 is a block diagram of a second embodiment. In the figure, 140 is a vector generator, 160
is an offset circuit, 180 is a brightness control circuit, 20
0 is a storage circuit, 220 is a comparison control circuit, and 260 is a display device.

Claims (1)

[Claims] 1. A display device having a plurality of pixels arranged regularly in the horizontal and vertical directions, and a memory circuit having a memory location corresponding to each pixel of the display device, the memory content of each memory location of the memory circuit. In a display device that performs display by selectively modulating the brightness of the pixels of the display according to the brightness, the brightness control circuit generates a brightness signal and the memory connects the start point and the end point according to the start point and end point data of the straight line. a vector generator that sequentially specifies memory locations in the circuit; a comparison control circuit that writes to a memory location of the storage circuit; and an offset circuit that selectively offsets the horizontal or vertical component of the output signal of the vector generator depending on the magnitude of the horizontal and vertical components of the straight line. A linear display device, characterized in that the luminance signal from the luminance control circuit has a larger value when the output signal of the vector generator is not offset than when it is offset.