JPH0337213B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus, in which a plurality of execution modules are selectively loaded onto a main memory, and a plurality of execution modules having one or more entry points. In a data processing device in which a processing mode is adopted in which sub-modules are used by the execution module, an execution module in which the plurality of sub-modules are made to reside on a main memory and is currently loaded in the main memory. The present invention relates to a data processing device in which a plurality of sub-modules can be used in common.

[Conventional technology]

For example, as shown in FIG.
There are cases where a sub-module commonly used by each execution module is called and executed while the execution module is executing the process.

[Problem that the invention seeks to solve]

In such a case, conventionally, all execution modules are stored in the main memory 4 as shown in FIG.
Alternatively, as shown in FIG. 5, all sub-modules may be connected to each execution module, and all sub-modules may be resident on the main memory 4. The configuration was such that the main module 1 dynamically loads the combined units onto the main memory 4.

However, in the former case shown in FIG. 4, the storage capacity on the main storage device 4 is inevitably large. In the latter case shown in Figure 5, (i) when the execution module loaded on the main memory requires a sub-module, if a method is adopted in which multiple sub-modules are loaded, the sub-modules are・Module loading time becomes a problem, and (ii) multiple sub-modules are statically linked to each execution module, and when one of the execution modules is loaded, the above-mentioned sub-modules are If a method is adopted in which sub-modules are loaded together, it is necessary to hold the above-mentioned combined unit as a single unit on the disk memory, resulting in multiple identical sub-modules existing on the disk memory, and the disk
This is not desirable from the standpoint of efficient memory usage.

[Means for solving problems]

The present invention aims to solve the above-mentioned problems by making the sub-module resident in the main memory, and by making the sub-module commonly available to each execution module that is selectively loaded. It is intended to.

FIG. 1 shows the configuration of an embodiment of the present invention.
Codes 1, 2-1, 2-2, 2-3, 3 in the diagram
4 corresponds to FIGS. 3 to 5, 5 is a disk memory, 6 is a loading routine, and 7-
1, 7-2, ... are individual subroutines,
8 represents the dispatch routine. The loading routine 6 also has a common area 9 and a plurality of branch tables 10-1, 10-2, . . . . In the common area 9, the above branch table 1
In order to inform the dispatch routine 8 of the starting position of 0-1, 10-2, . . . , the starting address of the branch table is written and referred to by the dispatch routine 8.
Further, each branch table 10-1, 10-2, . . . has individual subroutines 7-1, 7-2, .
The storage location of ... on the main storage device 4 is described.

The dispatch routine 8 statically coupled to each execution module 2-1, 2-2, . Function 11-1 to extract the position of the branch table and branch to the address position indicated by the contents of the branch table;
11-2,... are given.

[Effect]

The main module 1 has a function of selectively loading each execution module 2-1, 2-2, . As shown in FIG. 2, it has a function of loading a loading routine 6 statically combined with a plurality of subroutines 7-1, 7-2, . . . onto the main storage device 4. Then, the plurality of subroutines 7-1, 7-2,
. . . and the loading routine 6 resides in the main memory 4, stores the start address of the branch table in the common area 9, and loads the branch table 10-
1, 10-2, . . . the storage locations of the respective subroutines are set above.

When the execution module currently loaded on the main storage device 4 attempts to use the subroutine 7-1, for example, as shown in FIG. -1 is executed.
This causes dispatch routine 11-1
extracts the branch table start address on the common area 9, determines the position of the branch table 10-1 corresponding to the subroutine 7-1, and indexes the branch table 10-1. Then, based on the contents of the table 10-1, a branch is made to a desired subroutine 7-1.

〔Example〕

Loading routine 6 is constructed as follows.

(1) Statically coupled to all submodules with one or more inlets.

(2) Branch table 1 corresponding to all the above entrances
0-1, 10-2, etc. are prepared, and it is possible to branch to each entrance by external declaration. (3) The start address of the branch table is set on the common area 9. However, the dispatch routine 8 is enabled to refer to the starting address.

Dispatch routine 8 is constructed as follows.

(4) All execution modules 2-1, 2-2,...
..., and the branch destination to the above entry point is brought into the routine 8 by the global declaration.

(5) Then, make it possible to branch to each branch destination.

(6) Also, set the argument address list (return address) of the branch destination module as the return address of the routine 8.

〔Effect of the invention〕

As explained above, according to the present invention, sub-modules are made to reside on the main memory, and the execution module loaded on the main memory can branch processing to any entry point of the plurality of sub-modules. It becomes possible to do so.

[Brief explanation of drawings]

FIG. 1 shows the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the processing mode, and FIGS. 3 to 5 are explanatory diagrams for explaining the prerequisite problems of the present invention. In the figure, 1 is the main module, 2-1, 2-
2, . . . are execution modules, 3 and 7-, respectively.
1, 7-2, ... are sub modules, 4 is the main memory, 5 is the disk memory, 6 is the loading routine, 8 is the dispatch routine, 9
10-1, 10-2, . . . are branch tables, and 11-1, 11-2, . . . are branch functions.

Claims (1)

[Claims] 1 A main module, a plurality of execution modules that are selectively loaded onto the main memory by the main module, and a plurality of execution modules that are used by each execution module during execution of processing in each execution module. A data processing system comprising a plurality of sub-modules having one or more entrances, wherein the main module, one of the execution modules, and the plurality of sub-modules are resident on a main memory to execute processing. In the device, a loading module is statically coupled to the plurality of sub-modules and has at least a branch table indicating the entrance of each of the sub-modules.
The routine is statically coupled with the plurality of sub-modules and configured to reside on the main storage device, and the contents of the branch table are loaded into each of the plurality of execution modules to execute the contents of the branch table. A dispatch routine for branching to one of the sub-modules instructed by the main module is statically coupled, and the loading routine and the plurality of sub-modules are connected to the main module by the main module. A data processing device characterized in that said execution module loaded and resident on a storage device and coupled with said dispatch routine is selectively loaded onto said main storage device by said main module.