JPH0337219B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dual address control scheme that allows a receiver with one address decoder to operate similarly to a receiver with multiple address decoders.

As shown in Fig. 1, address signals are sent from the central controller CC to a plurality of receivers RCV1 to
Specify one of RCVn and switch SW1~
In a system that controls on/off, etc. of one of SWn, receivers RCV1 to RCVn
1 of the configuration corresponding to the addresses respectively assigned to
Address recorders are provided. Therefore, when looking at address decoders, only those designated by the address signal perform an output operation, resulting in a low utilization rate.

Furthermore, in a system that specifies switches etc. using only address signals and controls states such as on and off, for example, an address signal for on control and an address signal for off control assigned to each switch are used. Therefore, the receiver must be provided with two address decoders.

SUMMARY OF THE INVENTION An object of the present invention is to add a simple configuration to one address decoder so that it can decode a plurality of address signals as if it were equipped with a plurality of address decoders. Examples will be described in detail below.

FIG. 2 is a block diagram of the main part of the embodiment of the present invention. 1 is an address decoder, an address signal a is input to a terminal SI, and an address can be set to terminals A1 to A4 from the outside. It includes a shift register that performs serial-to-parallel conversion of the address signal a, and a gate circuit that performs a match comparison between the set address and the parallel-converted input address signal, and is an integrated circuit. Reference numeral 2 denotes a flip-flop, and the output signal b of the address decoder 1 is applied to its clock terminal C. Also, 3 and 6 are resistance,
4 is a capacitor, and 5 is a diode, which constitute an initial set circuit of the flip-flop 2.

This embodiment is for the case where a 4-bit address signal is used, and terminals A1 to A3 of the address decoder 1 are set to "1", "0", and "0", respectively.
The case is shown in which "1" is set, the output signal c from the terminal of flip-flop 2 is applied to terminal A4, and the least significant bit of the set address is switched between "0" and "1". Further, the output signal c from the terminal of the flip-flop 2 is applied to the data terminal D, the set signal is applied to the set terminal S by the above-mentioned initial set circuit, and the reset terminal R is grounded. The output signal corresponding to the input address signal a is the output signal b of the address decoder 1 as OUT1.
Alternatively, the output signal of the terminal Q of flip-flop 2 can be used as OUT2.

FIG. 3 is an explanatory diagram of the operation, where a is the input address signal a, b is the output signal b of the address decoder 1,
c shows an example of the output signal c of the terminal of the flip-flop 2. When flip-flop 2 is set by initial set, address decoder 1
Since "0" is added to terminal A4 of , the set address becomes "1010". address signal a1-a
4 is "1010", the output signal b of the address decoder 1 becomes "1", the flip-flop 2 performs an inverting operation at the rise of the output signal b, and the output signal c of the terminal becomes "1". Therefore, the set address of address decoder 1 is "1011".

Next, when the address signals a1 to a4 become "1011", the output signal b of the address decoder 1 becomes "1" again, and at its rising edge, the flip-flop 2
performs an inversion operation, and the output signal c of the terminal becomes "0". Therefore, the set address of address decoder 1 is "1010", which is the same as the beginning.

As mentioned above, address signals a1 to a4 are set to “1010”.
Then, the terminal Q of flip-flop 2 is “0”
Therefore, for example, when a switch is turned on, the next address signals a1 to a4 become "1011".
At this time, since the terminal Q of the flip-flop 2 becomes "1", the switch can be controlled to turn off. That is, one address decoder 1 can decode two address signals. Also, the output signal c of the terminal of flip-flop 2 is sent to the terminal A of address decoder 1.
It is also possible to have a configuration in which it is added to any one terminal or a plurality of terminals from A4 to A4. As another modification example, by adding more flip-flops and connecting them in cascade, and connecting the output terminal of each flip-flop to the address setting terminal of address decoder 1, one address decoder 1 can be used to decode multiple address signals. It can be operated for any purpose.

As explained above, the present invention allows one address decoder to operate for decoding at least two address signals.
The utilization rate of the address decoder can be improved to provide an economical configuration, and it can be applied to various control systems.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an example of a control system, FIG. 2 is a block diagram of essential parts of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of operation. 1 is an address decoder, 2 is a flip-flop, 3 and 6 are resistors, 4 is a capacitor, 5 is a diode, SI is an address signal input terminal, A1 to A4
is a terminal for setting the address.

Claims (1)

[Claims] 1. A device having a plurality of terminals for externally setting an address and a terminal for inputting an input address signal,
It is equipped with an address decoder 1 that performs a match comparison between an input address and a set address, and a flip-flop 2 that performs an inverting operation by inputting the output signal of the address decoder 1 to a clock terminal and feeding back an inverted output terminal output to a data terminal. , a dual address control characterized in that the output signal of the flip-flop 2 is applied to at least one terminal for address setting of the address decoder, and the two input address signals are alternately decoded by the address decoder. method.