JPH0337729B2 - - Google Patents
Info
- Publication number
- JPH0337729B2 JPH0337729B2 JP56212105A JP21210581A JPH0337729B2 JP H0337729 B2 JPH0337729 B2 JP H0337729B2 JP 56212105 A JP56212105 A JP 56212105A JP 21210581 A JP21210581 A JP 21210581A JP H0337729 B2 JPH0337729 B2 JP H0337729B2
- Authority
- JP
- Japan
- Prior art keywords
- scanning
- single crystal
- energy
- width
- energy line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3238—Materials thereof being insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H10P14/3808—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H10P14/3818—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H10P14/382—Scanning of a beam
Landscapes
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は、例えば絶縁物上に形成された非単結
晶半導体層をエネルギ線照射により単結晶化する
方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for single crystallizing a non-single crystal semiconductor layer formed on an insulator by irradiating energy beams.
半導体基板例えばシリコン（Si）基板表面を被
覆する二酸化シリコン（SiO2）膜のような絶縁
物上に、多結晶シリコンまたは非晶質シリコン層
を形成し、これにレーザ・ビーム或いは荷電粒子
線（以下エネルギ線と総称する）を照射すること
により単結晶化する方法が既に種々提唱されてい
る。 A polycrystalline silicon or amorphous silicon layer is formed on an insulating material such as a silicon dioxide (SiO 2 ) film that covers the surface of a semiconductor substrate, such as a silicon (Si) substrate, and is then irradiated with a laser beam or a charged particle beam ( Various methods have already been proposed for single crystallization by irradiation with energy beams (hereinafter collectively referred to as energy beams).
例えば第１図ａの要部上面図及び同図ｂのＢ−
Ｂ矢視部断面図に示すように、シリコン基板１上
に加熱酸化法によりSiO2膜２を形成し、該SiO2
膜２に一部を選択的に除去して開口３を設け、シ
リコン基板１の表面を露出させ、この露出せる表
面上を含むSiO2膜２上に非単結晶シリコン層４
を化学気相成長（CVD）法等により形成する。 For example, the top view of main parts in Figure 1a and B- in Figure 1b.
As shown in the cross-sectional view of arrow B, a SiO 2 film 2 is formed on a silicon substrate 1 by a thermal oxidation method, and the SiO 2
A portion of the film 2 is selectively removed to form an opening 3 to expose the surface of the silicon substrate 1, and a non-single crystal silicon layer 4 is formed on the SiO 2 film 2 including the exposed surface.
is formed by chemical vapor deposition (CVD) or the like.
次いで非単結晶シリコン層４がシリコン基板１
の表面と直接接触している開口３部を始点として
スポツト状のエネルギ線５をＸ方向（エネルギ線
５の方向）に移動させる。このように非単結晶シ
リコン層４はエネルギ線５の照射を受けると溶融
し、エネルギ線５が通過してしまうと再び凝固す
る。この時エネルギ線の中心部が通過した部分は
単結晶層６が形成されるが、その上側及び下側に
は多結晶層６ａ，６ｂが形成される。その理由は
エネルギ線の直径方向に対する強度分布は、中心
部で大で外側に行くにつれて小さくなる所謂ガウ
シヤン分布をしているためである。即ち中央部は
開口３において基板１の表面と接触しているの
で、基板１の結晶方位に従つて固相部が成長して
単結晶層６が形成されるが、その両側の周辺部の
方が温度が低いので中央部より先に凝固してしま
う。その際近傍に無数に存在する結晶粒を核とし
て固相が成長するので周辺部は多結晶層６ａ，６
ｂとなつてしまう。 Next, the non-single crystal silicon layer 4 is applied to the silicon substrate 1.
The spot-shaped energy ray 5 is moved in the X direction (the direction of the energy ray 5) starting from the opening 3 that is in direct contact with the surface of the spot. In this way, the non-single crystal silicon layer 4 melts when irradiated with the energy beam 5, and solidifies again when the energy beam 5 passes through. At this time, a single crystal layer 6 is formed in the portion through which the center of the energy beam passes, and polycrystalline layers 6a and 6b are formed above and below the single crystal layer 6. The reason for this is that the intensity distribution in the diametrical direction of the energy line has a so-called Gaussian distribution, which is large at the center and becomes smaller toward the outside. That is, since the central portion is in contact with the surface of the substrate 1 at the opening 3, a solid phase portion grows according to the crystal orientation of the substrate 1 to form a single crystal layer 6, but the peripheral portions on both sides Because the temperature is low, it solidifies before the center. At this time, a solid phase grows with the countless crystal grains existing nearby as nuclei, so the peripheral areas are polycrystalline layers 6a, 6.
It becomes b.
そこで次にエネルギ線５をスポツト径の半分程
下にずらし、上記単結晶層６に重畳（オーバラツ
プ）させて開口３部を始点としてエネルギ線を図
の左方向へ移動させる。このようにすると上記多
結晶層６ｂは今度は単結晶化される。 Therefore, the energy line 5 is then shifted downward by about half the spot diameter, overlapped with the single crystal layer 6, and moved to the left in the figure with the opening 3 as the starting point. In this way, the polycrystalline layer 6b is now made into a single crystal.
以下この操作を繰り返すことにより非単結晶層
４を単結晶化し得るが、この方法ではエネルギ線
の走査回数が多くなり能率的ではなかつた。 By repeating this operation, the non-single crystal layer 4 can be made into a single crystal, but this method requires a large number of scans of the energy beam and is not efficient.
このような欠点を解消するため、エネルギ線の
形状或いは強度分布を適切に選択するなどし、非
単結晶半導体層上の溶融された軌跡の中央がその
両端より先に再結晶化するように走査する技術が
提案されている。 In order to eliminate these drawbacks, the shape or intensity distribution of the energy beam is appropriately selected, and scanning is performed so that the center of the melted trajectory on the non-single crystal semiconductor layer recrystallizes earlier than both ends. A technique to do this has been proposed.
第３図はその例であり、これは本発明の先行技
術として本出願人に於いて開発されたものであつ
て、第１図及び第２図に於いて用いた記号と同記
号は同部分を示すか或いは同じ意味を持つものと
する。 FIG. 3 is an example of this, which was developed by the applicant as prior art to the present invention, and the same symbols as those used in FIGS. 1 and 2 refer to the same parts. or have the same meaning.
この改良された技術では、エネルギ線５の横断
面パターンが二つの膨大部分をその走査方向を横
切る棒状部分で結んだ亜鈴状をなし、そして、エ
ネルギ線５の走査方向を横切る軸、即ち、線Ａ−
Ａに対して対称な形状をなしていて、その両側の
膨大部分（例えば球状部分）に於ける最大幅X1
と中央の棒状部分に於ける幅X2とを比較すると
X1＞X2
であり且つ該棒状部分の縁辺は平坦になつている
ものである。従つて、非単結晶シリコン層４が溶
融することに依つて形成される液相の部分は記号
LPで指示してあるようなパターンとなる。即ち、
エネルギ線５の横断面形状は走査方向の長さより
走査方向に直角方向である幅の方が大であるとと
もに前記幅方向に対して所定の強度分布を有する
ものとなして、一回の走査で広い範囲を単結晶化
できるようにし、しかも、このようなエネルギ線
を前の走査領域に一部オーバラツプさせて走査す
ることに依り、単結晶化しきれなかつた周辺部の
多結晶層例えば６ｂを単結晶化するものである。
また、エネルギ線５の横断面形状が、その走査方
向を横切る軸に対して対称な形状であるので、走
査方向を反対方向にしても、その効果に変わるこ
とがなく、エネルギ線５を双方向に走査すること
で単結晶化の効率を向上させることができる。 In this improved technique, the cross-sectional pattern of the energy line 5 has a dumbbell-like shape in which two large portions are connected by a bar-shaped part that crosses the scanning direction of the energy line 5, and A-
It has a symmetrical shape with respect to A, and the maximum width of the huge part (e.g. spherical part) on both sides X 1
Comparing the width X 2 of the central rod-shaped portion, X 1 >X 2 and the edges of the rod-shaped portion are flat. Therefore, the part of the liquid phase formed by melting the non-single crystal silicon layer 4 is indicated by the symbol
The pattern will be as instructed on the LP. That is,
The cross-sectional shape of the energy line 5 is such that the width perpendicular to the scanning direction is larger than the length in the scanning direction and has a predetermined intensity distribution in the width direction. By making it possible to single-crystallize a wide area, and by scanning such an energy beam while partially overlapping the previous scanning area, it is possible to single-crystallize the peripheral polycrystalline layer, for example 6b, which could not be completely single-crystalized. It crystallizes.
In addition, since the cross-sectional shape of the energy line 5 is symmetrical with respect to the axis that crosses the scanning direction, the effect does not change even if the scanning direction is reversed, and the energy line 5 can be used in both directions. The efficiency of single crystallization can be improved by scanning.
この第３図に関して説明した技術に依れば、非
単結晶層を効率良く単結晶化できる点で極めて有
効であるが、それを一層効果的に実施するには或
る条件を採り入れると良いことが判つた。 The technique explained with reference to FIG. 3 is extremely effective in efficiently turning a non-single crystal layer into a single crystal, but in order to make it even more effective, certain conditions should be adopted. I found out.
本発明は、非単結晶層上をエネルギ線で順次走
査する際に、走査領域を一部オーバラツプさせる
させ方に適切な条件を見出し、それに沿うアニー
リングを行なうことに依り、より効率的に広い面
積を単結晶化できるようにするものであり、以下
これを詳細に説明する。 In the present invention, when sequentially scanning a non-single-crystal layer with an energy beam, by finding appropriate conditions for partially overlapping the scanning areas and performing annealing in accordance with the conditions, the present invention can more efficiently spread the area over a larger area. This will be explained in detail below.
第４図は本発明実施例を説明する為の半導体装
置の要部平面説明図である。 FIG. 4 is an explanatory plan view of a main part of a semiconductor device for explaining an embodiment of the present invention.
図に於いて、１１は非単結晶シリコン層、１２
は多結晶シリコン領域、１３ｎはｎ回目の走査で
形成された単結晶シリコン領域、13o+1はｎ＋１
回目の走査で形成された単結晶シリコン領域、１
４ｎはｎ回目の走査エネルギ線、１４o+1はｎ＋
１回目の走査エネルギ線、LPは液相部分、Ａは
エネルギ線走査方向、W1は単結晶シリコン領域
の幅、W2は多結晶シリコン領域の幅、ｄは走査
エネルギ線１４ｎの中心と走査エネルギ線１４o+
１の中心との間の距離をそれぞれ示している。 In the figure, 11 is a non-single crystal silicon layer, 12
is a polycrystalline silicon region, 13n is a single crystal silicon region formed in the nth scan, and 13 o+1 is n+1
Single crystal silicon region formed in the second scan, 1
4n is the nth scanning energy line, 14 o+1 is n+
The first scanning energy line, LP is the liquid phase part, A is the energy line scanning direction, W 1 is the width of the single crystal silicon region, W 2 is the width of the polycrystalline silicon region, d is the center and scanning of the scanning energy line 14n. Energy line 14 o+
1 and the distance from the center is shown respectively.
さて、本発明では、ｎ回目の走査とｎ＋１回目
の走査とを一部重ねて行なう際に
W2＜ｄ＜W1＋W2
なる条件を維持して実施するものである。この条
件に沿つて走査を行なうことに依り、重ね合せが
過剰になつて能率が悪かつたり、重ね合せが不足
して多結晶シリコン領域１２が残留するなどの惧
れは皆無になる。 Now, in the present invention, when the n-th scan and the (n+1)-th scan are partially overlapped, the condition W 2 <d<W 1 +W 2 is maintained. By performing scanning in accordance with this condition, there is no fear that overlapping will result in poor efficiency or that polycrystalline silicon region 12 will remain due to insufficient overlapping.
以上の説明で判るように、本発明に依れば、非
単結晶半導体層をエネルギ線でアニールして単結
晶化するに際し、前記エネルギ線としては、その
横断面パターンが、二つの膨大部分をその走査方
向を横切る棒状部分で結んだ亜鈴状であつて且つ
その走査方向を横切る軸に対して対称な形状を有
すると共にその照射に依つて生成される固液界面
が平面で見てＷ字状をなしていて、しかも、中央
の山部分が両側の谷部分に比較して先行すると共
に略平坦となる横断面強度分布を有するものとな
し、また、或る走査と次の走査とを重ね合わせる
条件を適切に設定することに依り、能率の良い単
結晶化を再現生良く実現できる。 As can be seen from the above description, according to the present invention, when a non-single crystal semiconductor layer is annealed with an energy beam to form a single crystal, the energy beam has a cross-sectional pattern that covers two large portions. It has a bell-like shape connected by rod-shaped parts that cross the scanning direction, and has a symmetrical shape with respect to the axis that crosses the scanning direction, and the solid-liquid interface generated by the irradiation is W-shaped when viewed from the plane. , and has a cross-sectional intensity distribution in which the central peak portion precedes and is substantially flat compared to the valley portions on both sides, and one scan and the next scan are overlapped. By appropriately setting conditions, efficient single crystallization can be achieved with good reproducibility.
第１図乃至第３図は従来技術を説明する図、第
４図は本発明一実施例を説明する為の半導体装置
の要部平面説明図である。
図に於いて、１１は非単結晶シリコン層、１２
は多結晶シリコン領域、１３ｎ，１３o+1は単結
晶シリコン領域、１４ｎ，１４o+1はエネルギ線、
W1は単結晶シリコン領域の幅、W2は多結晶シリ
コン領域の幅、ｄは走査エネルギ線の中心間距離
である。
FIGS. 1 to 3 are diagrams for explaining the prior art, and FIG. 4 is a plan view for explaining the main parts of a semiconductor device for explaining one embodiment of the present invention. In the figure, 11 is a non-single crystal silicon layer, 12
is a polycrystalline silicon region, 13n, 13o +1 is a single crystalline silicon region, 14n, 14o+1 is an energy line,
W 1 is the width of the single crystal silicon region, W 2 is the width of the polycrystalline silicon region, and d is the center-to-center distance of the scanning energy lines.
Claims (1)
結晶化するに際し、 前記エネルギ線としてはその横断面パターンが
二つの膨大部分をその走査方向を横切る棒状部分
で結んだ亜鈴状であつて且つその走査方向を横切
る軸に対して対称な形状を有すると共にその照射
に依つて生成される固液界面が平面で見てＷ字状
をなし、しかも、中央の山部分が両側の谷部分に
比較して先行すると共に略平坦となる横断面強度
分布を有するものとなし、 １回の走査で単結晶半導体領域となる幅をW1
及びその両側に形成される多結晶半導体領域の幅
をW2及びｎ回目の走査エネルギ線とｎ＋１回目
の走査エネルギ線の中心間距離をｄとしたとき W2＜ｄ＜W1＋W2 を維持してｎ回目の走査軌跡にｎ＋１回目の走査
軌跡を重畳させて順次走査を進行させることを特
徴とする非単結晶半導体層の単結晶化方法。[Claims] 1. When scanning a non-single-crystal semiconductor layer with an energy beam to single-crystallize it, the energy beam has a cross-sectional pattern that connects two huge portions with a rod-shaped portion that crosses the scanning direction. It has a bell-shaped shape and is symmetrical with respect to the axis that crosses the scanning direction, and the solid-liquid interface generated by the irradiation has a W-shape when viewed from above, and the peak in the center is It is assumed to have a cross-sectional intensity distribution that precedes and is approximately flat compared to the valley portions on both sides, and the width of the single crystal semiconductor region in one scan is W 1
When W 2 is the width of the polycrystalline semiconductor region formed on both sides of the polycrystalline semiconductor region, and d is the distance between the centers of the n-th scanning energy line and the n+1-th scanning energy line, W 2 <d<W 1 +W 2 is maintained. A method for single-crystallizing a non-single-crystal semiconductor layer, characterized in that the n+1-th scanning trajectory is superimposed on the n-th scanning trajectory to sequentially advance scanning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56212105A JPS58116720A (en) | 1981-12-30 | 1981-12-30 | Singlecrystallization of nonsinglecrystal semiconductor layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56212105A JPS58116720A (en) | 1981-12-30 | 1981-12-30 | Singlecrystallization of nonsinglecrystal semiconductor layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58116720A JPS58116720A (en) | 1983-07-12 |
| JPH0337729B2 true JPH0337729B2 (en) | 1991-06-06 |
Family
ID=16616957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56212105A Granted JPS58116720A (en) | 1981-12-30 | 1981-12-30 | Singlecrystallization of nonsinglecrystal semiconductor layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58116720A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0787177B2 (en) * | 1985-07-03 | 1995-09-20 | 工業技術院長 | Beam annealing method |
| US5496768A (en) * | 1993-12-03 | 1996-03-05 | Casio Computer Co., Ltd. | Method of manufacturing polycrystalline silicon thin film |
-
1981
- 1981-12-30 JP JP56212105A patent/JPS58116720A/en active Granted
Non-Patent Citations (1)
| Title |
|---|
| APPL.PHYS.LETT=1981 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58116720A (en) | 1983-07-12 |
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