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JPH0337759B2 - - Google Patents
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JPH0337759B2 - - Google Patents

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Publication number
JPH0337759B2
JPH0337759B2 JP56151731A JP15173181A JPH0337759B2 JP H0337759 B2 JPH0337759 B2 JP H0337759B2 JP 56151731 A JP56151731 A JP 56151731A JP 15173181 A JP15173181 A JP 15173181A JP H0337759 B2 JPH0337759 B2 JP H0337759B2
Authority
JP
Japan
Prior art keywords
connector
electronic package
motherboard
electronic
mounting structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56151731A
Other languages
Japanese (ja)
Other versions
JPS5853894A (en
Inventor
Mitsuo Takamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP15173181A priority Critical patent/JPS5853894A/en
Publication of JPS5853894A publication Critical patent/JPS5853894A/en
Publication of JPH0337759B2 publication Critical patent/JPH0337759B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Mounting Of Printed Circuit Boards And The Like (AREA)

Description

【発明の詳細な説明】 本発明は、電子パツケージ実装構造、特に、電
子処理装置を構成する電子パツケージの実装を行
うための電子パツケージ実装構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic package mounting structure, and more particularly to an electronic package mounting structure for mounting an electronic package constituting an electronic processing device.

近年、電子処理装置における電子パツケージ実
装構造は、素子の高集積化に伴なつて接続端子数
および発熱への対策から立体実装方式より平面実
装構造に置き換わりつつある。
In recent years, electronic package mounting structures in electronic processing devices are being replaced by planar mounting structures from three-dimensional mounting methods due to the number of connection terminals and measures against heat generation as devices become highly integrated.

しかしながら、同一集積度の電子パツケージを
立体実装構造で構成できるならば、実装密度並び
に実装配線長は平面実装構造よりも向上するとと
もに取り扱いが簡単で保守上有利である。
However, if electronic packages with the same degree of integration can be configured with a three-dimensional mounting structure, the mounting density and the mounting wiring length will be improved compared to the planar mounting structure, and it will be easier to handle and advantageous in terms of maintenance.

しかし、高密度集積回路の使用により、発熱密
度の増大から、高密度集積回路もしくは電子パツ
ケージへの放熱板の取付に伴う電子パツケージの
実装間隔の拡大等により、装置実装密度、実装配
線長は不利となる。
However, due to the use of high-density integrated circuits, the density of device packaging and wiring length are disadvantageous due to an increase in heat generation density and an increase in the mounting distance between electronic packages due to the installation of heat sinks on high-density integrated circuits or electronic packages. becomes.

これらの不利を解決した従来の電子パツケージ
実装構造は、第1図および第2図に示す実装構造
がある。
Conventional electronic package mounting structures that solve these disadvantages include the mounting structures shown in FIGS. 1 and 2.

第1図は従来の電子パツケージ実装構造の一例
を示す斜視図であり、第2図は第1図に示す従来
例の正面図で矢視方向Aから見た図である。
FIG. 1 is a perspective view showing an example of a conventional electronic package mounting structure, and FIG. 2 is a front view of the conventional example shown in FIG. 1, viewed from the arrow direction A.

第1図および第2図に示す従来の電子パツケー
ジ実装構造は電子パツケージ2の相互間を接続す
るための多層配線板であるマザーボードの両面か
らコネクタ5を介して、高密度集積回路3および
放熱板4を搭載してなる電子パツケージ2を対面
実装して構成したものである。
The conventional electronic package mounting structure shown in FIG. 1 and FIG. 4 is mounted face-to-face.

このような電子パツケージの実装構造では第2
図に示すように、同一の軸B上にマザーボード1
の両面からコネクタ5が実装されるため、マザー
ボード1にコネクタピン用の接続穴が同一位置に
コネクタ2個相当分必要となる。
In the mounting structure of such an electronic package, the second
Motherboard 1 on the same axis B as shown in the figure.
Since the connector 5 is mounted from both sides of the motherboard 1, the motherboard 1 requires connection holes equivalent to two connectors at the same position.

しかしながら、高密度集積回路の集積度の向上
によりコネクタピンの数も増加するため、このよ
うなマザーボードの同一位置にコネクタ2個相当
分の接続穴を設けることは物理的に非常に困難で
あるという欠点もある。
However, as the number of connector pins increases as the degree of integration of high-density integrated circuits increases, it is physically extremely difficult to provide connection holes equivalent to two connectors at the same location on such a motherboard. There are also drawbacks.

また、論理変更が生じた時の改造布線を行う場
合に、布線接続および布線のルーテイングが非常
に困難であるという欠点がある。
Furthermore, when performing modified wiring when a logical change occurs, there is a drawback that wiring connection and wiring routing are extremely difficult.

さらにまた、装置の検査、保守の場合に於いて
も検査用プローブの取付が不可能であるという欠
点もある。
Furthermore, there is also the drawback that it is impossible to attach a testing probe when inspecting or maintaining the device.

すなわち、従来の電子パツケージ実装構造は、
接続穴の設置が困難であり、改造布線ならびに検
査用プローブの取付が困難であるという欠点があ
る。
In other words, the conventional electronic package mounting structure is
There are disadvantages in that it is difficult to install connection holes, and it is difficult to modify wiring and attach inspection probes.

本発明の目的は、接続穴の設置、改造布線、な
らびに検査用プローブの取付が容易にできる電子
パツケージ実装構造を提供することにある。
An object of the present invention is to provide an electronic package mounting structure that allows easy installation of connection holes, modification of wiring, and installation of inspection probes.

すなわち、本発明の目的は第2図に示すスペー
スCのデツドスペースを有効に利用することによ
り上記欠点を解決した電子パツケージ実装構造を
提供することにある。
That is, an object of the present invention is to provide an electronic package mounting structure that solves the above-mentioned drawbacks by effectively utilizing the dead space C shown in FIG.

本発明の電子パツケージ実装構造は、高密度集
積回路を搭載した電子パツケージと、前記電子パ
ツケージを表面と裏面とで軸を異にする位置に交
互に実装して接続するコネクタピンを貫通させて
固着したマザーボードと、前記コネクタピンをガ
イドするとともに布線エリアを確保する着脱可能
なコネクタハウジングとを含んで構成される。
In the electronic package mounting structure of the present invention, an electronic package equipped with a high-density integrated circuit and the electronic package are mounted alternately on different axes on the front and back sides, and the connector pins connecting the electronic package are fixed by passing through the electronic package. The device is configured to include a motherboard, and a removable connector housing that guides the connector pins and secures a wiring area.

すなわち、本発明の電子パツケージ実装構造
は、マザーボードの両面に高密度集積回路を搭載
した電子パツケージを実装する構造において、前
記電子パツケージを表面と裏面とで軸を異にする
位置に交互に実装して接続するコネクタピンを貫
通させて固着したマザーボードと該コネクタピン
をガイドし布線エリアを確保する着脱可能なコネ
クタハウジングとで構成される。
That is, in the electronic package mounting structure of the present invention, in a structure in which electronic packages mounted with high-density integrated circuits are mounted on both sides of a motherboard, the electronic packages are mounted alternately on different axes on the front and back sides. The connector housing is comprised of a motherboard fixed to the motherboard through which connector pins are passed through, and a removable connector housing that guides the connector pins and secures a wiring area.

次に、本発明の実施例について、図面を参照し
て詳細に説明する。
Next, embodiments of the present invention will be described in detail with reference to the drawings.

第3図は本発明の一実施例を示す斜視図であ
り、第4図は第3図に示す実施例の正面図で矢視
方向Dから見た図である。
FIG. 3 is a perspective view showing one embodiment of the present invention, and FIG. 4 is a front view of the embodiment shown in FIG. 3, as viewed from the arrow direction D.

第3図および第4図を参照すると、マザーボー
ド1の表面、裏面の両面にコネクタピン6がマザ
ーボード1の表面側のコネクタピン6は裏面側の
コネクタピン6の取付ピツチGの中央に位置する
ように貫通させて取り付ける。したがつてマザー
ボード1の表面に実装される電子パツケージ2と
裏面に実装される電子パツケージ2とは互いに軸
を異にする位置に交互に実装される。
Referring to FIGS. 3 and 4, the connector pins 6 on both the front and back sides of the motherboard 1 are arranged so that the connector pins 6 on the front side of the motherboard 1 are located in the center of the mounting pitch G of the connector pins 6 on the back side. Attach it by passing it through. Therefore, the electronic packages 2 mounted on the front surface of the motherboard 1 and the electronic packages 2 mounted on the back surface are alternately mounted at positions with different axes from each other.

このコネクタピン6にはマザーボード1からの
寸法Eが得られるように凹凸状をし、かつ、コネ
クタピン6をガイドするための穴Fを有した着脱
可能なコネクタハウジング9が取り付けられる。
A removable connector housing 9 is attached to the connector pin 6, which has an uneven shape so as to obtain a dimension E from the motherboard 1, and has a hole F for guiding the connector pin 6.

前記コネクタハウジング9に高密度集積回路
3、放熱板4とソケツト側コネクタ8を有してな
る電子パツケージ2が挿入され、コネクタピン6
とソケツト側コネクタ8のソケツトコンタクトが
電気的に接続される構造となつている。
An electronic package 2 comprising a high-density integrated circuit 3, a heat sink 4 and a socket side connector 8 is inserted into the connector housing 9, and the connector pin 6
The structure is such that the socket contact of the socket side connector 8 is electrically connected to the socket contact of the socket side connector 8.

したがつて論理変更が生じて布線10が必要と
なつた場合には、コネクタハウジング9とマザー
ボード1との間の寸法Eを有するすきまを使用し
ラツピング接続、布線のルーテイングが行なえ
る。
Therefore, when a logic change occurs and the wiring 10 becomes necessary, the gap having the dimension E between the connector housing 9 and the motherboard 1 can be used to perform the wrapping connection and the wiring routing.

ここで、一般に信号接続は同一ラツピングポス
トに最低2本接続できる必要があるが、第3図お
よび第4図に示す実施例では接続部H,Iにおい
て各1本ずつラツピング接続できるため、合計2
本ずつラツピング接続可能となる。
Generally, it is necessary to be able to connect at least two signal connections to the same wrapping post, but in the embodiments shown in Figs. 2
It is possible to wrap and connect books one by one.

また、電子パツケージ2はマザーボード1に対
して表面、裏面で交互に実装されているため従来
技術で述べたようなコネクタピン6の接続穴の問
題も解決できる。
Furthermore, since the electronic package 2 is mounted alternately on the front and back surfaces of the motherboard 1, the problem of connection holes for the connector pins 6 as described in the prior art can be solved.

また装置の検査、保守の場合の検査用プローブ
の接続もコネクタハウジング9の反対側に位置す
る接続部に接続できるため、検査が容易となる。
In addition, since an inspection probe for inspecting or maintaining the device can be connected to the connecting portion located on the opposite side of the connector housing 9, inspection becomes easy.

本発明は以上説明したように電子パツケージを
表面と裏面で軸を異にする位置に交互に実装して
接続するコネクタピンをマザーボードに貫通して
固着させ且つ着脱可能なコネクタハウジングで布
線エリアを設ける構成にすることにより前記従来
技術で述べた欠点を解決できるという効果があ
る。
As explained above, the present invention involves mounting the electronic package alternately on the front and back sides with different axes, allowing the connector pins to be connected to penetrate through the motherboard and fixing them, and using the removable connector housing to cover the wiring area. By providing such a configuration, there is an effect that the drawbacks mentioned in the prior art can be solved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電子パツケージ実装構造の一例
を示す斜視図、第2図は第1図に示す従来例の正
面図、第3図は本発明の一実施例を示す斜視図、
第4図は第3図に示す実施例の正面図である。 1……マザーボード、2……電子パツケージ、
3……高密度集積回路、4……放熱板、5……コ
ネクタ、6……コネクタピン、8……ソケツト側
コネクタ、9……コネクタハウジング、10……
布線、A……矢視方向、B……軸、C……スペー
ス、D……矢視方向、E……寸法、F……穴、G
……取付ピツチ、H……接続部、I……接続部。
FIG. 1 is a perspective view showing an example of a conventional electronic package mounting structure, FIG. 2 is a front view of the conventional example shown in FIG. 1, and FIG. 3 is a perspective view showing an embodiment of the present invention.
FIG. 4 is a front view of the embodiment shown in FIG. 3. 1...motherboard, 2...electronic package,
3... High-density integrated circuit, 4... Heat sink, 5... Connector, 6... Connector pin, 8... Socket side connector, 9... Connector housing, 10...
Wiring, A...Direction of the arrow, B...Axis, C...Space, D...Direction of the arrow, E...Dimensions, F...Hole, G
...Mounting pitch, H...Connection part, I...Connection part.

Claims (1)

【特許請求の範囲】 1 第1の面と該第1の面に対向する第2の面と
を有するマザーボードと、前記第1の面側および
前記第2の面側に突出して配列された複数のコネ
クタピン群と、 前記コネクタピンが貫通し突出する複数の穴を
有し布線空間を確保できるよう前記第1の面また
は前記第2の面と該複数の穴との間に予め定めた
間隔を保つて前記第1の面および第2の面に取り
付けられる複数のコネクタハウジングと、 前記複数のコネクタハウジングの前記複数の穴
から突出する前記コネクタピンと嵌合するコネク
タを有し電子部品を搭載した複数の電子パツケー
ジとから構成したことを特徴とする電子パツケー
ジ実装構造。
[Scope of Claims] 1. A motherboard having a first surface and a second surface opposite to the first surface, and a plurality of motherboards arranged protruding from the first surface and the second surface. a group of connector pins, and a plurality of holes through which the connector pins protrude, and predetermined holes are provided between the first surface or the second surface and the plurality of holes so as to secure wiring space. a plurality of connector housings that are attached to the first surface and the second surface while maintaining intervals; and a connector that fits with the connector pins that protrude from the plurality of holes of the plurality of connector housings, and is equipped with an electronic component. An electronic package mounting structure comprising a plurality of electronic packages.
JP15173181A 1981-09-25 1981-09-25 Electronic package mounting structure Granted JPS5853894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15173181A JPS5853894A (en) 1981-09-25 1981-09-25 Electronic package mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15173181A JPS5853894A (en) 1981-09-25 1981-09-25 Electronic package mounting structure

Publications (2)

Publication Number Publication Date
JPS5853894A JPS5853894A (en) 1983-03-30
JPH0337759B2 true JPH0337759B2 (en) 1991-06-06

Family

ID=15525052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15173181A Granted JPS5853894A (en) 1981-09-25 1981-09-25 Electronic package mounting structure

Country Status (1)

Country Link
JP (1) JPS5853894A (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AR242331A1 (en) * 1984-09-03 1993-03-31 Siemens Ag FRAME FOR ACCOMMODATION OF INSERTABLE ELECTRIC MODULAR GROUPS.
JPS6294695U (en) * 1985-12-04 1987-06-17
JPH06870Y2 (en) * 1987-09-14 1994-01-05 東芝エンジニアリング株式会社 Back panel
US4984133A (en) * 1990-01-19 1991-01-08 International Business Machines Corporation Unitized central electronics complex construction
US5031075A (en) * 1990-01-19 1991-07-09 International Business Machines Corporation Double-sided logic cage
US5317477A (en) * 1992-06-30 1994-05-31 International Business Machines Corporation High density interconnection assembly
CN2626161Y (en) * 2003-04-28 2004-07-14 华为技术有限公司 Doublefaced plugging back plate
JP4621039B2 (en) * 2005-02-22 2011-01-26 株式会社日立製作所 Disk unit
CN109857689A (en) * 2017-11-30 2019-06-07 捷普有限公司 Server

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51104567A (en) * 1975-03-11 1976-09-16 Mitsubishi Electric Corp Keisankiniokeru purintokaadotoritsukeho

Also Published As

Publication number Publication date
JPS5853894A (en) 1983-03-30

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