JPH0337773B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In the frame synchronization method, when establishing frame synchronization of m series of random data using m LSI-based frame synchronization circuits of one series, in the present invention, each series In both cases, the logical sum of the outputs of m frame synchronization code comparison circuits is used to control the clock applied to the frame counter. As a result, frame synchronization is established quickly,
The amount of data lost until synchronization is established can be reduced.

[Industrial application field]

The present invention relates to an improvement of a frame synchronization method that establishes frame synchronization of m series of data by using m pieces of one series of frame synchronization circuits implemented as an LSI.

Here, "m-series data" will be explained.
For example, when a multilevel modulation method is used in a digital radio modulation method, the signal sequences are 4PSK (2 sequences), 16QAM (4 sequences), 64QAM (6 sequences),
The number of data series increases to 256QAM (8 series). The "m sequence" in the present invention is a general term for the number of sequences based on such a modulation method,
Although the data portions of each series are different, they have the same frame synchronization bits.

Now, recently, circuits have been converted to LSI in order to make devices smaller, but since converting to LSI requires a large amount of development costs, it is often necessary to make the circuit as versatile as possible. Therefore, for the frame synchronization circuit, only one series of circuits may be implemented as an LSI, and in the case of m series, m pieces of these circuits may be used to provide versatility. In this case, there is a need for a system that minimizes the amount of data lost until frame synchronization is established.

[Conventional technology]

Fig. 3 is a block diagram of the conventional example, Fig. 4 is an explanatory diagram of the operation of Fig. 3, the numbers on the left are the waveforms of the parts with the same numbers in Fig. 3, and Fig. 5 is the m-series connection of Fig. 3. Figures are shown respectively. Note that 4 in FIG. 5 indicates a frame synchronization circuit section.

Therefore, the operation shown in FIG. 3 will be explained with reference to FIG.

In FIG. 3, input random data is applied to an exclusive OR circuit (hereinafter abbreviated as EX-OR circuit) 11 in the frame synchronization code comparison circuit 1.

Here, the format of this data is shown in Figure 4a.
Or, as shown in b, frame synchronization codes (for example, F1 to F7 and 101...0) are inserted discretely into the data, and n-bit data is inserted between each frame synchronization code. Suppose it is on.

On the other hand, a frame counter 21 in the frame synchronization code generation circuit 2 counts the input clock and sends an output as shown in a or b in FIG. In addition to the generator 22, the output from the latter shown in FIG. 4a or b is also applied to the EX-OR circuit 11.

Therefore, the data and frame synchronization codes are EX−
EX-OR is performed in the OR circuit 11, and its output is added to the AND circuit 12, and only the comparison result of the period of (n+1) bits is taken out (Fig. 4 a or b).
).

That is, when the output of the frame synchronization code moderator 22 has a waveform as shown in FIG. 4a, EX-
This is a case where the comparison results match in the OR circuit 11, and the EX-OR circuit 11 outputs 0 at the frame bit timing as shown in FIG. 4A. By adding the output of this EX-OR circuit and the output of the frame counter 21 shown in FIG. 4a to the AND circuit 12, the AND circuit 12 outputs 0 as shown in FIG. 4a. When the output of the AND circuit 12 is applied together with a clock to an OR circuit (hereinafter referred to as an OR circuit) 3, the OR circuit 3 outputs the clock as is, as shown in FIG. 4a.

Furthermore, when the comparison result in the EX-OR circuit 11 does not match, 1 is added to the OR circuit 3 along with the clock as shown in Fig. 4b, so that the clock is inhibited by 1 bit as shown in Fig. 4b. Then, the frame counter 21 stops incrementing (counting up) by one, and the comparison result of the n-bit period is taken out. Continue this until frame synchronization is established.

Next, when the circuit of FIG. 3 is made into an LSI and used for an m-series frame synchronization circuit, the configuration is as shown in FIG. 5. That is, m pieces (41 to 4m) of LSI frame synchronization circuits are prepared, and frame synchronization of each series is established independently.

At this time, the worst average frame synchronization time T is known as T=〓1+[{(n+1)M-1}/M]・{(1-P)/P}〓・[(n+1)M/ f].

Note that P is the probability (transition probability) of recognizing random data as an error and shifting it by 1 bit, and in the case of one sequence, P = 1/2, so T ₁ = [1+{(n+1)M-1}/M]・[(n+1)M/f] (1)

Here, the worst average frame synchronization time is, for example, the time when synchronization is started from the next code on the right side of F1 to establish synchronization of F1 in Fig. 4-, and the time when synchronization is established with the next F1, n is the number of bits between adjacent frame synchronization codes, M is the number of multi-frames (7 in the above case), and f is the bit rate of one series.

Therefore, since the transmission capacity in the case of m sequences is multiplied by m, there is a possibility that data will be lost by T·m·f bits.

[Problem that the invention seeks to solve]

That is, there is a problem in that as the number of sequences increases, the transmission capacity increases, and the amount of data lost increases accordingly.

[Means for solving problems]

The problem mentioned above is that the output of the frame synchronization code comparison circuit is divided into m and sent to (m-1) frame synchronization circuits, and the remaining part is sent to (m-1) frame synchronization code comparison circuits. This problem can be solved by a frame synchronization method in which an OR circuit 5 is added to calculate the OR with the output, and the clock is controlled by the output of the OR circuit.

[Effect]

In the present invention, in order to reduce the probability of mistaking random data for a frame pulse (retention probability) and increase the transition probability, the outputs of m frame synchronization code comparison circuits 1 are added to the OR circuit 5 to perform an OR operation.

For example, the probability of frame pulse error in random data (retention probability) is 1/2 for 1 series, (1/2) ² for 2 series, and (1/2) ^m for m series, which is 1/2 for 1 series. It decreases compared to the case of .

Therefore, if the clock applied to the frame counter 21 is controlled by the output of the OR circuit 5, the number of times the clock is inhibited due to an erroneous output of the OR circuit will increase, so the time for establishing frame synchronization will become faster, and along with this, The amount of data lost before frame synchronization is reduced.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of the present invention, and FIG. 2 shows an m-series connection diagram of FIG.

Note that the same reference numerals indicate the same objects throughout the drawings, the portions indicated by dashed-dotted lines are the portions added in the embodiment of the present invention, and the reference numeral 6 indicates a frame synchronization circuit section.

As shown in Figure 1, the outputs of the m frame synchronization code comparison circuits are added to the OR circuit 5 of each series and ORed, so there is a low probability that the input random code will be mistaken for a frame code. output,
That is, an output with increased reliability can be obtained.

Therefore, since this output is added to the OR circuit 3 to control the clock, the number of times the clock is inhibited increases, and the time it takes for frame synchronization to become established becomes faster.

In this case, the frame error pulses of all m sequences stop advancing, so the retention probability is (1/2), the transition probability P is 1-(1/2), and the worst average frame synchronization time Tm is as follows. Become.

Tm=〓1+[{(n+1)M-1}/M]・{1/(2 ^m −1)}〓・[(n+1)M/f] (2). Here, A=(n+1)M/f, B=[{(n+1)M-1}/M]A=[(n-1)
−(1/M)] A, equations (1) and (2) become as follows.

T=A+B Tm=A+[1/(2 ^m -1)]B Normally, n is several tens of bits and M is several bits, so A<B, and Tm approaches A as m becomes larger.

Note that the definitions of n, M, and f are the same as in the conventional example.

Fig. 2 shows a connection diagram of the frame synchronization circuits 61 to 6m when the frame synchronization of m series is achieved by converting Fig. 1 into an LSI, and the output of the frame synchronization code comparison circuit is sent to the frame synchronization circuit of other series. So,
Wiring is required to connect each LSI.

This increases the probability of frame synchronization and reduces the amount of lost data.

〔Effect of the invention〕

As explained in detail above, there is an effect that the probability of frame synchronization becomes faster and data loss is reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an m-series connection diagram of Fig. 1, Fig. 3 is a block diagram of a conventional example, Fig. 4 is an operation explanatory diagram of Fig. 3, and Fig. 5 The figure shows the m-series connection diagram of FIG. In the figure, 1 is a frame synchronization code comparison circuit;
Reference numeral 2 indicates a frame synchronization code generation circuit, 3 indicates an OR circuit, and 5 indicates an OR circuit.

Claims (1)

[Claims] 1. A frame synchronization code generation circuit 2 comprising a frame counter 21 and a frame synchronization code generator 22 that generates a frame synchronization code using the output of the frame counter, and a frame synchronization code generator 22 in which the frame synchronization codes are discretely inserted. It consists of a frame synchronization code comparison circuit 1 that compares data with the output of the frame synchronization code generation circuit, and an OR circuit 3 that controls the clock applied to the frame counter by the output of the frame synchronization code comparison circuit. frame synchronization circuit
When establishing frame synchronization of m series of data using 2 frames, the output of the frame synchronization code comparison circuit is divided into m and sent to (m-1) frame synchronization circuits, and the remaining part and ( A frame synchronization method characterized in that an OR circuit 5 is added to take a logical OR with the outputs of m-1) frame synchronization code comparison circuits, and the clock is controlled by the output of the OR circuit. .