JPH0337789B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal delay device, and more particularly to a video signal delay device that delays an input composite video signal by one field using a simple and inexpensive circuit configuration and outputs the delayed signal.

BACKGROUND ART Conventionally, in VTRs and other video signal reproducing devices, noise reduction circuits for reducing noise contained in reproduced composite video signals by utilizing so-called line correlation and field correlation have been equipped with the following functions:
A delay device for one horizontal scanning period (1H) or one field is provided, and the delay device is also used for dropout compensation. As described above, conventional video signal delay devices have been used for various purposes, and FIG. 7 shows a block diagram of an example of this conventional video signal delay device. In the figure, a composite video signal input to an input terminal 1 is supplied to a semiconductor delay circuit section 2. This semiconductor delay circuit section 2 is connected to an input horizontal transfer register 3 in n columns (where n is 2
The vertical transfer registers 4 ₁ to 4n (the above natural numbers) and the output horizontal transfer register 5 are arranged in a matrix.

FIG. 8 shows an example of a detailed configuration of this semiconductor delay circuit section 2. As shown in FIG. In the figure, the semiconductor delay circuit section 2 has (m+1)×n cells (where m is a natural number of 2 or more) arranged in a matrix of m+1 rows and n columns. The n cells _C1 to Cn in the first row _L1 constitute the input horizontal transfer register 3, and similarly, the n cells in the m+1st row Lm+1 constitute the output horizontal transfer register 5. , second row to mth row
(m-1) x n cells 4 ₁₁ to 4n (m-
1) constitutes n columns of vertical transfer registers 4 ₁ to 4n. Here, m-1 cells 4 ₁₁ to 4 ₁ (m-1) arranged in the vertical direction constitute a vertical transfer register 4 ₁ , and similarly cells 4 ₂₁ to 4 ₂ are arranged in the vertical direction.
(m-1) constitutes a vertical transfer register ₄₂ , and cells _4n1 to 4n(m-1) constitute a vertical transfer register 4n.

These n×(m+1) cells are composed of, for example, a charge coupled device (CCD), and the input/output terminals are horizontally transferred in opposite directions to prevent the input/output signals from going in opposite directions. They are provided in registers 3 and 5, respectively. The delay circuit section 2 having the configuration shown in FIG. 8 is a circuit previously proposed by the present applicant in Japanese Patent Application Laid-open No. 134524/1983.

Returning to FIG. 7 again, the composite video signal or horizontal synchronization signal separation circuit 6 from the input terminal 1
The horizontal synchronizing signal is separated and extracted here and then supplied to the horizontal transfer clock generation circuit 7 and the vertical transfer clock generation circuit 8, respectively. The horizontal transfer clock generation circuit 7 receives the input composite video signal as the first signal.
0A, the input composite video signals are in opposite phases to each other as shown in FIGS. 10B and 10C, respectively.
Clock pulses φ _H , n pulses equal to the number of cells in horizontal transfer registers 3 and 5 per 1H period,
It is generated as φ _H and supplied to the horizontal transfer registers 3 and 5, respectively.

On the other hand, the vertical transfer clock generation circuit 8 has a structure in which two monostable multivibrators (monomulti) 11 and 12 are connected in cascade, as shown in FIG. The synchronizing signal is delayed by the time T ₁ by the monomulti 11, and the next monomulti 12 generates a 1H cycle pulse with a pulse width T ₂ as shown in FIG. 10D. The output pulse of the monomulti 12 is output from the output terminal 14.
The vertical transfer clock pulse φ _V is supplied to the vertical transfer registers 4 ₁ to 4 n, respectively, and after being phase-inverted by the inverter 13 and converted into the vertical transfer clock pulse _V as shown in FIG. Vertical transfer register 4 ₁ ~
4n respectively. Here, the generation positions of the above clock pulses φ _V and _V are, for example, the first
As can be seen from Figures A, D, and E, it is selected within the back porch of the input composite video signal, and its pulse width T ₂ is about 1 μs. Furthermore, clock pulses φ _H and _H are configured to occur during periods other than those in which φ _V and _V occur.

As a result, the input composite video signal supplied to the input horizontal transfer register 3 is clocked by the clock pulse φ _H
With the signal waveform as sampled by and _H ,
Configure horizontal transfer register 3. n cells C ₁
~Cn are stored sequentially. That is, the input composite video signal is sequentially transferred in the order of C ₁ → C ₂ → C ₃ →... → Cn based on the clock pulses φ _H , _H , and when n clock pulses φ _H , _H are input ( (period slightly shorter than 1H) n sampling waveforms of the input composite video signal are finished being stored in all cells C ₁ to Cn (horizontal transfer is completed). Next, the clock pulses φ _H , _H are not generated and the clock pulses φ _V , _V are generated within the back porch period as shown in FIG. 10D and E, so that the cell C ₁
The n sampling waveforms held in Cn are transferred in parallel to the cells 4 ₁₁ , 4 ₂₁ , _. . . , 4n ₁ in the first row of the vertical transfer registers 4 1 to 4n, respectively.
This completes the horizontal transfer and vertical transfer for the 1H period.

Thereafter, the same operation as above is repeated, and the n sampling signals held in the horizontal transfer register 3 are transferred m times vertically to the output horizontal transfer register 3.
Thereafter, the clock pulses φ _H and _H are input to the output terminal 9 in series. As a result, mH
A composite video signal to which a delay of is added is taken out from the output terminal 9.

Therefore, the input composite video signal is a composite video signal with 525 scanning lines, and this is
When delaying by 0.5H, the value of m above is selected as 262, and the waveform near the vertical blanking period (V.BLK) of the input composite video signal is shown in Figure 11A, and the waveform of the clock pulse φ _V is shown in the same figure. In the example shown in B, a composite video signal delayed by 262H and having a waveform shown in C in the figure is taken out at the output terminal 9.

Problems to be Solved by the Invention However, the above-mentioned conventional video signal delay device has the following problems:
In order to widen the passband width, it is necessary to increase the repetition frequency of horizontal transfer clock pulses (horizontal transfer clock frequency), and in order to obtain the required delay time, it is necessary to increase the repetition frequency of horizontal transfer clock pulses (horizontal transfer clock frequency). However, since this method requires a large number of registers, there is a problem in that the device becomes expensive.

Furthermore, when performing signal processing using field correlation using a field delay circuit, the number of scanning lines per field for a television video signal is 262.5 (in the case of a 525 scanning line system) or 312.5 due to interlacing. (For 625 scanning lines)
Then, a fraction of 0.5 occurs, whereas the number of lines in the vertical transfer registers 4 ₁ to 4n is a natural number, so the delay time of the conventional delay device described above can only be a natural number times 1H. I was only able to correlate fields that were shifted in a certain direction, either up or down on the screen.

Therefore, the present invention changes the horizontal transfer clock frequency to
A frequency slightly higher than the upper limit frequency of the required frequency band of the video signal is selected, and one field ± of mutually opposite phases obtained by sampling and delaying is selected.
It is an object of the present invention to provide a video signal delay device that solves the above problems by alternately switching and outputting two types of delayed video signals each having a delay time of 0.5H in accordance with the horizontal transfer clock. shall be.

Means for Solving the Problems FIG. 1 is a block diagram showing the configuration of the apparatus of the present invention, in which an input composite video signal such as a luminance signal inputted to an input terminal 1 is supplied to field delay circuit means 20, where Sampling frequency f _S f _S ≒ (2k+1)・(f _H /2) (1) (where, in the above equation, k is a natural number and f _H is the horizontal scanning frequency of the input composite video signal) shown by the following formula. It is sampled by a clock pulse and delayed by one field period minus 0.5H. The delayed sampled signal (first delayed signal) taken out from the field delay circuit means 20 is sent to the switch circuit means 2.
1, while the delay circuit 22 further supplies
The signal is delayed by 1H and is supplied to the switch circuit means 21 after being made into a second delayed signal delayed by a period of 1 field period + 0.5H in total. The switch circuit means 21 is supplied with the clock pulse from the field delay circuit means 20 as a switching signal, and alternately switches the first and second delay signals, respectively, and outputs them as a desired one-field delayed video signal to an output terminal 23. do.

Effect The sampled signal obtained by sampling the input composite video signal at the sampling frequency f _S shown in equation (1) above has a certain 1
In the screen of the field, any two adjacent scanning lines contain time-series composite signals of sample points at time intervals of 1/f _S , as shown by the broken lines and white circles above in Figure 2. This is a time-series composite signal of each sample point displayed with a relative shift of 1/(2f _S ) in the horizontal scanning direction between adjacent scanning lines. Here, when the sampled signal of the scanning line shown in FIG. 2 is taken out from the field delay circuit means 20, the delay circuit 22
From here, the sampled signal of the scanning line 1H earlier than that indicated by the broken line in the same figure is extracted. Therefore, for the sampled signal of the field at the current time shown by the solid line in FIG. 2 before delay, obtained by sampling the input composite video signal at the sampling frequency _fS ,
1 field from the field delay circuit 20
The sampled signal (first delayed signal) to be displayed on the scanning line indicated by a broken line in the same figure 0.5H past is taken out, while the signal to be sampled (first delayed signal) is output from the delay circuit 22 to the same figure 1 field + 0.5H past. Sampled signal (second delayed signal) to be displayed on the dashed scanning line
is being taken out.

The switch circuit means 21 switches the first delay signal and the second delay signal using a clock pulse having the same frequency as the sampling frequency _fS ,
When a sample point of the first delayed signal is output from the field delay circuit means 20, it is selectively outputted;
When the sample point of the second delayed signal is output from the delay circuit 22, it is selectively outputted, so that the signal outputted from the switch circuit means 21 to the output terminal 23 corresponds to each sample of the first and second delayed signals. A composite signal is obtained by combining points alternately in time series. This composite signal is a predicted signal generated from a sampled signal one field past, and is a sampled signal in which sample points are arranged and displayed at each position on the scanning line shown by a black circle in FIG. This corresponds to a signal that is equivalently sampled at a frequency 2f _S that is twice the sampling frequency f _S and delayed by exactly one field.

This allows the sampling frequency f _S to pass through the required frequency using a low frequency clock pulse without using a high frequency clock pulse that satisfies Nyquist's sampling theorem, which is more than twice the upper limit frequency of the required frequency band of the input composite video signal. A bandwidth delayed signal can be obtained. Each embodiment of the present invention will be described below with reference to FIGS. 3 to 6.

Embodiment FIG. 3 shows a block system diagram of a first embodiment of the apparatus of the present invention. In the figure, the same components as in FIGS. 1 and 7 are designated by the same reference numerals. This embodiment is an example in which a delay circuit including the semiconductor delay circuit section 2 shown in FIG. 7 is used as the field delay circuit 20.
Each vertical transfer register 4 ₁ of the semiconductor delay circuit section 2
The number m-1 of each stage (number of rows) of 4n is selected to be the value obtained by subtracting 1 from the number of H in a period of 1 field - 0.5H of the input composite video signal. Therefore, if the input composite video signal has 525 scanning lines, the number of stages in each vertical transfer register is 261 (the value of m above is
262), 311 stages for the 625 scanning line method (the m
The value of is 312). As a result, when the semiconductor delay circuit section 2 performs vertical transfer once every 1H, the input composite video signal is transferred for a period of 1 field - 0.5H (262H in the case of the 525-scanning line system, 625-scanning lines).
In this method, the signal is delayed (312H) and output to output terminal 9.

Here, in this embodiment, the horizontal transfer clock generation circuit 24 generates horizontal transfer clock pulses φ _H , _H with a repetition frequency f _S satisfying the above equation (1) based on the horizontal synchronization signal from the horizontal synchronization signal separation circuit 6 . Therefore, a sampled signal (first delayed signal) sampled at this horizontal transfer clock frequency f _S and delayed for a period of 1 field - 0.5H is extracted from the semiconductor delay circuit section 2. It turns out.
As mentioned above, this horizontal transfer clock frequency f _S is
Since the frequency is less than twice the upper limit frequency of the required frequency band of the input composite video signal and lower than the horizontal transfer clock frequency that satisfies the conventional Nyquist sampling theorem, the number of horizontal transfer register cells and the number of vertical transfer registers are (That is, the number of columns n) can be smaller than in the conventional case, and the structure of the semiconductor delay circuit section 2 can be made inexpensive and compact.

The first delayed signal taken out from the semiconductor delay circuit section 2 constituting the field delay circuit means 20 is supplied via the output terminal 9 to the low-pass filter 25 for removing clock components, where the clock component is removed. The signal is applied to the terminal 26a of the switch circuit 26, while being supplied to the 1H delay circuit 27. The 1H delay circuit 27 constitutes the delay circuit 22, and outputs the first delayed signal delayed by 1 field - 0.5H to 1H.
By delaying, a second delayed signal obtained by delaying the input composite video signal by 1 field + 0.5H is applied to the terminal 26b of the switch circuit 26.

The horizontal transfer clock pulse φ _H from the horizontal transfer clock generation circuit 24 is applied to the switch circuit 26 as a switching signal through a pulse delay circuit 28. Here, assuming that the horizontal transfer clock pulse φ _H causes horizontal transfer to be performed during a high level period and suspends horizontal transfer during a low level period, the switch circuit 26 receives the horizontal transfer clock pulse φ H from the pulse delay circuit 28. Switching control is performed such that during the high level period of φ _H , the first delayed signal input to the terminal 26a is selected and output, and during the low level period of φ _H , the second delayed signal input to the terminal 26b is selected and output. As a result, as described above, the signal to be sampled from the switch circuit 26 is equivalently sampled at a frequency 2f _S that is twice the horizontal transfer clock frequency f _S , and is delayed by exactly one field. The signal is extracted and output to the output terminal 23 through a low-pass filter 29 for removing noise caused by switching of the switch circuit 26.

Here, as an example, the horizontal transfer clock frequency f _S
If you select 4.9484MHz (k in equation (1) is 314,
f _H is 15.73426kHz), by the sampling theorem
Signal components of f _S /2, that is, 2.4742 MHz or higher, are not directly output from this sampling system, but according to the present invention, the equivalent sampling frequency is
Since it is set to 2f _S , signal components up to 4.9484MHz are transmitted. Further, in the above case, a wide band signal of up to about 3 MHz can be transmitted through the low-pass filter 29 which constitutes the switch circuit means 21 together with the switch circuit 26 and the pulse delay circuit 28.

It should be noted that the pulse delay circuit 28 has delays caused by the horizontal transfer clock pulses φ _H and _H in the driver, the delay caused by the low-pass filter 25 for clock removal, etc.
Horizontal transfer clock pulse _φH and switch circuit 2
6 is provided to correct a transmission error between the sampled signal and the actual sampling point at the input terminal of the circuit 6, and has a known circuit configuration as shown in FIG. 4, for example. In FIG. 4, the horizontal transfer clock pulse φ _H that has entered the input terminal 31 is supplied to the base of the NPN transistor Q 1 via the DC blocking capacitor C ₁ and the resistor R ₁ , and is then supplied to the base of the NPN transistor _{Q 1} .
It is inverted amplified and taken out from the connection point between the emitter and the collector, while it is non-inverted amplified and taken out from the connection point between the emitter and the resistor _R5 . Resistors R ₂ and R ₃ are base bias resistors.

A signal in phase opposite to the input signal taken out from the collector of transistor Q ₁ is taken out through capacitor C ₂ , and is added and mixed with a signal in phase with the input signal taken out from the emitter of transistor Q ₁ through variable resistor VR ₁ . After that, resistor R ₆ , NPN transistor Q ₂ that constitutes the emitter follower, resistor R ₇
is supplied to the base of NPN transistor _Q3 . Transistor Q ₃ , resistor R ₈ , R ₉ , capacitor
The circuit section consisting of C ₃ and variable resistor VR ₂ receives a signal obtained by performing the same operation as the circuit section consisting of transistor Q ₁ , resistors R ₄ and R ₅ , capacitor C ₂ and variable resistor VR ₁ . is supplied to the base of NPN transistor Q ₄ via resistor R ₁₀ . transistor
The signal taken out from the connection point between the emitter of Q ₄ and resistor R ₁₁ is passed through a filter consisting of capacitor C ₄ and resistor R ₁₂ to inverters 32 and 33 and a resistor.
The signal is supplied to a waveform shaping circuit formed by R ₁₃ , where it is converted into a pulse train and then outputted from the output terminal 34 .

The variable resistors VR ₁ and VR ₂ are used to adjust the amount of phase shift caused by CR, and a desired delay time can be obtained by adjusting the amount of phase shift.

Next, a second embodiment of the apparatus of the present invention will be described. FIG. 5 shows a block system diagram of the main parts of the second embodiment of the apparatus of the present invention. In the figure, the same components as in FIG. 7 are given the same reference numerals. This embodiment is an example in which a digital memory is used as the field delay circuit means 20, and the delay circuit 22 and switch circuit means 21 are respectively the same as those shown in FIG. Fifth
In the figure, the composite video signal that has entered the input terminal 1 is supplied to the A/D converter 35, where the composite video signal (1) is phase-locked to the horizontal synchronization signal from the phase locked loop (PLL) 36. ) is digitally sampled based on a clock pulse with a repetition frequency f _S that satisfies the equation. The output digital signal of this A/D converter 35 is supplied to a random access memory (RAM) 37, where it is
After being written based on a clock pulse from PLL 36, it is read out with a one field delay.

The 1-field delayed digital signal read from the RAM 37 is supplied to the DA converter 38,
Here, the signal is digital-to-analog converted into a one-field delayed video signal, and then supplied to the delay circuit 22 and switch circuit means 21 via the output terminal 39, respectively. Note that the output clock pulse of the PLL 36 is outputted as a switching pulse of the switch circuit means 21 via the output terminal 40.

Next, an example of application of the device of the present invention will be explained. FIG. 6 shows a block system diagram in which the device of the present invention is applied to a noise reduction circuit for video signals. In Figure 6,
For example, a reproduced composite video signal that has been reproduced from a magnetic tape and then demodulated is supplied to subtraction circuits 42 and 44 via an input terminal 41, respectively. Subtraction circuit 42
The reproduced video signal extracted from the above is supplied to the video signal delay device 43 according to the present invention, where it is delayed for a period of 1 field - 0.5H, and then sent to the subtraction circuit 4.
4. The subtraction circuit 44 performs a subtraction operation of subtracting the output signal of the delay device 43 from the reproduced composite video signal from the input terminal 41, and supplies the obtained signal to the subtraction circuit 42 through the limiter 45. Here, while a video signal generally has so-called field correlation in which video information at one field interval is extremely close to each other, noise does not have such field correlation.

Therefore, the output signal of the subtraction circuit 44 is mainly noise without field correlation. The limiter 45 limits the amplitude of the signal mainly composed of noise to about the peak-to-peak level of the noise. The subtraction circuit 42 subtracts the output signal of the limiter 45 from the reproduced composite video signal from the input terminal 41, and removes noise in the reproduced composite video signal from the limiter 4.
The signal is substantially canceled out by the output signal No. 5 and outputted again to the video signal delay device 43, while being outputted to the output terminal 46.
In this way, the input reproduced composite video signal is extracted from the output terminal 46 with the noise therein reduced.

In a noise reduction circuit called a so-called cyclic field correlation noise reducer having a one-field delay circuit in such a feedback path, the video signal delay device 43 of the present invention, which is used as a one-field delay circuit, has the above-mentioned structure. Since it is possible to transmit a wideband video signal up to about 3 MHz, it is possible to sufficiently suppress noise in higher frequencies than in the past.

Effects of the Invention As described above, according to the present invention, since the clock pulse frequency is selected to be a predetermined frequency, the input composite video signal can be output after being delayed by one field over a wide band, and the circuit configuration can be made inexpensive. Furthermore, the video signal delayed by 1 field - 0.5H and the video signal delayed by 1 field + 0.5H are output alternately in accordance with the clock pulse, so that the required bandwidth can be effectively reduced. Moreover, even if a charge transfer element is used, a video signal equivalent to a delay time of exactly one field (262.5H or 312.5H) can be obtained, and the first and second delay signals can be obtained from the switch circuit means. Composite signals that are alternately synthesized in time series (i.e., predicted signals generated from sampled signals one field past)
is output, so it is possible to obtain a video signal equivalent to one field delay that allows field correlation that is not biased in a fixed direction on the screen, either up or down.
When used in a field delay circuit, it has the advantage of being able to sufficiently suppress noise in higher frequencies than conventional noise reducers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the device of the present invention, FIG. 2 is a diagram for explaining the operating principle of the device of the present invention, and FIG. 3 is a block diagram showing the first embodiment of the device of the present invention. FIG. 4 is a circuit diagram of an example of the main part of the block system shown in FIG. 3, FIG. 5 is a block system diagram showing the main part of the second embodiment of the device of the present invention, and FIG. FIG. 7 is a block diagram showing an example of a conventional device. FIG. 8 is an enlarged diagram of an example of the structure of a semiconductor delay circuit. FIG. 9 shows the main points of FIG. 7. 10 and 11 are signal waveform diagrams for explaining the operation of FIG. 7, respectively. 1, 41...Composite video signal input terminal, 2...Semiconductor delay circuit section, 3...Horizontal transfer register for input, 41 _to 4n...Vertical transfer register, 5...Horizontal transfer register for output, 6... Horizontal synchronization signal separation circuit, 7, 24...Horizontal transfer clock generation circuit,
8... Vertical transfer clock generation circuit, 9... Delayed video signal output terminal, 20... Field delay circuit means, 21... Switch circuit means, 22... Delay circuit, 23... Delayed video signal output terminal, 25... ... Low-pass filter for clock removal, 26 ... Switch circuit, 27 ... 1H delay circuit, 28 ... Pulse delay circuit, 35 ... A/D converter, 36 ... Phase locked loop (PLL), 37 ...Random access memory (RAM), 38...D/
A converter.

Claims (1)

[Claims] 1. A sampling frequency fs fs ≒ a frequency that is less than twice the upper limit frequency of an input composite video signal such as a luminance signal and higher than the upper limit frequency, and is expressed by the following formula: (2k+1)・(f _H /2) (where, in the above equation, k is a natural number and f _H is the horizontal scanning frequency of the input composite video signal). field delay circuit means for outputting a first delayed signal obtained by delaying the obtained sampled signal by a period equal to one field period minus 0.5 horizontal scanning period; and the first delayed signal obtained from the field delay circuit means. a delay circuit that outputs a second delayed signal obtained by delaying the delayed signal by one horizontal scanning period and delaying the sampled signal by a period of one field period plus 0.5 horizontal scanning period; 1. A video signal delay device comprising switch circuit means for alternately switching two delay circuits using the clock pulse and outputting a one-field delayed video signal. 2. The field delay circuit means includes an input horizontal transfer register to which the input composite video signal is serially supplied, and a plurality of columns of vertical transfer registers to transfer signals supplied in parallel from the input horizontal transfer register; a semiconductor delay circuit section comprising an output horizontal transfer register that holds signals supplied in parallel from the vertical transfer register and then horizontally transfers the signals to output delayed video signals in series; A horizontal transfer clock generation circuit generates a clock pulse for causing the horizontal transfer register to perform horizontal transfer and supplies it to both the input and output horizontal transfer registers, and a horizontal transfer clock generation circuit generates a clock pulse for causing the horizontal transfer register to perform horizontal transfer. Claim 1 comprising: a vertical transfer clock generating circuit that generates a clock during a period and supplies it to the vertical transfer register.
The video signal delay device described in . 3. The switch circuit means includes a pulse delay circuit for correcting a phase error between the first delay signal taken out from the field delay circuit means and the clock pulse, and a pulse delay circuit for correcting a phase error between the first delay signal taken out from the field delay circuit means and the clock pulse delayed by a certain period of time by the pulse delay circuit. 2. The video signal delay device according to claim 1, further comprising a switch circuit that is controlled to selectively output the first and second delayed signals alternately. 4. The field delay circuit means is supplied with the input composite video signal, and includes a clock pulse generation circuit that generates the clock pulse phase-synchronized with the horizontal synchronizing signal, and converts the input composite video signal from analog to digital based on the clock pulse. an A/D converter that outputs an output digital signal of the A/D converter, a memory circuit that delays and outputs an output digital signal of the A/D converter by a period of one field period minus 0.5 horizontal scanning period based on the clock pulse, and an output digital signal of the memory circuit. 2. The video signal delay device according to claim 1, further comprising a D/A converter that performs digital-to-analog conversion on a signal and outputs the signal as the first delayed signal.