JPH0337857B2 - - Google Patents

Description

[Detailed description of the invention]

[Summary] In a semiconductor LSI wiring method that requires multilayer wiring, the formation of an interlayer insulating layer is divided into two layers.
Chemical vapor deposition (CVD) for the underlayer with less damage to the substrate
A method is provided in which a conventional inorganic insulating layer is formed by a method, an insulating resin layer is applied thereon, and the resin layer is hardened and flattened by plasma heat treatment. As a result, a smooth resin layer without cracks can be obtained, and a flattened interlayer insulating layer that can be made finer can be formed. [Industrial Application Field] The present invention relates to a multilayer wiring method for semiconductor devices. In recent years, the wiring layers of compound semiconductor LSIs and other devices have been multilayered to address the need for greater integration, multifunctionality, and higher performance of devices. In addition to fixed wiring, multilayer wiring may include, for example, a gate array in which functions are selected in the uppermost layer wiring to form a desired device. [Prior Art] FIGS. 1 to 5 are cross-sectional views illustrating a conventional multilayer wiring method. In FIG. 2, an element formation layer 2 is grown on a substrate 1, an element isolation region 3 made of an insulating layer is formed to define an element formation region, and a field effect transistor (FET) is formed in the element formation region. G,S,
D are the gate, source, and drain electrodes of the FET, respectively. 4 is an alloy layer of an electrode metal and a semiconductor formed under the source and drain electrodes. Next, a first wiring layer 5 is formed on the element isolation region 3.
form. 2 In FIG. 2, an interlayer insulating layer 6 is formed on the substrate, covering the first wiring layer 5, using the CVD method. In FIG. 2, a contact hole is opened in the interlayer insulating layer 6 using normal lithography. In FIG. 2, a second wiring layer 7 is deposited on the entire surface of the substrate on the interlayer insulating layer 6, covering the contact hole. In FIG. 2, the second wiring layer 7 is patterned using normal lithography. In the multilayer wiring method as described above, the interlayer insulating layer 6
This causes unevenness, which impairs the accuracy of lithography in subsequent processes. Another disadvantage is that it is difficult to remove the metal (second layer wiring 7) adhered to the recess (portion A in the figure) by ion milling during patterning. In other words, when conventional multilayer wiring technology connects upper and lower wiring layers, disconnections occur around the periphery of contact holes made in the interlayer insulating layer, disconnections in the upper wiring layer due to irregularities in the interlayer insulating layer, or disconnections between the upper and lower wiring layers. Short circuits and the like occur, and in order to prevent these, it is necessary to planarize the interlayer insulating layer. For this reason, film formation techniques with good step coverage have been developed, but damage to the elements may become a problem. DC bias sputtering and flattening by resin coating have been attempted as film formation techniques that provide good step coverage. [Problems to be solved by the invention] As a conventional method for planarizing the interlayer insulation layer of a multilayer wiring structure, the DC bias sputtering method applies a reverse bias during film formation, which causes protrusions of the deposited film to become flat. The entire surface of the substrate is flattened by sputter etching. In this case, some ion damage occurs to the substrate, and this damage cannot be sufficiently annealed out if there is no high-temperature process, such as in the process of compound semiconductor devices. Furthermore, in the resin coating method, if a sufficient thickness is applied to flatten the substrate surface, cracks are likely to occur during thermal curing of the resin, so the coating is done in several parts. Even with this method, as the resin layer becomes thicker, cracks tend to occur as the resin hardens, and the method of curing the resin is extremely difficult. [Means for solving the problem] The above problem can be solved by: (1) forming a wiring layer on a substrate, forming an insulating layer on the substrate to cover the wiring layer; A step of coating an insulating resin layer on the substrate to make the surface of the substrate substantially flat, a step of placing the substrate in plasma and etching back the insulating resin layer, and then heating the substrate. or (2) the multilayer wiring method according to item (1) above, wherein the insulating resin layer is a resin containing silicon. In the wiring method, or (3) the etching back step and the curing and reflowing step, the substrate is placed in a plasma of carbon tetrafluoride and oxygen at room temperature, the insulating resin layer is etched back, and the substrate is then etched back. The insulating resin layer is cured in plasma of carbon tetrafluoride and nitrogen while the temperature is raised, and then the substrate is held at high temperature in nitrogen plasma to harden the surface at the same time as reflow of the insulating resin layer. This is achieved by the multilayer wiring method described in (1) above, which includes a continuous process of cooling the substrate in vacuum. [Function] In the present invention, the interlayer insulating layer is divided into two layers, an insulating layer is deposited on the base layer by a CVD method or the like that causes less damage to the substrate, an insulating resin layer is applied on top of the insulating layer, and the insulating resin layer is approximately flattened. Film thickness control etchback using carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) at room temperature, addition of nitrogen (N ₂ ) to CF ₄ and O ₂ when the substrate temperature is raised, and heating reflow using N ₂ plasma when the substrate temperature is high. and
It forms a smooth flat surface. The above process controls the film thickness by etching back from the resin surface by changing the atmospheric gas and plasma ion species during one step, and then hardens the resin surface to be reflowed by heating the substrate with _N2 plasma. As a result, the resin surface becomes extremely smooth and glass-like, and the occurrence of cracks can be prevented. [Example] FIGS. 1 to 6 are cross-sectional views illustrating a multilayer wiring method according to the present invention. 1. In FIG. 1, an element formation layer 2 is grown on a substrate 1, an element isolation region 3 made of an insulating layer is formed to define an element formation region, and an FET is formed in the element formation region.
form. G, S, and D are the gate, source, and drain electrodes of the FET, respectively. The element isolation region 3 is formed by implanting oxygen ions (0 ⁺ ). 4 is an alloy layer of an electrode metal and a semiconductor formed under the source and drain electrodes. Next, a first wiring layer 5 is formed on the element isolation region 3.
form. In FIG. 1, a silicon oxynitride (silicon oxynitride, SiON) layer is formed as an insulating layer 6A as a base layer of an interlayer insulating layer on the substrate, covering the first wiring layer 5, using the CVD method. do. Furthermore, silicone resin, for example PMSS resin, is applied thereon as an insulating resin layer 6B to a thickness that substantially flattens the substrate. Next, plasma heat treatment, which will be described later in FIG. 3, is performed to control the thickness of the insulating resin layer 6B and flatten the surface. In FIG. 1, contact holes are formed in interlayer insulating layers 6A and 6B by etching using a resist pattern 8 as a mask using ordinary lithography. In FIG. 1, a contact hole is filled and a conductive layer 9 for connection is formed on a resist pattern 8 using, for example, titanium-platinum-gold (Ti-Pt-Au).
A layer is deposited over the entire substrate. Next, the conductive layer 9 on the resist pattern 8 is lifted off. In Figure 1, 5, as an insulating layer on the entire surface of the substrate.
A SiON layer 10 is deposited. In FIG. 1, a contact hole is opened in the SiON layer 10 to expose the conductive layer 9 using the same lift-off method, and a wiring layer 7 is formed as the second layer. In the multilayer wiring method as described above, the interlayer insulating layer is planarized, and the accuracy of lithography in the subsequent process is improved. Next, plasma heat treatment of the insulating resin layer will be explained. FIG. 3 is a diagram showing the relationship between substrate temperature and elapsed time for each process of plasma heat treatment. In the figure, each series of plasma heat treatment processes is as follows.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to flatten a board with a multilayer wiring structure without damaging the board, and to prevent cracks in the interlayer insulating resin layer.

[Brief explanation of drawings]

1 to 6 are cross-sectional views explaining a multilayer wiring method according to the present invention, FIGS. 2 1 to 5 are cross-sectional views explaining a conventional multilayer wiring method, and FIG. 3 is a substrate for each process of plasma heat treatment. Figure 4 is a diagram showing the relationship between temperature and elapsed time. Figure 4 shows the configuration of the plasma etching equipment. Figure 5 shows how to apply a PMSS resin layer and contact this layer when forming a conductive layer for connection in two stages. FIG. 3 is a cross-sectional view showing a state in which a hole is opened. In the figure, 1 is a substrate, 2 is an element formation layer, 3 is an element isolation region, 4 is an alloy layer, 5 is a first wiring layer, 6 is an interlayer insulating layer, 6A is an underlying insulating layer, 6B
7 is the insulating resin layer, PMSS resin layer, 7 is the second wiring layer, 8 is the resist pattern, and 9 is the conductive layer for connection.
The Ti-Pt-Au layer, 10 is an insulating layer and is a SiON layer.

Claims (1)

[Claims] 1. A step of forming a wiring layer on a substrate, and forming an insulating layer on the substrate to cover the wiring layer, and coating an insulating resin on the insulating layer to substantially cover the surface of the substrate. A step of depositing a flattened insulating resin layer, a step of placing the substrate in plasma and etching back the insulating resin layer, and then raising the temperature of the substrate to harden and reflow the insulating resin layer in the plasma. A multilayer wiring method characterized by comprising the steps of: 2. The multilayer wiring method according to claim 1, wherein the insulating resin layer is a resin containing silicon. 3. The etching back step and the curing and reflowing step include etching back the insulating resin layer by placing the substrate in a plasma of carbon tetrafluoride and oxygen at room temperature, and then raising the temperature of the substrate. The insulating resin layer is cured in carbon tetrafluoride, oxygen, and nitrogen plasma, and then the substrate is held at high temperature in nitrogen plasma to reflow and simultaneously harden the surface of the insulating resin layer. Then, the substrate is cured in a plasma of carbon tetrafluoride, oxygen, and nitrogen. 2. The multilayer interconnection method according to claim 1, further comprising a continuous process of cooling the substrate in vacuum.