JPH0338668B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase servo circuit, and is particularly suitable for application to a drum phase servo of a video signal recording and reproducing device equipped with an automatic editing function.

In helical scanning VTRs such as 2-head VTRs, 1-head VTRs, and 1.5-head VTRs with auxiliary heads, in order to record by inserting or connecting another video signal to a recorded magnetic tape or a partially recorded magnetic tape, Requires automatic editing functionality. Conventionally, the arrangement of control signals on the tape and the phase of the synchronization signal on the video track are matched before and after the editing point to prevent the screen from being distorted at the editing point during playback.

Editing methods include "assembly" shown by the track pattern on tape 1 in FIG. 1a and "insert" shown in FIG. 1b. In the assemble mode, after the recording of one cut is completed, the signals of the next cut are connected and recorded. In this mode, the full erase head operates, erasing all previously recorded signals after the edit point, including the control signal (CTL signal).
Record the video signal while writing the CTL signal.
If the full erase head suddenly operates at this time, the necessary portion of the recorded signal A will be erased, so the flying erase head is operated for a predetermined period of time as shown by the dotted line in Figure 1a. The full erase head is operated from the position P where the erased part no longer covers the full erase head.

In insert mode, the B signal is inserted into the recorded A signal. In this mode, Figure 1b
As shown in the figure, the flying erase head records the B signal (dotted chain line) while erasing the A signal (solid line), but does not erase the CTL signal.

In these assemble modes and insert modes, until the editing point is reached, the head drum servo of the editing machine is locked using the vertical synchronization signal of the B signal, and while the A signal is being played back, the PG pulse of the drum and the playback CTL signal are synchronized. It also controls the tracking servo (capstan servo) of the editing machine. Therefore, the phase alignment between the vertical synchronization signal of the newly recorded B signal and the CTL signal of the editing machine has been completed before the editing point is reached. After the editing point, when in the assemble mode, the editing machine switches to a recording mode for recording the B signal, and at this time, the capstan servo is usually only constant-speed servo. On the other hand, in the insert mode, only the head drum system is switched to the recording mode, and the capstan servo operates with the reproduction servo (tracking servo) applied even with the CTL signal of the recorded A signal.

By doing this, the arrangement of CTL signals and the phase of the synchronization signal on the video track are matched before and after the editing point, but the compatibility between the playback device and editing device for obtaining the B signal is If you are not satisfied with the completion, or if the drive system changes over time, they may not match completely. That is, the second
As shown in Figure a, if there is a phase shift ΔV between the vertical synchronization signal V of the newly recorded video signal B and the vertical synchronization signal V of the already recorded video signal A, the editing point The reproduced image shifts vertically between the front and back, making it difficult to see. Further, as shown in FIG. 2B, if there is a phase shift ΔH in the horizontal synchronizing signal H of the video signals A and B, the horizontal oscillation of the monitor device is disturbed at the editing point, causing so-called H jump in the flow of the image.

The present invention has been made in view of the above-mentioned problems, and it is possible to record (insert or assemble) a video track by aligning the synchronization signal of the recorded portion on the video track with the synchronization signal of the newly recorded video signal. ).

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows a drum servo system of a VTR to which the present invention is applied. As shown in FIG. 3, magnetic heads 3A and 3B attached to a rotating drum are rotationally driven by a drum motor, and a magnetic tape 1 is rotated by a drum motor.
A track at a predetermined angle is formed on the track to record/play back the video signal. A frequency generator 4 is attached to the rotating shaft of the drum motor 2, and its output is supplied to a speed servo circuit 5, where a reference signal is generated.
A speed error signal is formed based on REF. The speed error signal is supplied to a drive amplifier 7 through an adder 6, and the speed of the drum motor 2 is also controlled by the output of the amplifier 7.

The rotational phases of the magnetic heads 3A and 3B are detected by a PG head 8, and the output PG signal is supplied to a phase servo circuit 9. The phase servo circuit 9 is supplied with a vertical synchronizing signal REC-VD during recording, and an external reference signal X-VD or a reproduced CTL signal during reproduction. Further, during tape editing such as insert mode or assemble mode, the vertical synchronization signal REC-VD of the video signal to be recorded is supplied to the phase servo circuit 9 for phase matching with the recorded signal. The phase error signal obtained from the phase servo circuit 9 is added to the speed error signal in an adder 6, and then supplied to the drum motor 2 via a drive amplifier 7.

FIG. 4 shows a circuit diagram of the phase servo circuit 9 of FIG. 3 to which the present invention is applied. FIG. 5 is a time chart showing the target to be achieved by this servo circuit, and FIGS. 6 to 9 are waveform diagrams of each part of FIG. 4. As shown in Fig. 5, the output PG of the PG head 8
(Fig. 5 a) and a predetermined reference signal REF (Fig. 5 b)
The purpose of the phase servo circuit 9 is to maintain a predetermined phase difference φ. This reference signal may be a vertical synchronization signal of a recorded video signal during recording, and may be an external reference synchronization signal, a reproduction vertical synchronization signal, or the like during reproduction.

In FIG. 4, the phase difference detection circuit 10 is shown surrounded by a dotted line, and the other part is an editing phase correction circuit 11 for correcting the recording phase during tape editing. The phase difference detection circuit 10 detects the phase difference between the PG signal shown in FIG. 5 and the reference signal REF by counting it using clock pulses of a predetermined frequency, and generates a position modulation pulse of a predetermined period according to the counting result. I'm trying to get it. The monomulti 13 in Fig. 4 contains 30
A PG pulse PGH (FIG. 6a) of Hz is supplied, and a signal PGHDL having a predetermined pulse width shown in FIG. 6B is obtained from the output of the monomulti 13. This signal sets flip-flop FF14. on the other hand,
When the phase servo circuit in Figure 4 operates in recording mode, the vertical synchronization signal of the video signal to be recorded
REC-VD (FIG. 6c) is supplied to the delay counter 15 as a reference signal REF. Since the counter 15 counts a predetermined number of clock pulses TF6 of a predetermined frequency from the clock circuit 16, a signal VDL (FIG. 6d) delayed by a fixed amount is obtained from its output. The FF 14 is reset by this signal VDL.

From the Q output of FF14, the signal shown in Figure 6e is generated.
DPEB is obtained. The pulse width of this signal is PG
It represents the phase difference between the pulse PGH and the recording vertical synchronization signal. Note that the delay counter 15 is provided to simplify the counting operation and configuration of a phase detection counter, which will be described later. The output of FF14 is supplied as a strobe signal to AND gate G1, and during its high level period, clock pulse TF6 passes through gate G1. The output of AND gate G1 is supplied to clock terminal CK of phase detection counter 17 through OR gate G2.
The phase detection counter 17 may be, for example, in 512 base, and the phase difference between the drum rotation phase and the recording synchronization signal φ
When the pulse width of the signal DPEB that represents It is starting to rise. Therefore, the phase detection counter 17 accumulates a count value corresponding to the phase difference φ.

Note that when the PG pulse is delayed as shown by the dotted line in Figure 6a, the count value of the counter 17 is 256-
x (x: variable), and its MSB output is shown in Figure 6.
As shown in f′, it remains at a low level at the end of counting. Further, when the PG pulse advances as shown by the dashed line in Figure 6a, the count value of the counter 17 is 256 + x, and the MSB output is as shown in Figure 6.
As shown in f'', the count value rises to 256 and is in a state where x is counted further.

The phase information measured by the counter 17 is read out as follows, and the buffer counter 18
will be forwarded to. That is, the output DPEB of FF14 is supplied to the set input of flip-flop FF19,
At the falling edge, FF19 is set as shown in FIG. 6g. The Q output of FF19 is a flip-flop
Since it is supplied to the set input of FF20, this FF
The FF 20 is set as shown in FIG. 6i at the timing of the clock TF12 (FIG. 6h) supplied to the FF 20. Q output D-TRS of FF20 is FF2
0 and the reset input of FF19, FF19 is reset, and one clock later, FF20 is reset as shown in FIG. 6i. Therefore, a signal D-TRS having a pulse width of one cycle of TF12 is obtained from FF20.

The clock TF12 is formed by the clock circuit 16, and one cycle thereof, ie, the period in which the signal D-TRS is at a high level, corresponds to the length of 512 clock pulses TF6. Since the output D-TRS (data transfer pulse) of the FF 20 is supplied as a strobe pulse to the AND gate G3, the clock pulse CP from the clock circuit 16 is supplied to the clock terminal of the phase detection counter 17 through the gates G3 and G2. . As a result, the counter 17 starts counting again as indicated by the thick line in FIG. 6f, and the count value increases based on the stored count value (phase information). Therefore, the most significant bit output of counter 17
DPC falls at a count value of 512 as shown in FIG. 6f. The position of this fall is determined according to the previously measured phase information as shown in Fig. It is obtained by position modulating the falling position of the output of No. 17.

The output of counter 17 is supplied to the reset input of buffer counter 18 through AND gate G4. The counter 18 is a 512-decimal counter and counts the clock pulses CP from the clock circuit 16. Therefore, the most significant bit output BC becomes a pulse signal with a predetermined period, which becomes a high level at a count value of 256 and returns to a low level at a count value of 512, as shown in FIG. 6J. When the buffer counter 18 is reset by the output of the counter 17, the cyclic phase of the counter 18 is changed according to the phase information of the phase detection counter 17, as shown in FIG. 6j, and this cyclic phase remains unchanged until the next reset. is retained. That is, the position information of the falling edge of the output of the counter 17 (f, f', f'' in FIG. 6) is transferred to the counter 18 as shown in j, j', j'' of FIG. 6.

The output BC of counter 18 is flip-flop FF
23 set input, so this output
At the falling edge of BC, FF23 is set as shown in FIG. 6k. When the phase servo system shown in FIG. 4 operates in the normal recording mode, the reset input of the FF 23 is supplied with a reference timing signal, for example, the clock pulse TF12 shown in FIG. 6h. Therefore,
From the output of the FF 23, a signal DPPWM (k, k', k'' in Fig. 6) whose pulse width is modulated according to the phase difference φ between the PG pulse PGH and the recording synchronization signal REC-VD is obtained. TF12 can be obtained from a phase difference correction PEC counter 20, which will be described later.That is, by resetting the counter 20 with a predetermined timing signal when switching to the recording mode, a predetermined phase and a value can be obtained from the output of the counter 20. A periodic timing signal TF12 is obtained.

After the pulse width modulation signal is inverted, it is converted to an analog level through a low-pass filter and added to the output of the speed servo circuit 5 in an adder 6 in FIG. Therefore, when the PG pulse is delayed as indicated by the dotted line in FIG. The output phase error voltage increases and the speed of the drum motor 2 is increased. Also, on the contrary, the PG pulse is the 6th pulse.
When progressing as indicated by the dashed line in FIG. 1A, the effective pulse width of the pulse width modulation signal becomes shorter, and as a result, the motor 2 is decelerated.

In this way, the phase of the PG pulse PG with respect to the recording vertical synchronizing signal REC-VD, ie, the rotational phase of the head, is fixed at the set value φ. This fixes the track on the tape on which the video signal is recorded in the correct position. Also, during playback, for example, if the tracking servo is performed by a capstan,
As a reference signal for drum phase servo, an external vertical synchronizing signal X-VD obtained from a reference frequency source (for example, the clock circuit 16 in FIG. 4) is supplied as a reference signal REF to the phase difference detection circuit 10, and as in the case of recording, As shown in FIGS. 5a and 5b, the phase servo circuit 9 operates so that the PG pulse and the reference signal REF are fixed at a predetermined phase difference.

Next, the editing mode will be explained. In the editing mode, the recording vertical synchronizing signal REC-VD is supplied to the phase difference detection circuit 10 in FIG. 4, as in the recording mode, and the drum servo system operates in the recording mode. Before entering the editing point, the vertical synchronization signal REC-VD of the recording video signal B and the reproduction vertical synchronization signal of the already recorded video signal (signal A in Figure 1) are input.
A phase error with PB-VD is detected, and the rotational phase of the rotary head is changed so that this phase error becomes zero. That is, as shown in Fig. 5 a and c,
The phase difference between REC−VD and PG pulse is fixed value φ
is changed by Δφ from REC−VD.
and PB-VD (FIG. 5d). This phasing is accomplished by adjusting the reset signal of flip-flop 23 of FIG.

Next, the configuration and operation of the editing phase correction circuit 11 shown in FIG. 4 will be explained with reference to the waveform diagrams shown in FIGS. 7 to 9.

In Figure 4, the phase difference correction counter (PEC
The counter 24 is, for example, a 10-bit counter that counts clock pulses of a predetermined frequency. The output of this counter 24 has the same period as the output of the buffer counter 18 (FIG. 6j) that stores phase servo information in the form of its cyclic phase.
PEC (Figure 6l) is obtained. This output is used by FF2 to form a pulse width modulation signal (DPPWM).
Since it is supplied to the reset terminal of FF23 through the gate circuit, the reset timing of FF23 is PEC.
It is changed according to the cyclic phase of the counter 24.
The circulation phase of the PEC counter 24 is equal to REC−VD.
It is changed by adjusting the number of supplied clocks according to the phase difference with PB-VD.

As shown in FIG. 7, from the vertical synchronization signal REC-VD (FIG. 7a) of the recording video signal B, a certain period t
A delayed signal REC-VD' (FIG. 7b) is formed. Also, the vertical synchronization signal of the playback video signal A
From PB-VD (FIG. 7d), a signal PB-VD' (FIG. 7e) is formed which is delayed by the same time t as above. The phase correction circuit operates so that the phases of these signals REC-VD' and PB-VD' match.

Signal REC-VD' is applied to the clear input of flip-flop FF25. Further, since a predetermined timing signal CG2 is supplied to the trigger input of the FF 25, a signal WID of a predetermined pulse width (low level) shown in FIG. 7c is obtained from the output of the FF 25. This signal WID is a signal for detecting coincidence with PB-VD of reproduction, and has a predetermined width D (dead zone).
to prevent hunting from occurring during match detection. The coincidence detection signal WID is supplied to the data input of flip-flop FF26. In addition, the sample pulse DLPBVD (7th
FIG. f) is formed and fed to the clock input of FF 26. Therefore, the level of the coincidence detection signal at the rising position of the sampling pulse is FF2.
6.

If the rising edge of the sample pulse is within the pulse width D of the coincidence detection signal as shown in FIG. 7f, FF2
6 is reset, its output MODFY is “0”
It is. Furthermore, if PB-VD' is in phase leading or lagging behind REC-VD', the rising edge of the sample pulse will be outside the detection range of the coincidence detection signal as shown in Figure 7 f' and f'', and FF26 will be set. Therefore, the output MODFY becomes “1”. Correction command signal
MODFY=1 indicates that phase correction is required.

Sample pulse DLPBVD is flip-flop
It is also supplied to the clock input of FF27. This FF
The data input D of 27 is supplied with a signal VG12 which goes high before the signal REC-VD' (FIG. 7b) as shown in FIG. 7g and goes low afterward. Therefore, FF27 is set or reset according to the level of VG12 at the timing of the rise of DLPBVD, and the PB for PEC-VD' is determined from its Q output.
A signal that determines the direction of phase lead or lag of −VD′
You can get DIRE. When the sample pulse is in an advanced phase as shown in Fig. 7 f', the correction direction indication signal DIRE becomes "1", and in this case, the
Phase correction is performed in the direction indicated by the arrow f'. Further, when the sample pulse has a delayed phase as shown in FIG. 7f'', the signal DIRE becomes "0", and in this case, phase correction is performed in the direction of the arrow in FIG. 7f''.

In order to prevent the phase correction time from becoming long, the step width of one correction amount is changed in two steps, one in the vicinity of the coincidence detection width and one outside it. Therefore, the correction command signal MODFY output from FF26 is supplied to the flip-flop FF28, and the number of times the sample pulse DLPBVD passes through the coincidence detection width D is FF28.
It is counted by. The output of the FF 28 is supplied to the set input of the flip-flop 29 via the differentiating circuit 30, so it is reset when the power is turned on.
In FF29, when the number of passes does not reach 2,
Remains in reset state. Therefore, AND gate G5 is opened by the output "1" of FF29,
A relatively low frequency (long period) clock pulse CP3 (FIG. 8a) passes through the gate G5 and further passes through the OR gate G7 to the pulse number control circuit 31.
supplied to As a result, for REC−VD
The phase of PB-VD is changed in large steps as shown in FIG.

Next, when the coincidence detection band (shaded area) in FIG. As a result, FF29 is set, and its Q output "1" opens AND gate G6, and clock pulse CP2 (FIG. 9a) with a frequency four times that of CP3 is applied to gates G6 and G7.
It is supplied to the pulse control circuit 31 through. As a result, as shown in FIG. 10, the phase of PB-VD is corrected by a step width of 1/4.

In addition, the output of the PEC counter 24 for phase difference correction
The period of PEC (Figure 6l) is equal to clock pulse CP6.
When CP3 is selected, FF2 is
Open the AND gate G8 even at the output of 9,
Select output PEC8 of PEC counter 24, and
When CP2 is selected, the AND gate G9 is opened using the Q output of the FF29 to select the output PEC10 of the counter 24 which is two bits higher. The number of times the coincidence detection zone in Figure 10 passes is:
Corrected direction indication signal obtained from the output of FF27
The number of inversions of DIRE, that is, the number of turns in FIG. 10 may be counted. Furthermore, regions with a constant pulse width are provided on both sides of the coincidence detection width D shown in FIG. It's okay.

Clock pulse obtained from gate G7
PECCP (CP3 or CP2) is supplied to the clock terminal of a D-type flip-flop FF32. The data input of this FF32 is connected to the data transfer signal D-TRS shown in FIG. 6i (FIG. 8b and FIG. 9b).
is supplied, so the signal D is output from the output of FF32.
- A signal delayed by one clock of TRS is obtained with opposite polarity. The output of FF32 and signal D-TRS are supplied to AND gate G10, so gate G1
Pulse for one clock period from the output of 0
ONECLK (FIGS. 8c and 9c) is formed. This pulse is supplied to the AND gate G11 of the pulse number control circuit 31. The one-clock pulse is generated every time the signal D-TRS is generated, that is, once every rotation of the head drum.

The gate G11 receives a correction direction instruction signal DIRE, a correction command signal MODFY, and a clock pulse CP.
3 or CP2 doubled by a frequency multiplier 33 (FIGS. 8d and 9d). Therefore, when the phase of the sample pulse DLPBVD is at the position shown in FIG.
Since the correction direction instruction signal DIRE output from the multiplier 33 becomes "1", two clock pulses (Fig. 8 d) from the output of the multiplier 33 enter the gate G11 during the period of the one clock pulse ONECLK (Fig. 8 c). It passes through and is supplied to the OR gate G12. Furthermore, since the one-clock pulse is inverted by the inverter 34 and supplied to the AND gate G14 via the OR gate G13, in sections other than the one-clock pulse,
Clock pulse CP3 is supplied to OR gate G12 through gate G14.

As a result, the clock pulse shown in FIG. 8e is obtained from the output of OR gate G12, and this clock pulse is supplied to the clock input of PEC counter 24. Therefore, since the counter 24 counts one extra clock pulse at a rate of one clock pulse per one revolution of the head drum, the phase of the output PEC8 of the counter 24 becomes equal to the time width of one clock pulse as shown in FIG. Only earlier. Since the output PEC8 is supplied to the reset input of the FF23 as a phase adjustment pulse PEC-OUT through the AND gate G8 and the OR gate G15, the effective pulse width of the pulse width modulation signal DPPWM output from the FF23 is expanded.
The supply voltage of the drum motor 2 increases. For this reason
The PG pulse advances in phase. That is, using the PG pulse as a reference, the sample pulse DLPBVD generated from the reproduced signal is moved in the direction of the arrow from the state shown in FIG. 7 f'. As a result, the phase of DLPBVD changes as shown in P1, P2, . . . in FIG. 10 every rotation of the drum.

When the sample pulse passes through the coincidence detection band as shown in Fig. 10 and reaches the position P4 (corresponding to the phase f'' in Fig. 7), the correction direction indication signal of the output of FF27
DIRE becomes "0" and gate G11 is closed. Therefore, only the inverted signal of the one clock pulse is supplied from the inverter 34 to the gate G14 through the gate G13, so that the clock pulse that has missed only one clock from the gate G14 as shown in FIG. The PEC counter 24 is supplied to the PEC counter 24 through the PEC counter 24. For this reason, the phase of the output PEC8 of the counter 24 is delayed by the time width of one clock pulse as shown in FIG. As the supply voltage decreases, the DG pulse becomes delayed in phase, i.e., with respect to the PG pulse, the sample pulse DLPBVD
is changed from the state shown in FIG. 7 f'' in the direction of the arrow.

When the phase of the sample pulse passes through the coincidence detection band and becomes as shown at P5 in Fig. 10, the correction direction indication signal is generated.
DIRE is inverted to "1", and since the sample pulse has passed through the coincidence detection band twice, the clock pulse is switched to the clock pulse CP2 having four times the frequency. Therefore, as described above, the clock pulse e in FIG.
The sample pulses are supplied to the counter 24, and the phases of the sample pulses are adjusted as shown in FIG. 10, P5, P6, P7, . . . . Note that the phase of the sample pulse may be changed in small steps from the position of P4 in the direction of the coincidence detection band.
The counter 24 counts the clock pulses shown in FIG. 9(f) in which the number of CP2 is decreased by one per rotation of the drum, as described above.

When the rising edge of the sample pulse DLPBVD falls within the coincidence detection width D as shown in FIG. 7f, the correction command signal MODFY output from the FF 26 becomes "0". FF
Since the output of 26 is supplied to the OR gate G13 of the clock number control circuit 31, after a match is detected, continuous clock pulses CP2 are supplied to the PEC counter 24 through gates G14 and G12. Therefore, the output PEC10 of the counter 24
The phase of is held constant.

In this way, the recording vertical synchronization signal REC−VD
(Figure 5c) and reproduced vertical synchronization signal PB-VD (Figure 5c)
Figure d) matches the pulse width modulated signal.
The position of the DPPWM reset point R (falling point) is
For example, it is changed as shown by the dotted line in FIG. 5e. As a result, a bias amount Δφ is added to the set phase difference φ between the PG pulse (FIG. 5a) and REC-VD.
Note that when a change in pulse width occurs in the pulse width modulation signal DPPWM, the phase difference detection circuit 10 in FIG.
However, since the set point S of the pulse width modulation signal is returned to the original pulse width as shown by the dashed line in Fig. 5e, when the servo system is in a stable state, the PG
The phase difference between the pulse and PEC-VD is maintained at φ+Δφ.

In addition, when adjusting the editing phase, it is necessary to maintain the adjustment range of the reset point R of the pulse width modulation signal within a predetermined range. This means that if the adjustment range is unlimited, for example, point R in Figure 5e approaches point S,
This is because the S point may be exceeded. In this case, the phase servo system is disturbed and the head phase rotates by one rotation for editing phase adjustment, which is extremely undesirable. For this reason, the phase adjustment is performed only in the region defined by the dashed-dotted lines in FIG. 6l-l''.

In FIG. 4, the phase adjustment pulse PEC-OUT obtained from OR gate G15 is supplied to each clock input of D-type flip-flops FF37 and FF38. Further, in the clock circuit 16, timing pulses T1 and T2 shown in FIG. 6 m and n are generated. These pulses T1, T2 and their inverted signals 1, 2 are supplied to gates G16, G17, and the outputs of these gates are FF37, FF37, respectively.
38 D input. Therefore, when the FF 37 samples the range indicated by the solid line J in FIG. Therefore, the output DIRE of the FF 27 becomes "1" and the direction of change of the phase adjustment pulse PEC-OUT is reversed to the left direction of the arrow in FIG. 6n.

Similarly, when the FF 38 samples the range indicated by the solid line K in FIG. Therefore, the direction of change of the phase adjustment pulse is reversed to the right direction of the arrow in FIG. 6n.

In this way, in the assemble mode of editing,
Until the assembling point is reached, the editing machine operates in the playback mode, and tracking servo is performed by the capstan, during which phase alignment between the recording signal and the playback signal is performed as described above. After the assembly point, aligned phases are maintained and the editor is switched to recording mode. In the insert mode, tracking servo is performed in the playback mode as described above until the insertion point is reached, and phase matching is performed during this time. After the insert point, tracking servo using the reproduced CTL signal continues, but since the reproduced vertical synchronization signal is no longer obtained, the editing phase correction circuit 11 maintains the phase. In the editing machine, only the magnetic head system is switched to recording mode.

Note that when switching to normal recording mode after operating in edit mode, the PEC counter 20
Clear the phase correction information held in
It is necessary to cancel the phase correction amount of Δφ given between the PG pulse and PEC-VD.

Next, FIG. 11 is a partial block diagram showing another embodiment of the present invention, and FIG. 12 is a waveform diagram of FIG. 11. In FIG. 11, the same parts as in FIG. 4 are given the same reference numbers, and common circuit parts are omitted.

In this embodiment, the fixed delay amount (FIG. 6b) by the monomulti 13 in FIG. 4 is set to REC-VD and PB-
The control is performed according to the phase difference with VD, thereby adding a correction amount of Δφ to the set phase difference φ between the PG pulse and REC-VD as shown in FIG. In Figure 11, the PG pulse (Figure 12a)
is supplied to a monomulti 39 for timing adjustment, and the delayed signal shown in FIG. 12b is obtained from its output. The output of the monomulti 39 passes through a differentiating circuit 40 and sets a flip-flop 41, so that
The Q output of FF41 rises as shown in FIG. 12c.
Since the output of FF41 is supplied as a strobe pulse to AND gate G18, the clock pulse PECCP output from gate G7 in FIG. 4 is supplied to clock number control circuit 31 similar to that in FIG. 4 through gate G18.

Since the clock number control circuit 31 is supplied with the correction direction instruction signal DIRE and the correction command signal MODFY, which are formed in the same manner as shown in FIG. The clock pulses whose number has been adjusted are controlled by the control circuit 3.
Obtained from 1. This clock pulse is supplied to the PEC counter 24, so the PEC counter 2
4 performs a counting operation as shown in FIG. 12d, and after counting a predetermined number of clocks, the output PEC10
Alternatively, PEC8 falls as shown in FIG. 12d.

Output PEC10 or PEC8 is gate G8, G
9, selected by G15 and supplied to the reset input of FF4. Therefore, the Q output of FF4 is the first
The signal falls as shown in FIG. 2c, thereby setting the FF 14 as shown in FIG. Since the FF 14 is reset by the recording vertical synchronizing signal REC-VD (FIG. 12f), the signal DPEB shown in FIG. 12E is obtained from the Q output of the FF 14. The pulse width of this signal corresponds to the phase difference between the PG pulse and REC-VD as in FIG. 6e, and phase difference information can be obtained by measuring this pulse width. This phase difference information allows the phase difference between the PG pulse and REC−VD to be
Fixed.

Similar to the embodiment shown in FIG. 4, REC-VD and PB-
The number of clocks supplied to the PEC counter 24 is 1 per drum rotation so that the phase difference with VD is zero.
only the clock is increased or decreased, thereby
The rise of the Q output of the FF 14 is gradually changed as indicated by the arrow in FIG. 12e. As a result, the PG pulse and
A bias amount Δφ is added to the phase difference φ with REC-VD, and thereby the phase difference between REC-VD and PB-VD becomes zero.

As described above, the present invention provides rotating magnetic heads 3A and 3B that sequentially form inclined tracks on a magnetic tape 1.
, a motor 2 that drives the rotating magnetic heads 3A and 3B, and a rotation detection register (frequency generator 4) that detects the rotational phase of the motor 2 and outputs a phase pulse FG.
and a video signal recording and reproducing circuit that supplies video signals to the rotating magnetic heads 3A and 3B and converts the output signals from the rotating magnetic heads into video signals. Phase pulse PG indicating the rotational phase and recording vertical synchronization signal REC in the video signal to be newly recorded
The position of one edge is determined based on the phase relationship with -VD, and the recording vertical synchronization signal REC-VD in the video signal to be newly recorded is used with the rotating magnetic head until the editing start point is reached. A pulse width modulation circuit (phase detection counter 17, buffer counter 18, phase difference correction counter in the embodiment) that forms a pulse whose phase relationship with the reproduced vertical synchronization signal PB-VD determines the position of the other edge. 24, flip-flop 23, etc.), and drives the motor 2 based on the output of the pulse width modulation circuit to control the rotational phase of the rotating magnetic heads 3A, 3B. This allows the vertical synchronization phase on the video track formed on the tape to match before and after the editing point. In particular, phase matching can be achieved using a pulse width modulation signal with a constant amplitude consisting of a high level and a low level without signal processing in the amplitude direction, so the circuit configuration is simple and digital It is suitable for processing and easy to integrate into integrated circuits.

[Brief explanation of drawings]

Figures 1a and b are recording pattern diagrams on a tape to explain the processes of assemble editing mode and insert editing mode, respectively. Figures 2a and b are diagrams of a phase shift of the synchronization signal before and after the editing point, respectively. 3 is a block diagram of a drum servo system of a VTR to which the present invention is applied; FIG. 4 is a circuit diagram of a phase servo circuit to which the present invention is applied; Figure 5 is a time chart showing the target to be achieved by this servo circuit, Figures 6 to 9 are waveform diagrams of each part of Figure 4, and Figure 10 is the process of phase alignment between the reproduction synchronization signal and the recording synchronization signal. 11 is a partial block diagram showing another embodiment of the present invention, and FIG. 12 is a waveform diagram of each part of FIG. 11. In addition, in the symbols used in the drawings, 9...phase servo circuit, 10...phase difference detection circuit, 11...editing phase correction circuit, 17...phase detection counter, 1
8... Buffer counter, 23... Flip-flop, 24... PEC counter.

Claims (1)

[Scope of Claims] 1. A rotating magnetic head that sequentially forms inclined tracks on a magnetic tape, a motor that drives the rotating magnetic head, and a rotation detector that detects the rotational phase of the motor and outputs a phase pulse. When editing and recording with a VTR that has a video signal recording and reproducing circuit that supplies a video signal to the rotating magnetic head and converts the output signal from the rotating magnetic head into a video signal, the phase pulse from the rotation detector and the , the position of one edge is determined based on the phase relationship with the recording vertical synchronization signal in the video signal to be newly recorded, and the recording vertical synchronization signal in the video signal to be newly recorded,
A pulse width modulation circuit is provided for forming a pulse that determines the position of the other edge based on the phase relationship with the reproduced vertical synchronization signal reproduced by the rotating magnetic head until reaching the editing start point, and the pulse width modulation circuit A phase servo circuit for controlling the rotational phase of the rotating magnetic head by driving the motor based on the output of the motor. 2. The phase servo circuit according to claim 1, wherein the control step amount for the other edge in the pulse width modulation circuit is variable in accordance with the amount of phase error between the recording vertical synchronization signal and the reproduction vertical synchronization signal.