JPH0338673B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal reading device for reading signals reproduced from a recording medium in which digital data and image signals are recorded in video format.

[Conventional technology]

When digital data is recorded on a recording medium and later reproduced, a clock signal is required to provide timing for reading the data. For this reason, a self-clock method is common in which a clock signal component is recorded together with data during recording, and a PLL circuit extracts the clock signal during playback. For example, the magazine "Electronic Technology" Volume 24, No. 11,
As disclosed on pages 36 to 37,
A 3.5-inch microfloppy disk has a sink area at the beginning of the data field, where the data is read.
The PLL circuit is designed to lock.
It takes some time for the PLL circuit to lock onto a signal of a predetermined frequency and phase, and this time becomes faster as the time constant of the loop filter included in the PLL circuit is smaller. On the other hand, if the time constant of the loop filter is made smaller, the response becomes faster, so it becomes more susceptible to the effects of noise, disturbance, etc., and becomes more likely to lose lock and become unstable. Therefore, in the sink area, the time constant is made small to lock the PLL circuit at high speed, and in the data area, the time constant is made large to prevent the lock from being lost due to noise, dropouts, etc. Furthermore, when the modulation method is FM, the clock signal in the sync area is half of that when it is MFM, so the time constant of the loop filter can also be switched.

[Problem that the invention seeks to solve]

However, such a conventional signal reading device has a drawback that, once the PLL circuit is locked, if the lock is lost for some reason, it takes time to lock it again. Furthermore, if the sink area in the above example cannot be locked within a predetermined period for some reason, there is a drawback that it takes a long time to finally lock.

[Means for solving problems]

FIG. 1 shows the configuration of a signal reading device according to the present invention. In the figure, 1 is an input terminal to which an input signal is supplied, and a separation circuit 2 that separates data from the input signal and a field sink provided at the beginning of the field in which data is recorded from the input signal are detected. It is connected to the detection circuit 3.
4 is a reading circuit for reading the digital data separated by the separation circuit 2; Reference numeral 5 denotes an extraction circuit for extracting the edges of the data separated by the separation circuit 2. A monostable multivibrator 6 is triggered in synchronization with the edge extracted by the extraction circuit 5, and its output pulse is supplied to a phase comparator 7 as a reference signal for the PLL circuit.
8 is a loop filter (low pass filter) to which the output of the phase comparator 7 is supplied; 9 is a voltage controlled oscillator controlled by the output of the loop filter 8; constitutes a PLL circuit. The output of the voltage controlled oscillator 9 is sent to the reading circuit 4 and the phase comparator 7.
is supplied to. A monitoring circuit 10 is connected to the phase comparator 7 and detects, for example, the level of the phase error signal of the phase comparator 7 to monitor whether the PLL circuit is locked to a signal of a predetermined frequency and phase. . A switching circuit 11 receives the output of the detection circuit 3 or the monitoring circuit 10 and switches the time constant of the loop filter 8.

[Effect]

The operation will now be explained. The signal input from input terminal 1 is a video format signal. Therefore, for example, when using the NTSC system,
Two fields each consisting of 262.5 horizontal scanning lines constitute one frame, and a vertical sync (vertical synchronization signal) is placed at the beginning of each field.
are provided only on predetermined lines. If the field is a video field, an image signal (analog signal) is recorded following vertical sync, and is similar to a normal television signal. If the field is a data field, the structure is as shown in FIG. 2, for example. That is, one line of field sync is provided following the vertical sync, the next four lines are control data blocks containing field codes, and then nine data blocks of 26 lines each are formed.

Since the separating circuit 2 separates and outputs only the data from the data field, the image signal of the video field is not supplied to the reading circuit 4 and the extracting circuit 5. The extraction circuit 5 extracts edges of the separated data and triggers the monostable multivibrator 6 at the timing of the extracted edges. The output pulse of this monostable multivibrator 6 becomes a reference signal for the PLL circuit. The reference signal contains a component equal to the clock frequency and the PLL
The circuit is frequency synchronized to this clock frequency. Further, the reference phase of the reference signal is determined by the data edge timing and the output pulse width of the monostable multivibrator 6, and the PLL circuit is phase-synchronized with this reference phase. In this way, the PLL circuit locks to a predetermined frequency and phase and outputs a clock signal, so that the reading circuit 4 can read digital data based on this timing.

By the way, when what is input to input terminal 1 is a data field, the 22nd line following the vertical sync is a field sync in which a bit synchronization signal is recorded. When this field sync is detected, the detection circuit 3 issues a signal to the switching circuit 11 to switch the time constant of the loop filter 8 to a smaller value. As a result, the PLL circuit responds quickly and quickly locks onto the bit synchronization signal. When the field sync is completed, the detection circuit 3 again issues a signal to the switching circuit 11 to switch the time constant of the loop filter 8 to a large value again. Therefore, the control data block containing the field codes of the 23rd line to the 26th line following the field sync, and then the 27th line to the 26th line.
In the section of data blocks that last nine blocks per line, the time constant of the loop filter 8 is switched to a large value. Therefore, the clock signal output by the voltage controlled oscillator 9 is stable during that time, even if there is noise, dropout, etc.
PLL circuits are becoming less susceptible to them.

However, if dropout occurs for a relatively long period of time or for other reasons, the PLL circuit may lose lock during the data interval.
Alternatively, the PLL circuit may not be able to lock during the field sync period. In such a case, the monitoring circuit 10 detects this and outputs a signal to the switching circuit 11. As a result, the time constant of the loop filter 8 is switched to a small value, and the PLL circuit is quickly locked. Thereafter, when the PLL circuit is locked, the monitoring circuit 10 issues a signal to the switching circuit 11 to switch the time constant of the loop filter 8 to a larger value.

〔effect〕

As described above, in the present invention, the lock state of the PLL circuit is monitored, and the time constant of the loop filter is switched to a small value not only during the field sync period but also when the lock is released. Even if the error occurs, it will be possible to recover quickly, minimize the damage during that time, and improve the probability that the data can be read accurately. Furthermore, even if locking is not possible during field sync, locking is performed immediately afterward, and the same effect can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the signal reading device of the present invention.
FIG. 2 is a schematic diagram of the signal. 2... Separation circuit, 3... Detection circuit, 4... Reading circuit, 5... Extracting circuit, 6... Monostable multivibrator, 7... Phase comparator, 8... Loop filter, 9... Voltage control Oscillator, 10...monitoring circuit, 11...switching circuit.

Claims (1)

[Claims] 1. In a signal reading device that reads a playback signal from a recording medium in which digital data and an image signal are recorded as a video format signal, the playback signal is recorded at the beginning of the data field in which digital data is recorded. a detection circuit that detects a field sync signal; a separation circuit that separates the digital data from the reproduced signal; an extraction circuit that extracts edges of the digital data separated by the separation circuit; A PLL circuit that extracts a clock signal from the edge, a reading circuit that reads the digital data separated by the separation circuit based on the clock signal extracted by the PLL circuit, and whether the PLL circuit is locked. and a switching circuit that switches the time constant of the loop filter of the PLL circuit, and when the detection circuit detects the field sync, controls the switching circuit and changes the time constant of the loop filter. A signal reading device characterized in that the time constant of the loop filter is reduced by controlling the switching circuit when the monitoring circuit detects that the PLL circuit is unlocked.