JPH0339416B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a D-A conversion circuit and a D-A conversion method for converting a quantized digital signal into an analog signal. It is used in audio equipment such as audio tapes, and its purpose is to reduce distortion and speed up operation.

Generally, an analog audio signal is sampled and the quantized digital signal is recorded on a DAD or digital audio tape. For reproduction, the recorded digital signal is extracted and converted into an analog signal.

Conventionally, there is a method for converting a digital signal into an analog signal by using a ladder type resistance circuit or the like to synthesize weighted electrical quantities, such as current or voltage. A DA converter using this method generates noise when reproducing a very low level signal. In other words, when reproducing a small level, the input digital signal constantly goes back and forth between "011...111" and "100...000", so the resistor that generates the weighted amount of electricity is turned off each time. Therefore, the error in the resistor appears as noise. Furthermore, when the number of bits of digital signals increases and high resolution is required, it is necessary to adjust individual resistors such as ladder-type resistor circuits to accurate values by precise trimming, which requires technical difficulties. This has been a cause of the high cost of high-resolution D-A converters.

Furthermore, conventionally, an integral type D-A converter is formed as shown in FIG. In FIG. 1, an operational amplifier 1, a capacitor 2, and an input resistor 3 form an integrator. A reference potential source 4 is connected to the input resistor 3 via a switch means 5, and switch means 6 are also provided at both ends of the capacitor 2. The opening and closing of the switch means 5 and 6 are controlled by a control circuit 7. In particular, the closing time of the switch means 5 is determined by a time generating circuit 8 to which the digital signal is applied. Determined by the time created based on the value. That is, first, by closing and opening the switch means 6, the electric charge of the capacitor 2 is discharged, and the operational amplifier 1 is discharged.
Set the output voltage to 0 volts. Then, at the same time as the switch means 5 is closed, the time generating circuit 8 counts the clock pulse CLK applied from the outside,
When the count matches the applied digital signal, the switch means 5 is opened. Therefore,
During the counting time, the integrator integrates the voltage of the reference potential source 4, a voltage proportional to the counting time is generated at the output of the operational amplifier 1, and DA conversion is performed. However, in this integration method, if the resolution of the digital signal is n bits, a maximum of ^22-1 clock pulses are required, so the higher the resolution, the longer it takes to obtain the output and the operation becomes slower. It had the disadvantage of being slow.

The present invention has been made in view of the above points, and includes a plurality of continuously connected integrating circuits, and divides a digital signal to be converted into an analog signal into N groups each having an arbitrary number of bits. , which provides a D-A conversion method capable of high-speed operation with low distortion by performing conversion operation for each group using an integrating circuit and accumulating the integration results of each group in the final stage integrating circuit. It is. Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention, in which integrating circuits ₁ to _N include an operational amplifier 9, a resistor 10 connected to one input terminal of the operational amplifier 9,
Each of them is composed of a capacitor 11 connected between one input terminal and an output terminal. This integrator circuit
₁ to _N are continuously connected via the switch means 12, and the reference potential source 14 is connected to the first stage integrating circuit ₁ via the switch means 12. Further, switch means 13 for discharging accumulated charges is provided at both ends of the capacitors 11 of each of the integrating circuits ₁ to _N. Integrating circuits ₁ to _N use a resistor 10 and a capacitor 11 to control the output voltage of the reference potential source 14 or the previous integrating circuit during the time when the switch means 12 connected to the input side is closed.
and the switching means 12
When opened, the output voltage at that time is held.

The switching means 12 and 13 are opened and closed by the control circuit 1.
The control circuit 15 is controlled by control signals a ₁ to a _N and b ₁ to b _N output from the time generating circuit 16
Based on the output of the counter 17, the switch means 12, 13 and the latch circuit 18 are controlled according to a predetermined procedure. The latch circuits 18 divide the digital signal to be converted into N groups and store the digital signals for each group, and there are N latch circuits 18 provided. Further, the digital signals stored in the latch circuit 18 are sequentially sent to the multiplexer 19 by control signals C ₁ to C _N of the control circuit 15.
is applied to the counter 17 via. counter 1
7 counts the applied reference clock pulse CLK and creates a time corresponding to the data value of each group. Specifically, the reference clock pulse CLK is counted.
CLK is counted by a number equal to the data value of each group, and the output is outputted to the control circuit 15. When operating the required number of integrating circuits ₁ to _N to generate a weighted voltage corresponding to the least significant bit of each group, the time generating circuit 16 counts the applied reference clock pulses CLK and calculates each integral It is what creates time.

The n-bit digital signal stored in the latch circuit 18 is divided into N groups G ₁ to G _N in order from the least significant bit, as shown in FIG. In the case of this embodiment, the number of stages of continuously connected integrating circuits and the number of digital signal groups are equal. Also, each group consists of arbitrary bits,
Assume that G ₁ is D ₁ bit, G ₂ is D ₂ bits...G _N is D _N bits. The procedure for converting the digital signals divided in this way will be explained with reference to FIGS. 2 and 4.

Figure 4 is a diagram showing the integration time of integration circuits ₁ to _N , that is, the number of reference clock pulses _CLK , in the integration operation of _each group. Groups are shown. The reference potential source 14 is a reference potential corresponding to the least significant bit of the digital signal, and by integrating this reference potential source ₁₄ by the number of reference clock pulses equal to the data value of group G1 in the integrating circuit ₁ , The amount of electricity corresponding to the data of ₁ can be obtained. That is, the control signal _a1 closes the first stage switch means 12, and at the same time, the control signal _C1 sends data from the stored latch circuit 18 of group _G1 to the counter 17. Counter 17 outputs the reference clock pulse for the data value of group _G1 .
After counting CLK, the control signal _a1 opens the first stage switch means 12. The output voltage V ₁ of the integrating circuit ₁ is integrated by the integrating circuit 2 by opening and closing the second stage switch means 12 for a time determined by the time generating circuit 16, that is, for _one reference clock pulse CLK. Ru. Furthermore, the integration circuits ₃ to _N from the third stage onward continue in the same way,
By integrating one reference clock pulse CLK, the converted analog voltage of group _G1 is held in the final stage integrating circuit _N.

Next, convert group _G2 . First, the first stage switch means 12 is closed for a time determined by the time generating circuit 16, and the weighted electrical quantity corresponding to the least significant bit of group _G2 is transferred to the integrating circuit.
₁ output. That is, since the number represented by the least significant bit of group _G2 is 2 ^D1 , the time generating circuit 16 generates time to count 2 ^D1 reference clock pulses CLK, and the integrator circuit ₁ integrates 2 ^D1 times. Accordingly, a weighted electrical quantity corresponding to the least significant bit of group _G2 is output. This quantity of electricity is integrated in the integrating circuit 2 during the period during which the counter 17 counts a number of reference clock pulses CLK equal to the data value of group G ₂ , so that the output voltage _{V 2 corresponds} to the data value of group G ₂ . It becomes the amount of electricity. As described above, the third and subsequent stages of integration circuits ₃ to _N successively integrate this electrical quantity for one reference clock pulse CLK. At this time,
The final stage integrating circuit _N holds an electrical quantity obtained by adding the converted electrical quantity of group G ₂ to the converted electrical quantity of group G ₁ .

The number represented by the least significant bit of group _G3 is
2 ^D1+D2 , that is, 2 ^D1・2 ^D2 , so group G _3
The weighted voltage corresponding to ^the least significant bit of
₂ performs integration for a period equal to 2 reference clock pulses ^CLK2 , and the output voltage V ₂ of integration circuit ₂ is
occurs in Therefore, the integration of the period corresponding to the data value of group _G3 is performed by the integration circuit ₃ , and the converted electrical quantity is added to the integration circuit _N at the final stage, as described above.

Thereafter, by performing the same operation up to the group G _N , the output voltage V _N of the integrating circuit _N becomes an analog signal obtained by converting an n-bit digital signal. In the above operation, each of the integrating circuits ₁ to _N-1 except the final stage always opens and closes the switch means 13 and closes the capacitor 11 before performing the integrating operation.
Discharge the charge and initialize it.

Also, in FIG. 2, there is an offset voltage at the input of the operational amplifier 9, and when the integration circuits ₁ to _N are connected in multiple stages, this offset voltage occurs as an error. Now, 10 resistors and 1 capacitor
1 are R and C, and the offset voltage of each integrating circuit ₁ to _N is Vε. When converting one group, the integration time of each integrating circuit ₁ to _N is T ₁ , T ₂ ...T _N , the output voltage V ₁
is V ₁ =T ₁ /CR(V ₀ +Vε), which is equivalent to applying V ₀ +Vε to the integrating circuit ₁ via the first stage switch means 12, so V ₀ +Vε=V ′ ₀ , V ₁ =T ₁ /CRV′ ₀ V ₂ =T ₂ /CR(V ₁ +Vε)=T ₁・T ₂ /(CR) ² V′ ₀ +T ₂ /
CRVε V ₃ = T ₃ /CR (V ₂ + Vε) = T ₁・T ₂・T ₃ /(CR) ³ V′ ₀ +
(T ₂・T ₃ /(CR) ² +T ₃ /CR)Vε 〓 V _N =T _N /CR (V _N-1 +Vε)=T ₁・T ₂・...T _N /(CR)NV
′ ₀ + (T ₂・T ₃ …T _N / (CR) ^N-1 +T ₃・T ₄ …T _N / (CR) ^N-
2 +…+T _N /CR)Vε. Therefore, the term Vε becomes the error term, so
In order to minimize this error, it is necessary to make the integration time T _N the shortest, followed by T _N-1 , T _N-2 , and so on. That is, as shown in FIG. 4, it is necessary to perform long-time integration in the previous stage. Furthermore, in order to reduce the error, it is also necessary to reduce the offset voltage Vε of the operational amplifier 9 itself as much as possible.

FIG. 5 is a diagram showing the number of reference clock pulses for each of the integrating circuits ₁ to ₄ when the 16-bit digital signal is divided into four groups of 4 bits each. According to FIG. 5, the number of reference clock pulses required for integration to convert all four groups is 102 + data value of group G ₁ + data value of group G ₂ + data value of group G ₃ + data value of group G _4.
The data value is . Therefore, since each group has 4 bits, the maximum value of each group is 15, so the maximum number of reference clock pulses required for integration when converting a 16-bit digital signal is 162.
It is individual. On the other hand, the number of reference clock pulses required by the integration method shown in FIG. 1 is 2 ¹⁶ =65536. In this way, according to this embodiment, the time is significantly reduced compared to the conventional method.

Furthermore, in FIG. 5, the integration of the integrating circuit ₃ in group _G1 is performed during the integration of the integrating circuit ₁ in group _G2 . Also, during the integration of the integration circuit ₂ in the group _G2 , the integration of the integration circuit ₄ of the group _G1 is performed. That is, when the subsequent integrating circuit ₃ or ₄ is performing an integrating operation, the preceding integrating circuit ₁ or ₂ is vacant, so it performs the integrating operation of the next group, and by performing the overlapping operation, Furthermore, conversion time is reduced.

As described above, according to the present invention, the feature of the integration method, that is, its excellent linearity, is utilized, and the digital signal is divided into N groups, and the lowest bit of each group is divided into N groups. By creating weighted voltages using predetermined stages of integral circuits that are continuously connected in a plurality of stages, conversion time can be shortened even in the case of high resolution, and high-speed operation can be performed. Furthermore, the circuit that controls the integration circuit does not require analog circuits that require precision.
Since it can be constructed using only digital circuits, it also has the advantage of being easy to integrate.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional example, Figure 2 is a block diagram showing an embodiment of the present invention, Figure 3 is a diagram showing data division, and Figures 4 and 5 are the number of reference clock pulses required for integration. FIG. 9... operational amplifier, 10... resistor, 11... capacitor, 12, 13... switch means, 14... reference potential source, 15... control circuit, 16... time generating circuit, 17
...Counter, 18...Latch circuit, 19...Multiplexer.

Claims (1)

[Claims] 1 N bits are provided corresponding to N groups obtained by dividing a digital signal consisting of n bits into an arbitrary number of bits starting from the least significant bit, and are continuously connected in N stages.
a reference voltage source for applying a reference voltage corresponding to the least significant bit of the digital signal, the reference voltage source being connected to the input of the first stage of the integrating circuit;
a switch circuit interposed between the reference voltage source and the first-stage integrating circuit and between each integrating circuit; a memory circuit for storing the contents of the N groups of digital signals; a counter that sequentially counts based on clock pulses; a time generation circuit that generates a time corresponding to the least significant bit of each of the N groups of the digital signal based on the reference clock; and an output of the counter and the time generation circuit. and a control circuit that controls opening and closing of the switch circuit based on the output of the digital signal, and a control circuit that controls opening and closing of the switch circuit based on the output of the digital signal. The voltage source and the reference voltage source are created by continuous integration of m stages (m=1, 2,...N-1) of the integrating circuit, and the weighted electrical quantity is further integrated by the subsequent integrating circuit. A DA converter characterized in that an analog signal corresponding to the digital signal is obtained by integrating for a time based on the data value of the group and accumulating the integration result of each group in a final stage integrating circuit.