JPH033943B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to
This article relates to a method for measuring the dimensions required to evaluate the characteristics of MOS transistors or MOS transistors built into MOS type large-scale integrated circuits (LSI).

Conventional Structures and Problems The miniaturization of large-scale integrated circuits has progressed, and MOS transistors having gate lengths of 2 to 3 μm or less have been integrated. As the gate length becomes shorter, a short channel effect occurs, making it difficult to set the threshold voltage. In order to maintain high manufacturing yields in such large-scale integrated circuits, it is necessary to know not only the gate length dimension but also the effective channel length, which is obtained by subtracting the lateral diffusion spread of the source and drain diffusion layers. There is.

FIG. 1 shows the principle of a conventional example in which the effective channel length is determined from the characteristics of a MOS transistor. The explanation of Figure 1 can be found in the literature by JGJCHERN et al. (IEEE ELECTRON DEVICE LETTERS).
VOL.EDL-1, No. 9, 1980).

I- in the linear region of a MOS transistor
From the V characteristics, the drain current I _DS and drain resistance are
R _chao is I _DS = μ _s C _px W _eff /L _eff (V _GS −V _T −1/2V _DS )V _DS R _chao = V _DS /I _DS =L _eff / μ _s C _px W _eff (V _GS −V _T −1/2V _DS ).

Here, I _DS : Drain-source current V _DS : Drain-source voltage V _GS : Gate-source voltage V _T : Gate threshold voltage μ _s : Mobility of carrier in channel C _px : Gate oxide film capacitance L _eff : Effective channel length W _eff : Effective channel width R _chao : Channel resistance.

Furthermore, the drain resistance R _n measured from W _eff = W _MASK −ΔW L _eff = L _MASK −ΔL R _n = R _ext + R _chao is becomes.

Here, W _MASK : Channel width on the mask L _MASK : Channel length on the mask ΔW=W _MASK −W _eff ΔL=L _MASK −L _eff R _n : Drain resistance to be measured R _ext : External resistance.

In order to calculate the effective channel length L _eff , the relationship in equation (1) is used. The relationship between the measured drain resistance and the channel length on the mask is linear. 1st
The figure illustrates the relationship expressed by equation (1), where the horizontal axis represents the channel length on the mask and the vertical axis represents the measured drain resistance. The slopes a, b, and c of the straight line are (1)
It can be changed arbitrarily by changing the gate-source voltage _VGS in the equation. When the slope is changed like a, b, and c, when the drain voltage V _DS is constant, the point (ΔL, R _ext ) is found as the intersection. ΔL
Once determined, the effective channel length L _eff can be determined from the dimension L _MASK on the mask as L _eff = L _MASK −ΔL.

As described above, according to the conventional method, the effective channel length L _eff must be determined indirectly from several types of transistor characteristics. Therefore, it is not easy to automate measurements using a tester or the like during the manufacturing process.

Further, as a more direct measurement method than this method, there is a method using scanning electron microscopy.

With this method, the diffusion layer and gate length dimensions can be directly and accurately measured, but the sample must be destroyed for measurement.

Additionally, prior to measurement, a specific location on the sample must be precisely cleaved and then etched on this area, allowing a large number of inspections and evaluations to be performed automatically and in a short period of time during the manufacturing process. That is difficult. As described above, the conventional measurement method has a problem that makes it difficult to adopt it in the production of semiconductor devices.

Purpose of the Invention The purpose of the present invention is to provide a dimension measurement method that allows the effective channel length to be determined from the resistance of a diffusion layer sandwiched between two gate materials, and that allows easy inspection using an inspection device such as a tester. Our goal is to provide the following.

Structure of the Invention The dimension measurement method of the present invention uses a so-called Van der Pauw pattern, which is created to determine the layer resistance of the source and drain diffusion layers that determine the effective channel length. The gate material of the MOS transistor or the mask material formed thereon, such as a resist, is placed in a positional relationship separated by a distance GM based on a predetermined design rule, and these are placed facing each other in the test pattern formation area. have the same shape, and further, using these as a mask, diffuse impurities into the semiconductor substrate region located between them,
A diffused resistance layer having a length and width based on predetermined design rules is formed, a current source terminal and a voltage measurement terminal are attached to determine the resistance value of this diffused resistance layer, and electrodes attached to the above test pattern are attached. This is a method of measuring dimensions from the measurement results of the layer resistance value of the test pattern used and the length, width, and resistance value of the diffusion resistance layer.

If this dimension measurement method is adopted, it is possible to measure not only the effective channel length when impurity introduction such as ion implantation is self-aligned to form source and drain diffusion layers only at the gate electrode, but also the effective channel length of the gate electrode. It is also possible to measure the effective channel length when impurity introduction such as ion implantation is self-aligned depending on the mask material formed above.

DESCRIPTION OF THE EMBODIMENTS FIG. 2 is a diagram for explaining the principle of the dimension measurement method of the present invention. On the surface of the semiconductor substrate 1, gates 2 and 3 whose gate lengths are selected to have the same value L are formed. The gates 2 and 3 are arranged at a distance G, and mask layers 4 and 5 made of a resist film or an oxide film are formed on the gates 2 and 3 to form them by etching. Their lengths are both LR and their separation is GR. Note that 6 and 7 in the figure schematically indicate patterns on a mask for forming patterns of the mask layers 4 and 5, and have a length LM and a spacing GM. Further, 8 is a gate insulating film, and 9 is a diffusion layer formed in the semiconductor substrate 1. Incidentally, the diffusion layer 8 is self-aligned by the mask layers 4 and 5 or the gates 2 and 3 made of resist or oxide film, and is formed by, for example, ion implantation and subsequent heat treatment. Diffusion layer 9
The length of is GD and the interval is LEF. This LEF
is the effective channel length.

10 is the lateral extent of the diffusion layer 8 from the edge of the gate, and its length is Δl.

Based on the drawings explained above, gates 2 and 3
The effective channel length LEF formed at the bottom of is determined as follows. Effective channel length
Since the sum 2Δl of LEF and the lateral spread of the diffusion layer 8 directly below the gate is expressed by the formula LEF=L−2Δl 2Δl=GD−G, the effective channel length is
LEF is LEF=L-(GD-G)=L+G-GD=const-GD...(2).

Here, L+G=const (3) That is, L+G in equation (3) is the total pitch of the line length and line spacing at the time of mask design, and is a constant value regardless of pattern transfer, etching, or diffusion.

Note that equation (2) can be derived without using the lateral diffusion spread Δl. As shown in equation (3) above, the sum of line length and interval holds true for each of the mask, resist, gate, and diffusion layer, so the formula LM+GM=LR+GR=L+G=LEF+GD+const. holds true. From this relational expression, the effective channel length LEF is LEF=const.−GD (4). This equation (4) is equivalent to equation (2).

As mentioned above, the effective channel length LEF can be determined by determining the length GD of the diffusion layer 8 formed in the semiconductor substrate located between the two gate materials or between the mask layer made of resist or oxide film thereon.
It can be accurately calculated from predetermined design rule values.

FIG. 3 shows the pattern structure and electrode configuration for actually determining the effective channel length LEF according to the dimension measuring method of the invention described above.
Functionally, this pattern structure and electrode configuration are composed of a Juan de Pauw pattern portion for determining the layer resistance R _s of the diffusion layer, and a bridge portion for determining the length of the diffusion layer.

In the figure, 11, 12, 13 and 14 are Juan
The electrodes have a de-Pauw pattern, and each is connected to a diffusion layer 16 through a contact portion 15. Then, a current I _s is passed between the electrodes 12 and 13, and a voltage V _s generated between the electrodes 11 and 14 is measured. Electrodes 14, 17, 18 and 19 are electrodes of a bridge circuit for measuring the diffusion length GD of a diffusion layer 22 formed in a semiconductor substrate portion sandwiched between gate materials 20 and 21. The diffusion layer 22 is connected to the diffusion layer 16, and each electrode 14, 17 to
19 is connected to the diffusion layer through the contact portion 15. Note that the electrode 14 serves both as an electrode for the Juan de Pauw pattern and as an electrode for the bridge circuit. Incidentally, the cross-sectional structure of the pattern shown along the line X--X corresponds to the structure when only one diffusion layer is formed between the gate materials 2 and 3 in the principle explanatory diagram of FIG. 2. That is, gate materials 2 and 3 in FIG. 2 correspond to gates 20 and 21 in FIG. 3.

The gate materials 20 and 21 are separated by a distance G, and have a length W that is sufficiently larger than the distance G.

A current I _B is passed between electrodes 14 and 19, and electrode 17
Measure the voltage V _B between and 18.

The effective channel length LEF can be calculated from the following formula.

R _s = π/1 _o 2・V _s /I _s GD=R _s ×W×I _B /V _B …(5) formula LEF=C−GD where R _s : Resistance of the diffusion layer 16 V _s : Electrode Measuring voltage I _s between electrodes 11 and 14 : Current flowing between electrodes 12 and 13 GD : Length W of diffusion layer 22 : Length I of gate material 20 and 21 I _B : Current flowing between electrodes 14 and 19 V _B : Measuring voltage between electrodes 17 and 19 C: Constant determined by design rules C=G+L G: Dimension on mask of distance between gate materials 20 and 21 L: Mask dimension of gate length of effective channel length to be measured It is. Note that the MOS transistor in the LSI to be measured and the Juan de Pauw pattern are usually formed at close positions in the silicon wafer.
Therefore, conditions such as impurity diffusion conditions can be considered to be almost the same, and the diffusion length GD in equation (5)
can be regarded as the same value for the diffusion layer GD in equation (4). Furthermore, even if there is an error, it is a negligible error. Therefore, the effective channel length of the MOS transistor can be calculated more accurately from the diffusion length GD and the mask design value. Incidentally, an effective channel length of 3.07±0.05 μm was obtained for the gate dimension on the mask of 3.8 μm and the resist dimension on the gate of 4.22±0.15 μm. The lateral extent of diffusion is calculated to be approximately 0.5 μm.

The resulting diffusion depth was actually measured and found to be 0.59 μm. From this, it became clear that the dimension measurement according to the present invention was carried out correctly.

Note that although the diagram shown in FIG. 3 shows a structure in which the diffusion layers 16 and 22 are connected and the electrode 14 is used as a common electrode in order to reduce the number of electrodes, it is possible to connect the diffusion layers 16 and 22 independently. You can also do so. In this case, one more electrode may be added. What is important is to make the formation positions of the diffusion layers 16 and 22 as close to each other as possible, and to take care to avoid variations due to the positions between them.

Effects of the Invention As explained above, according to the method for measuring the effective channel length according to the present invention,
The effective channel length of a MOS transistor can be determined more directly than with conventional methods from electrical measurement results and a simple relational expression.

Therefore, it is possible to carry out inspections of semiconductor manufacturing process conditions automatically and in large quantities. In other words, the effective gate length can be determined using a simple method without having to prepare a number of mask design values as in the conventional example. Furthermore, since this method is a non-destructive method, it has the advantage that no restrictions are imposed on the measurement sample.

[Brief explanation of the drawing]

Figure 1 is a diagram for explaining the conventional measurement method for determining the effective channel length of a MOS transistor from a MOS transistor, and Figure 2 is a diagram for explaining the principle of the dimension measurement method of the present invention.
A schematic cross-sectional view of the transistor structure, FIG.
FIG. 2 is a plan view showing a pattern structure and an electrode structure that enable the dimension measurement method of the present invention. 1... Semiconductor substrate, 2, 3, 20, 21... Gate material, 4, 5... Mask layer, 6, 7... Pattern on mask, 8... Gate insulating film, 9, 22
... Diffusion layer, 10 ... Laterally expanding part of the diffusion layer, 1
1 to 14... Juan de Pauw pattern electrode,
15... Contact portion, 16... Diffusion layer for R _s measurement, 17-19... Electrode for measuring diffusion length GD of diffusion layer 22.

Claims (1)

[Claims] 1. In the vicinity of a test pattern formed in a semiconductor wafer and having a first diffusion region for measuring the layer resistance of the drain and source regions, identical shapes facing each other with a predetermined interval are provided. A gate material or a masking material is disposed, and a second diffusion region is formed in the semiconductor substrate between the gate materials or the masking material, and current-carrying electrodes and voltage measurement electrodes are provided at both ends of the second diffusion layer. an electrode, and calculating an effective ionnel length from the measured values of the layer resistance of the first diffusion region and the resistance value of the second diffusion region, and the set length of the second diffusion region. A method for measuring dimensions of a semiconductor device, characterized by: 2. The method for measuring dimensions of a semiconductor device according to claim 1, wherein the first diffusion region and the second diffusion region are connected to each other.