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JPH0339998B2 - - Google Patents
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JPH0339998B2 - - Google Patents

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Publication number
JPH0339998B2
JPH0339998B2 JP57124118A JP12411882A JPH0339998B2 JP H0339998 B2 JPH0339998 B2 JP H0339998B2 JP 57124118 A JP57124118 A JP 57124118A JP 12411882 A JP12411882 A JP 12411882A JP H0339998 B2 JPH0339998 B2 JP H0339998B2
Authority
JP
Japan
Prior art keywords
wafer
oxygen
oxygen concentration
atoms
defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57124118A
Other languages
Japanese (ja)
Other versions
JPS5918198A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12411882A priority Critical patent/JPS5918198A/en
Publication of JPS5918198A publication Critical patent/JPS5918198A/en
Publication of JPH0339998B2 publication Critical patent/JPH0339998B2/ja
Granted legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00Single-crystal growth by pulling from a melt, e.g. Czochralski method

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Description

【発明の詳細な説明】 本発明は新規かつ改良された半導体電子装置
(デバイス)の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a new and improved method of manufacturing semiconductor electronic devices.

従来、チヨクラルスキー法(CZ法)で育成し
たシリコン単結晶にはその製造過程を通じて多量
の酸素不純物が混入されており、この酸素不純物
は熱プロセスを経ることにより結晶欠陥の原因と
なることが知られている。
Traditionally, silicon single crystals grown using the Czyochralski method (CZ method) are contaminated with large amounts of oxygen impurities during the manufacturing process, and these oxygen impurities can cause crystal defects through thermal processes. Are known.

この欠陥は主としてデバイスを製作するプロセ
ス中に発生し、特にこれがウエーハ表面(デバイ
スの活性化領域)に発生した場合にはデバイスの
特性を極度に低下させることになるので、これま
ではシリコン単結晶に対する酸素不純物濃度をで
きるだけ下げるべく努力が払われてきた。
These defects mainly occur during the process of manufacturing devices, and if they occur on the wafer surface (the active region of the device), they can severely degrade device characteristics. Efforts have been made to reduce the oxygen impurity concentration as much as possible.

本発明は上記した酸素不純物の存在を有効に利
用し、これをデバイスの特性向上に寄与させよう
とするものであつて、これはチヨクラルスキー法
により得られるシリコン単結晶中に積極的に酸素
を導入し、この際その酸素濃度を8.5×1017〜10.5
×1017原子/立方センチメートルに規定したシリ
コン単結晶より得たウエーハを始発原料とし、そ
の表面に集積回路を900〜1200℃の温度条件下で
形成させる半導体電子装置の製造方法である。
The present invention effectively utilizes the presence of oxygen impurities described above to contribute to improving the characteristics of devices. was introduced, and at this time the oxygen concentration was adjusted to 8.5×10 17 to 10.5
This is a method for manufacturing semiconductor electronic devices in which a wafer obtained from a silicon single crystal with a density of ×10 17 atoms/cubic centimeter is used as a starting material and an integrated circuit is formed on the surface of the wafer at a temperature of 900 to 1200°C.

これを説明すると、本発明者らはデバイス基板
用単結晶シリコンウエーハの酸素濃度について
種々検討したところ、この酸素濃度が低すぎると
きはデバイスの製造に際し、900〜1200℃の熱処
理を経ても酸素の析出はさほど起らず、逆に酸素
濃度が高すぎるときには前記したようにウエーハ
表面(デバイス活性化領域)に酸素が析出してこ
れが原因となつて欠陥が発生し、デバイスの特性
を極度に悪くするようになつてしまうが、しかし
上記のように本発明に従つてシリコン単結晶の酸
素濃度を8.5×1017〜10.5×1017原子/立方センチ
メートルに規定するときには、上記のように酸素
の析出によるウエーハ表面の欠陥がなく、おどろ
くことにはウエーハ表面のライフタイムを向上さ
せることができることを確認し本発明を完成する
に至つたものである。
To explain this, the present inventors conducted various studies on the oxygen concentration of single crystal silicon wafers for device substrates, and found that when the oxygen concentration is too low, even after heat treatment at 900 to 1200 degrees Celsius during device manufacturing, oxygen is removed. Precipitation does not occur much; on the other hand, when the oxygen concentration is too high, as mentioned above, oxygen precipitates on the wafer surface (device activation region), which causes defects and extremely deteriorates device characteristics. However, when the oxygen concentration of the silicon single crystal is defined as 8.5×10 17 to 10.5×10 17 atoms/cm3 according to the present invention as described above, the The present invention was completed after confirming that there were no defects on the wafer surface and, surprisingly, that the lifetime of the wafer surface could be improved.

例えば、約800℃では、シリコン単結晶中の酸
素原子の拡散係数が小さくなりすぎるためと想像
されるが、ウエーハ内部に酸素の析出が起こらず
その結果ウエーハのライフタイムは向上しかなつ
た。しかし酸素濃度が9.0×1017原子/立方セン
チメートル、体積固有抵抗が約10Ωcmのp型シリ
コンウエーハは800℃で2時間熱処理したところ、
当初200マイクロ秒であつたライフタイムが僅か
に低下した。このライフタイムの低下は熱処理時
の汚染によるものと考えられる。一方1280℃でウ
エーハを熱処理したところ、表面はもちろんウエ
ーハ内部にも酸素の析出は起きなかつた。この理
由は、高温領域ではシリコンの酸素許容溶解度が
大きくなるためにウエーハ内の酸素が析出しにく
くなると考えられる。以上の実験と考察から、総
合的に酸素濃度が8.5×1017〜10.5×1017原子/立
方センチメートルのウエーハを900〜1200℃の範
囲で熱処理することにより、ウエーハ中の溶存酸
素はウエーハの表面ではなく内部に析出し、微小
な結晶欠陥を作つて集積回路を形成するウエーハ
表面のライフタイムを向上させることが可能にな
ると結論した。
For example, at approximately 800°C, the diffusion coefficient of oxygen atoms in the silicon single crystal becomes too small, but no oxygen precipitates inside the wafer, and as a result, the wafer's lifetime can only be improved. However, when a p-type silicon wafer with an oxygen concentration of 9.0×10 17 atoms/cm3 and a volume resistivity of approximately 10 Ωcm was heat-treated at 800°C for 2 hours,
The lifetime, which was originally 200 microseconds, has decreased slightly. This decrease in lifetime is thought to be due to contamination during heat treatment. On the other hand, when the wafer was heat-treated at 1280°C, no oxygen was precipitated on the surface or inside the wafer. The reason for this is thought to be that in a high temperature region, the permissible solubility of silicon in oxygen increases, making it difficult for oxygen to precipitate within the wafer. From the above experiments and considerations, by heat-treating a wafer with an overall oxygen concentration of 8.5 x 10 17 to 10.5 x 10 17 atoms/cubic centimeter in the range of 900 to 1200°C, dissolved oxygen in the wafer can be removed from the surface of the wafer. They concluded that it is possible to improve the lifetime of the wafer surface on which integrated circuits are formed by precipitating inside the wafer and creating minute crystal defects.

つぎに本発明を、シリコンウエーハ上にモス型
集積回路を形成する場合に関連して説明する。
Next, the present invention will be described in connection with forming a MOS type integrated circuit on a silicon wafer.

Nチヤンネルモス型集積回路形成のプロセスを
ゲート酸素膜の形成までに限定して一例を述べる
と、つぎの13工程からなる。
An example of the process for forming an N-channel MOS type integrated circuit limited to the formation of the gate oxygen film consists of the following 13 steps.

第1工程 初期酸化膜形成 1000℃ 第2工程 Si3N4膜成長 第3工程 フオトリングラフイ 第4工程 Si3N4エツチ 第5工程 Bイオン注入 第6工程 フオトレジスト除去 第7工程 フイールド酸化 1000℃ 第8工程 SiO2エツチ 第9工程 Si3N4膜 第10工程 SiO2エツチ 第11工程 酸化 1000℃ 第12工程 SiO2エツチ 第13工程 ゲート酸化 950℃ 上記の一部工程に処理温度を併記したが、これ
が集積回路形成工程の熱処理の温度であり、上記
例では1000℃付近が熱処理温度として選択されて
いる。
1st process Initial oxide film formation 1000℃ 2nd process Si 3 N 4 film growth 3rd process Photolithography 4th process Si 3 N 4 etching 5th process B ion implantation 6th process Photoresist removal 7th process Field oxidation 1000℃ 8th process SiO 2 etch 9th process Si 3 N 4 film 10th process SiO 2 etch 11th process Oxidation 1000℃ 12th process SiO 2 etch 13th process Gate oxidation 950℃ As mentioned above, this is the heat treatment temperature in the integrated circuit forming process, and in the above example, around 1000° C. is selected as the heat treatment temperature.

上記の集積回路の形成プロセス中にウエーハの
含有酸素が熱処理により析出したり、しなかつた
りして目的とする集積回路の良否の目安には、例
えば第13工程のゲート酸化における当該酸化膜の
耐圧電気特性があげられる。この酸化膜の耐圧
は、当然ながらウエーハ表面層における結晶欠陥
発生の良否およびウエーハ内部の結晶欠陥の形成
とそのゲツター効果によるウエーハ表面の清浄化
に大いに影響を受ける。
During the above integrated circuit formation process, whether the oxygen contained in the wafer is precipitated or not due to heat treatment, and whether or not the oxygen contained in the wafer is precipitated or not is determined as a measure of the quality of the intended integrated circuit. Examples include electrical properties. Naturally, the withstand voltage of this oxide film is greatly influenced by the quality of crystal defect generation in the wafer surface layer, the formation of crystal defects inside the wafer, and the cleaning of the wafer surface due to its getter effect.

つぎに、8.5×1017〜10.5×1017原子/立方セン
チメートルの酸素濃度を有するウエーハが900〜
1200℃の温度範囲の熱処理によつて、どのように
シリコンウエーハの表面および内部で結晶欠陥が
発生するかを説明し、上記酸素濃度範囲のウエー
ハを用い、かつ900〜1200℃の温度範囲をその工
程の一部で採用することによつて、収率よくある
いは高性能の集積回路の形成が可能であることを
説明する。
Next, a wafer with an oxygen concentration of 8.5 × 10 17 ~ 10.5 × 10 17 atoms/cm3 is
Explain how crystal defects occur on the surface and inside of silicon wafers due to heat treatment in the temperature range of 1200℃, and explain how heat treatment in the temperature range of 900 to 1200℃ is performed using wafers with the above oxygen concentration range. It will be explained that by employing this method in a part of the process, it is possible to form integrated circuits with high yield or high performance.

第2図は、高酸素濃度すなわち12.5×1017
子/立方センチメートルのシリコンウエーハを
1000℃で2時間熱処理し、そのウエーハ断面の欠
陥分布を観察した例である。かかる高酸素濃度の
ウエーハでは、結晶欠陥が表面まで生成してお
り、このような状態でこのウエーハ表面に集積回
路が形成されると、モス型では前述のゲート酸化
膜の耐圧特性は明らかに劣化することが予想され
る。第3図、第4図は、それぞれ酸素濃度が7.5
×1017原子/立方センチメートル、9.5×1017
子/立方センチメートルであるウエーハを同じく
1100℃で2時間熱処理したときのウエーハ表面の
欠陥を観察したものである。7.5×1017原子/立
方センチメートルの低酸素濃度のウエーハでは、
前記12.5×1017原子/立方センチメートルの酸素
濃度の場合と同様にウエーハ表面に微小欠陥が形
成されているが、その欠陥の性質は異なつている
ものと考える。しかし欠陥があるウエーハ表面に
は、特性の良い集積回路はできない。バイポーラ
型の場合は、ウエーハ表面近傍にpn接合が形成
されているが、上記の欠陥があれば、その部分で
異常拡散が起こり、正常なpn接合はできないの
は当然である。9.5×1017原子/立方センチメー
トルの酸素濃度のウエーハは表面に欠陥は観察さ
れなかつたが、内部にはゲツター効果のある酸素
の析出が行われたと考える。
Figure 2 shows a silicon wafer with a high oxygen concentration, i.e. 12.5 x 10 17 atoms/cm3.
This is an example of observing the defect distribution in the wafer cross section after heat treatment at 1000°C for 2 hours. In a wafer with such a high oxygen concentration, crystal defects are generated all the way to the surface, and if an integrated circuit is formed on the wafer surface under such conditions, the breakdown voltage characteristics of the gate oxide film mentioned above will clearly deteriorate in the MOS type. It is expected that In Figures 3 and 4, the oxygen concentration is 7.5.
x 10 17 atoms/cubic centimeter, wafer that is 9.5 x 10 17 atoms/cubic centimeter
This is an observation of defects on the wafer surface after heat treatment at 1100°C for 2 hours. In a wafer with a low oxygen concentration of 7.5×10 17 atoms/cm3,
Although micro defects are formed on the wafer surface as in the case of the oxygen concentration of 12.5×10 17 atoms/cm3, the nature of the defects is considered to be different. However, integrated circuits with good characteristics cannot be formed on a wafer surface that has defects. In the case of a bipolar type, a pn junction is formed near the wafer surface, but if there is any of the above defects, it is natural that abnormal diffusion will occur in that area and a normal pn junction will not be formed. Although no defects were observed on the surface of the wafer with an oxygen concentration of 9.5×10 17 atoms/cm3, it is thought that oxygen was precipitated inside with a getter effect.

添付図面の第1図はCZ法により得られた各種
酸素濃度の単結晶シリコンからなるデバイス基板
用ウエーハを、900〜1100℃の温度に加熱した後
の酸素減少量をプロツトしたものであつて、第1
図の横軸は単結晶シリコンの初期酸素含有量を、
また縦軸は上記熱プロセス後における含有酸素の
減少量をそれぞれ表わすものである。
Figure 1 of the attached drawings plots the amount of oxygen loss after heating device substrate wafers made of single crystal silicon with various oxygen concentrations obtained by the CZ method to temperatures of 900 to 1100°C. 1st
The horizontal axis of the figure is the initial oxygen content of single crystal silicon,
Moreover, the vertical axis represents the amount of decrease in the contained oxygen after the above-mentioned thermal process.

第1図から明らかなように、その酸素濃度が
8.5×1017原子/立方センチメートル未満のウエ
ーハでは熱プロセスを通じて酸素濃度の減少がほ
とんどみられず、これは欠陥が発生しないことを
意味し、これでは欠陥に基づくゲツター効果が期
待できない。一方酸素濃度が10.5×1017原子/立
方センチメートル以上の場合には過飽和の酸素が
ほとんどウエーハ表面に析出し、欠陥がウエーハ
全体にわたつて発生してこれがデバイスの特性を
極度に悪いものとしてしまう。しかしデバイス基
板の酸素濃度が17〜21ppmaの範囲内にある場合
には、酸素の析出が認められず所期のゲツター効
果が得られるのである。
As is clear from Figure 1, the oxygen concentration
Wafers with a size of less than 8.5×10 17 atoms/cubic centimeter show almost no decrease in oxygen concentration through thermal processing, which means that no defects are generated, and no defect-based getter effect can be expected. On the other hand, when the oxygen concentration is 10.5×10 17 atoms/cubic centimeter or more, most of the supersaturated oxygen is deposited on the wafer surface, and defects are generated throughout the wafer, resulting in extremely poor device characteristics. However, when the oxygen concentration of the device substrate is within the range of 17 to 21 ppma, no oxygen precipitation is observed and the desired getter effect can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は単結晶シリコンウエーハの熱プロセス
による酸素濃度の減少を表わすグラフ、第2図は
酸素濃度が12.5×1017原子/立方センチメートル
のシリコンウエーハを1000℃で2時間熱処理した
ときの断面の金属組織の顕微鏡写真、第3図は酸
素濃度が7.5×1017原子/立方センチメートルの
シリコンウエーハを1000℃で2時間熱処理したと
きの表面の金属組織の、aは200倍、bは400倍の
顕微鏡写真、第4図は酸素濃度が9.5×1017
子/立方センチメートルのシリコンウエーハを
1000℃で2時間熱処理したときの表面の金属組織
の、aは200倍、bは400倍の顕微鏡写真である。
Figure 1 is a graph showing the decrease in oxygen concentration due to thermal processing of single-crystal silicon wafers. Figure 2 is a cross-sectional view of a metal cross section of a silicon wafer with an oxygen concentration of 12.5 x 10 17 atoms/cm3 heat treated at 1000°C for 2 hours. Micrograph of the structure. Figure 3 is a micrograph of the metal structure on the surface of a silicon wafer with an oxygen concentration of 7.5 x 10 17 atoms/cubic centimeter heat-treated at 1000℃ for 2 hours, magnified 200x (a) and 400x (b) , Figure 4 shows a silicon wafer with an oxygen concentration of 9.5 x 10 17 atoms/cm3.
A is a 200x and b is a 400x micrograph of the surface metal structure after heat treatment at 1000°C for 2 hours.

Claims (1)

【特許請求の範囲】[Claims] 1 酸素濃度が8.5×1017〜10.5×1017原子/立方
センチメートルである半導体シリコンウエーハの
表面に、集積回路を900〜1200℃の温度条件下で
形成させることを特徴とする半導体電子装置の製
造方法。
1. A method for manufacturing a semiconductor electronic device, which comprises forming an integrated circuit on the surface of a semiconductor silicon wafer having an oxygen concentration of 8.5×10 17 to 10.5×10 17 atoms/cubic centimeter at a temperature of 900 to 1200°C. .
JP12411882A 1982-07-16 1982-07-16 Single crystal silicon for device base Granted JPS5918198A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12411882A JPS5918198A (en) 1982-07-16 1982-07-16 Single crystal silicon for device base

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12411882A JPS5918198A (en) 1982-07-16 1982-07-16 Single crystal silicon for device base

Publications (2)

Publication Number Publication Date
JPS5918198A JPS5918198A (en) 1984-01-30
JPH0339998B2 true JPH0339998B2 (en) 1991-06-17

Family

ID=14877364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12411882A Granted JPS5918198A (en) 1982-07-16 1982-07-16 Single crystal silicon for device base

Country Status (1)

Country Link
JP (1) JPS5918198A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3624827B2 (en) * 2000-12-20 2005-03-02 三菱住友シリコン株式会社 Method for producing silicon single crystal

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4118303A (en) * 1976-08-30 1978-10-03 Burroughs Corporation Apparatus for chemically treating a single side of a workpiece
JPS5857724B2 (en) * 1979-07-24 1983-12-21 日本電信電話株式会社 Optical signal connection device

Also Published As

Publication number Publication date
JPS5918198A (en) 1984-01-30

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