JPH0340400B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of forming a musical sound waveform for an electronic musical instrument, and more particularly to an improvement in a method of forming a musical sound waveform based on read values of a waveform memory in which a musical sound waveform is stored as a plurality of sample point amplitude values. Technical Background of the Invention A musical sound waveform is stored in a waveform memory as a plurality of sample point amplitude values, and the stored waveform is repeatedly read out using an address signal that changes at a frequency corresponding to the pitch of the musical sound to be generated. The musical sound waveform forming method for an electronic musical instrument is as follows.
Various so-called "waveform memory methods" have been proposed. By the way, one of the important issues in such a waveform memory type musical waveform forming method is as follows.
The problem is how to obtain smoothly changing tone waveforms by storing a small number of sample point amplitude values. To solve this problem, various techniques have been proposed to interpolate between adjacent sample point amplitude values, but all of them target waveform memory that stores the entire waveform period as multiple sample point amplitude values. That's what I'm saying. Therefore, although it is possible to reduce the capacity of the waveform memory to some extent by adopting interpolation technology, it is still necessary to store a large number of sample point amplitude values for one cycle of the musical waveform, so the capacity of the waveform memory is quite large. I had to use one. OBJECTS OF THE INVENTION It is an object of the present invention to provide a musical sound waveform forming method for an electronic musical instrument, which greatly reduces the number of sample point amplitude values stored in a waveform memory and allows a sufficiently smooth waveform to be obtained. Summary of the Invention In the present invention, a plurality of sample point amplitude values of a positive or negative half waveform of a musical sound waveform are stored in a waveform memory, and each sample point amplitude value is read out bidirectionally. A method is adopted in which a tone waveform is formed by suitably reversing the sign (positive or negative polarity) of the sample point amplitude value read out (read out) as the direction is reversed. A tone waveform is then formed by interpolating between the read values based on the amplitude values of adjacent sample points. However, when the reading direction of the waveform memory is reversed, interpolation is performed between read values having different signs based on the same sample point amplitude value. In one embodiment of the present invention, the waveform memory includes a first memory that stores even-numbered sample point amplitude values among the sample point amplitude values at each address;
and a second memory that stores odd-numbered sample point amplitude values at each address. For example, if we consider a configuration in which the positive half waveform of a sine wave musical waveform is stored as 16 sample point amplitude values, the waveform memory will store 16 sample point amplitude values as shown in Figure 1a. Therefore, the even-numbered sample point amplitude values X0, X2, . . . , X14 indicated by solid lines in FIG. X15 is stored in the second memory. Interpolation is then performed between adjacent sample point amplitude values, that is, between the read values of the first memory and the read values of the second memory. The interpolation adopted here is, for example, linear interpolation, and the state of this interpolation is shown in FIG. 1b. That is, the read values X( _R ) and X( _R+
1 ) is interpolated between each readout value of the waveform memory by linearly approximating and calculating each value on this straight line, for example, P ₁ , P ₂ , P ₃ as appropriate.
According to such a configuration, between the read value of the first memory and the read value of the second memory, between the read value of the second memory and the next read value of the first memory, and so on. Interpolation is performed sequentially, with the read values of the first memory and the read values of the second memory being alternate starting points, but if this operation is simply repeated, the following problems will occur when the read direction of the waveform memory is reversed. occurs. That is, after reading the amplitude value X15 of the 15th sample point from the second memory, the amplitude value X1 of the 14th sample point is read from the first memory.
The value 14 obtained by inverting the sign of 4 is read out, and interpolation is performed between the value X15 and the value 14 as shown in FIG. 1c. Therefore, the smoothness of the musical sound waveform formed in this portion will be lost. Similarly, the waveform memory is read in the opposite direction, and the value 0 obtained by inverting the sign of the amplitude value X0 of the 0th sample point is read from the first memory. Next, the amplitude value X1 of the first sample point is read from the second memory.
As a result, the smoothness of the tone waveform formed in this portion is also lost. Therefore, in the present invention, when the reading direction of the waveform memory is reversed as described above, interpolation is performed between read values having different signs based on the same sample point amplitude value. For example,
When the reading direction is reversed from the 15th sample point to the 14th sample point, the value X15 read from the second memory and the value 15 obtained by reversing the sign of this value In addition, when reversing the reading direction from the 0th sample point to go to the 1st sample point, the value 0 is obtained by inverting the sign of the value X0 read from the first memory. It is configured to interpolate between the value X0 and the value X0. That is, when the reading direction of the waveform memory is reversed, interpolation is performed between read values having different signs regarding the same sample point. Furthermore, according to the method of this invention, the amplitude value is 0.
is not stored in waveform memory. That is, the amplitude value is 0
is formed by interpolation between identical read values with different signs. Embodiments of the Invention Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. 2 shows an example of an electronic musical instrument to which the musical sound waveform forming method according to the present invention is applied.
This electronic musical instrument is capable of producing multiple tones at the same time, and the key switch circuit 1 includes a plurality of key switches that operate in response to the pressing of each key on a keyboard (not shown), and the operating status of these key switches is Detected by key assigner 2. The key assigner 2 determines which key or keys are being pressed (the sound of the key to be sounded) based on the detection of the operating state of each key switch in the key switch circuit 1, and forms a key code KC that identifies the sound of this key. , an operation is performed in which each of these key codes KC is assigned to one of a plurality of sounding channels that can be sounded simultaneously. Key assigner 2 sends a key code KC based on the above assignment and a key-on signal KON indicating whether or not the key corresponding to this key code KC is being pressed.
is output. The key code KC and key-on signal KON are outputted in a time-division manner for each sound generation channel. The key code KC is composed of a note code NC for identifying 12 note names and an octave code OC for identifying, for example, a 5-octave range, using a 4-bit digital code and a 3-bit digital code, respectively. Can be configured. Of the key codes KC output from the key assigner 2, the note code NC is added to the address generator 3. In response to the added note code NC, the address generator 3 generates an address signal corresponding to the frequency of the note in the lowest octave among the notes indicated by the note code. This address signal consists of 8-bit signals A0 to A7, of which the upper 6 bits are the signal A2.
~A7 corresponds to the frequency of the above-mentioned lowest octave sound. More precisely, in an embodiment of the present invention that will be explained later in connection with this electronic musical instrument, one musical waveform is represented by 64 sample point amplitude values, and 32 sample point amplitude values corresponding to half the waveform are stored in the waveform memory. Since the frequency of the sound in the lowest octave is _M , the address signal A0~
Signals A2-A7 of the upper 6 bits of A7 change at a speed of _64M , and the address signals A0-A7 as a whole change at a speed of _4.times.64M . The address signals A0 to A7 are also output in a time-division manner synchronized with the sound generation channel. Address signals A0 to A7 generated from the address generator 3 in response to the note code NC are applied to the shifter 4. The shifter 4 also has an octave code OC of the key code KC output from the key assigner 2.
has been added. The shifter 4 shifts address signals A0 to A7 corresponding to the lowest octave tone of each note generated from the address generator 3 in accordance with the octave code OC, thereby generating an address data signal AD0 having a frequency corresponding to the tone to be generated. ~ forms AD7. For example, address signal A0 generated from address generator 3
-A7 corresponds to the C note of the first octave, and the octave code OC indicates the second octave.The shifter 4 operates to shift the address signals A0-A7 by 1 bit to the upper side. Address data signals AD0 to AD7 corresponding to two octaves of C note are formed. These address data signals AD0 to AD7 are applied to tone generator 5. The structure of the tone generator 5 is the same as that of this invention, and its details are shown in FIG. In FIG. 3, musical waveforms to be generated are stored in an even waveform memory 501 and an odd waveform memory 502. To store a musical sound waveform in the even waveform memory 501 and the odd waveform memory 502, one period of a predetermined musical sound waveform is extracted with 64 sample point amplitude values, and positive amplitude values (from X0 to The even-numbered waveform memory 501 stores the even-numbered sample point amplitude values X0, X2, X4, . . . of the sample point amplitude values X0 to X31.
X30 is stored, and the odd-numbered sample point amplitude values X1, X3, X5...X are stored in the odd-numbered waveform memory 502.
31 is stored. The circuit consisting of the exclusive OR gate group 503, the adder 504, and the circuit consisting of the exclusive OR gate group 505 have mutually different phases based on the address data signals AD2 to AD7 applied from the shifter 4, and the waveform memories 501 and 502 are bidirectional. two address signals, namely a first address signal AS1 and a second address signal AS
form 2. The first address signal AS1 and the second address signal AS2 are transmitted to the waveform memory 501,
When the read direction of 502 is reversed, the selector 50
6,507, the even number waveform memory 5
01, is added to the odd waveform memory 502. Further, an exclusive OR gate group 508 and an adder 5 are provided on the output sides of the waveform memories 501 and 502, respectively.
09 circuit and exclusive OR gate group 51
0 and an adder 511 are for inverting the signs of the read values of the waveform memories 501 and 502 (converting them into complementary numbers indicating negative values). Arithmetic control data generation circuit 512 and arithmetic circuit 51
3 forms interpolated data, the details of which are shown in FIGS. 5 and 6. First, the operation of forming the first address signal AS1 and the second address signal AS2 will be explained.
The first and second address signals AS1 and AS2 are signals AD of the upper 6 bits of the address data signals AD0 to AD7 applied from the shifter 4 in FIG.
2 to AD7. The upper 6-bit signals AD2 to AD7 are shown in Fig. 4 a to f.
As shown in the figure, the value repeatedly changes from 0 to 63 in decimal notation, and its cycle corresponds to the pitch (frequency) of the musical note to be produced. In other words, if the frequency of the musical tone to be sounded is _O , the signals AD2 to AD7 are the speed
64 _O , and this unit change time is 1/64 _O (corresponding to the readout time interval of each sample point)
is hereinafter referred to as the read unit time. Among the signals AD2 to AD7, the signals AD3 to AD6 of the upper four bits excluding the most significant bit are respectively applied to one input of each exclusive OR gate of the exclusive OR gate group 503, and the signal AD7 of the most significant bit is applied to the other input of each exclusive OR gate. Commonly added to input. Then, the first address signals AS1, AS11 to AS are generated by a total of 5 bits of the signal AD7 of the most significant bit and the output signal of each exclusive OR gate.
15 is formed. Further, among the signals AD2 to AD7, the higher 5 bits of the signals AD3 to AD7 are added to the adder 504,
Signal AD2 is applied to the carry input of adder 504. Therefore, the adder 504 receives the signal AD3~
The contents of signal AD2 will be added to the value of AD7. The output signal of this adder 504, except for the most significant bit, is applied to one input of each exclusive OR gate of the exclusive OR gate group 505, and the output signal of the most significant bit is commonly applied to the other input of each of the exclusive OR gates. It will be done. and adder 504
A total of 5 bits of signals, including the most significant bit output signal of the
address signals AS2, AS21 to AS25 are formed. The above first address signals AS1, AS11 to AS
15 and second address signals AS2, AS21~
Table 1 shows AS25 in relation to signals AD2 to AD7 of the upper six bits of address data signals AD0 to AD7.

[Table] Also, the designated addresses of the first address signal AS1 and the second address signal AS2 are set to the signals AD2~
A timing chart based on the relationship with AD7 is shown in Figure 4 g and h. In addition, Figure 4g,
The numbers with bars in h indicate addresses when the reading direction is reversed. That is, the first address signal AS1 and the second address signal AS
2 change at half the speed of the signals AD2 to AD7, and the phase of the second address signal AS2 is shifted by the read unit time compared to the first address signal AS1. The first one like this
The address signal AS1 of selector 506, 507
The second address signal AS2 is applied to the B inputs of selectors 506 and 507, respectively. The selectors 506 and 507 select and output either the signal applied to the A input or the signal applied to the B input, respectively, and this selection control is performed by AND circuits A1 and A2 and an exclusive OR circuit.
It is controlled by the signal SS generated by EX1. This signal SS is expressed by a logical formula: SS=AD1, AD2, AD3, AD4, AD5,
It becomes AD6AD7. That is, the signal SS falls at the center of the period in which the signals AD2 to AD7 take the value 63, and rises at the center of the period in which the signals AD2 to AD7 take the value 31, as shown in FIG. 4i. This signal SS is directly connected to the A input selection terminal of the selector 506.
SA and the B input selection terminal SB of the selector 507, and the inverter IN
1 and IN2 are inverted, respectively, and the selector 506
is applied to the B input selection terminal SB of the selector 507, and also applied to the A input selection terminal SA of the selector 507. Therefore, the selector 506 indicates that the signal SS is "1".
the first address signal applied to the A input during
AS1 is selected, and during "0", the second address signal AS2 applied to the B input is selected. Further, the selector 507 selects the second address signal AS2 to be applied to the B input while the signal SS is "1",
During "0", the first address signal AS1 applied to the A input is selected. Signals AS11 to AS14 or AS of the lower 4 bits of the address signal AS1 or AS2 selected by the selector 506
21 to AS24 are added to the even waveform memory 501 as read address signals, and the most significant bit signal AE5, AS15 or AS25 is added to make the value read from the even waveform memory 501 into a value with the sign reversed in complement form. is added to the carry input C _i of the device 509 . Similarly, of the address signal AS2 or AS1 selected by the selector 507, the lower 4 bits of the signal AS21 to AS24 or
AS11 to AS14 are added to the odd waveform memory 502 as read address signals, and the most significant bit signal AO5, AS25 or AS15 is added to make the value read from the odd waveform memory 502 a value with the sign inverted in complement form. It is added to the container 511. As described above, the even waveform memory 501 stores the amplitude values X0,
2, X4...X30 are stored in each address,
In addition, the odd waveform memory 502 stores the amplitude values X1, X3, X5... . The value read from the even waveform memory 501 is added to the arithmetic circuit 513 via an exclusive OR circuit group 508 and an adder 509. Here, if the signal AE5 of the most significant bit of the address signal selected by the selector 506 is "0", no processing is performed in the exclusive OR circuit group 508 and the adder 509, and the read value of the even waveform memory 501 is is added to the arithmetic circuit 513 as is. But signal AE5
is “1”, each bit output of the even waveform memory 501 is inverted in the exclusive OR gate group 508, and “1” is added to the value of this inverted signal in the adder 5.
09 and is added to the arithmetic circuit 513 as a negative value in complement form. Similarly, when the signal AO5 of the most significant bit of the address signal selected by the selector 507 is "0", the circuit consisting of the exclusive OR gate group 510 and the adder 511 directly inputs the read value of the odd waveform memory 502 to the arithmetic circuit 513. In addition, in the case of "1", the read value of the odd waveform memory 502 is applied to the arithmetic circuit 513 with its sign inverted in complement form. The arithmetic circuit 513 receives control data X1, E2, E4, O2, O4 generated from the outputs of the adders 509 and 511 and the arithmetic control data generation circuit 512.
Based on this, interpolation calculations are performed between the amplitude values of each sample point stored in the even waveform memory 501 and the odd waveform memory 502. This interpolation calculation is normally performed between a value based on the read value of the even waveform memory 501 and a value based on the read value of the odd waveform memory 502, but when the read direction of the even waveform memory 501 and the odd waveform memory 502 is reversed, Interpolation is performed between values of different signs based on the read value of a single memory, either the even waveform memory 501 or the odd waveform memory 502. The arrow shown between j and k in FIG. 4 shows this interpolation. i.e. signal
When the value indicated by AD2 to AD7 is 0, even number waveform memory 501 is addressed to address 0, and memory 5
The memory value EV0 (corresponding to the sample point amplitude value X0) at address 0 of 01 is read out and stored in the odd waveform memory 502.
Similarly, address 0 is addressed, and the value OD0 (corresponding to the sample point amplitude value
An interpolation operation leading to 0 is performed. Next, signal AD2~
When the value indicated by AD7 is 1, even waveform memory 50
1 is addressed at address 1, and the odd waveform memory 502 is addressed at address 0 in the same way as above, and an interpolation calculation is performed starting from the value OD0 and reaching the stored value EV1 (corresponding to the sample point amplitude value X2) at address 1 in the memory 501. . Similarly, when the value indicated by the signals AD2 to AD7 is 2, the even waveform memory 501 and the odd waveform memory 502 are addressed to address 1, and the stored value EV1 at address 1 of the even waveform memory 501 is the starting point, and the odd waveform memory 502 Memory value OD1 of address 1
(corresponding to sample point amplitude value X3) is performed. The interpolation operation is repeated in the same way, and the signal
When the value indicated by AD2 to AD7 reaches 31, the address signals applied to the memories 501 and 502 are switched in the middle of that period, and in this period, the read value OD15 at address 15 of the odd waveform memory 502 is the starting point, and the read value is Negative value based on value OD15
Interpolation is performed to reach OD15. Subsequently, interpolation is performed starting from the negative value 15 based on the read value OD15 at address 15 of the odd waveform memory 502 to the negative value 15 based on the read value EV15 at address 15 of the even waveform memory 501. The same operation is repeated thereafter, and when the value indicated by the signals AD2 to AD7 reaches 63, the read address signals of the memories 501 and 502 are switched again at the center of the period, so that the even waveform memory 501 is Starting from a negative value 0 based on the read value EV0 at the 0th address, interpolation is performed to reach the read value EV0. The above interpolation is performed by linear interpolation that interpolates three interpolation points. Figures 7a-d show four typical examples of the above interpolation. FIG. 7a shows an example of interpolation starting from the value EV based on the read value of the even waveform memory 501 and reaching the read value OD of the odd waveform memory 502. The values of interpolation points P1, P2, and P3 resulting from this interpolation can be determined by the following calculation. P1=OD-EV/4+EV (1) P2=2(OD-EV)/4+EV (2) P3=3(OD-EV)/4+EV (3) By the way, formula (1) is P1=(OD/4+EV/ 4) × 1 + EV / 4 × 2 (4), formula (2) can be transformed as P2 = OD / 4 × 2 + EV / 4 × 2 (5), and formula (3) can be transformed as P3 = (OD / It can be transformed as 4+EV/4)×1+OD/4×2 (6). Also, it is expressed as EV=EV/4×4 (7). Therefore, if the stored value (EV) of the even waveform memory 501 corresponds to EV/4, and the stored value (OD) of the odd waveform memory 502 corresponds to OD/4, then the starting point P0 ( EV) and the three interpolation points P1, P2, P3 can be obtained by the following calculation. P0=EV×4 (8) P1=(OD+EV)×1+EV×2 (9) P2=OD×2+EV×2 (10) P3=(OD+EV)×1+OD×2 (11) Here, calculate EV×4. The command finger is E4,
X1 is the signal that commands calculation (OD + EV) x 1, E2 is the signal that commands calculation EV x 2, calculation OD x 2
Assuming that the command signal is O2, the calculation for the starting point P0 and the three interpolation points P1, P2, P3 will give the command signals shown in Table 2, and if two calculations are commanded at the same time, those calculations will be It turns out that all you have to do is add up the results.

[Table] Figure 7b shows the read value of the odd waveform memory 502.
Starting from OD, read value of even number memory 501
This shows an example of interpolation leading to EV. In this case as well, the same thing as explained in Fig. 7a holds true, and in addition to the definition of the command signal above,
Assuming that the signal for commanding is O4, in the case of Fig. 7b, the starting point P0 and the three interpolation points P1, P2, P
It can be seen that the calculation for obtaining 3 can be performed by giving a command signal as shown in Table 3.

[Table] Figure 7c shows the read value of the odd waveform memory 502.
The value obtained by starting from OD and reversing the sign of the read value OD.
This shows the case of interpolation leading to OD, and the signal
This corresponds to the case where the value indicated by AD2 to AD7 is 31.
In this case, each interpolation point P1, P2, P3 can be obtained as P1=OD/4×2 (12) P2=0 (13) P3=−OD/4×2 (14), and in this case is point P2
Since the sign of the read value is inverted after the fourth
It can be seen that it is sufficient to give command signals as shown in the table.

[Table] Also, FIG. 7d shows a case in which the starting point is a value obtained by inverting the sign of the read value EV of the even waveform memory 501, and interpolation is performed to reach the read value EV, and the values indicated by the signals AD2 to AD7 are Corresponds to case 63.
In this case, the same thing as explained in FIG. 7c holds true. That is, in this case, command signals as shown in Table 5 may be given.

[Table] The arithmetic control data generation circuit 512 generates command signals X1, E2, E4, O2, and O4 in each of the above cases. Details of this arithmetic control data generation circuit 512 are shown in FIG. The arithmetic control data generation circuit 512 includes 11 AND circuits A5
~A15 and two OR circuits OR1 and OR2, and input signals AD0, AD1, AD2',
Command signals X1, E2, E based on PTM, MTP
4, O2, and O4 are generated. Here signal AD0,
AD1 is shown in Figure 4l and m, respectively, and the signal
AD2' is the exclusive OR condition of the signal AD7 and the signal AD2 determined by the exclusive OR circuit EX2, as shown in FIG. 4n. Note that the signal AD2' indicates which reading value from the even waveform memory 501 or the odd waveform memory 502 is used as the starting point for interpolation, and the relationship between the signal AD2' and the direction of interpolation is shown in Table 6. become that way.

[Table] Furthermore, the signal PTM is formed by AND circuits A1, A3 and inverter IN3, and the signal MTP is formed by AND circuits A1, A4, which are expressed by the following logical formulas. PTM=AD2・AD3・AD4・AD5・AD6・7 MTP=AD2・AD3・AD4・AD5・AD6・AD7 These signals PTM and MTP are respectively shown in Figure 4 o+
It is shown in p. The manner in which the signals X1, E2, E4, O2, and O4 are generated from the arithmetic control data generating circuit 512 consists of four patterns, and each pattern corresponds to Tables 2 to 5 above. Listing each pattern is as follows. 1 AD2'=0 PTM=0 MTP=0 E4→X1, E2→E2, O2→X1, O2 2 AD2'=1 PTM=0 MTP=0 O4→X1, O2→E2, O2→X1, E2 3 AD2 '=0 PTM=1 MTP=0 O4→O2→0→O2 4 AD2'=0 PTM=0 MTP=1 E4→E2→0→E2 The above relationship is shown in a timing chart as shown in Figure 4q.
It becomes like ~u. The arithmetic circuit 513 performs predetermined arithmetic operations based on the outputs of the adders 509 and 511 and the signals X1, E2, E4, O2, and O4 output from the arithmetic control data generation circuit 512, the details of which are shown in FIG. shown. This circuit 513 is an AND gate group 5
14,515, OR gate groups 516,517, and adders 518,519,520. First, a case will be described in which among the signals X1 to O4 generated from the arithmetic control data generation circuit 512, only E4 is "1" and all the others are "0". In this case, the AND gate group 514 and the OR gate group 516 select a signal obtained by shifting the output of the adder 509 by 2 bits to the upper bit side (to the right), and this signal is applied to the A inputs A3 to A8 of the adder 518, Adder 520 via A inputs A3 to A8 of adder 520
It is sent out from the addition outputs S, S3 to S8. In this case, the calculation of EV×4 is performed. Similarly, if only the signal O4 is "1", the AND gate group 515 and the OR gate group 517 select a signal obtained by shifting the output of the adder 511 by 2 bits to the upper bit side, and this signal is used by the adder 519. A inputs A3 to A8, A inputs A3 to A8 of adder 520
Addition output S, S3~ of adder 520 via A8
It is sent from S8. In this case, the calculation of OD×4 has been performed. Further, if only the signals X1 and E2 are "1", the AND gate group 514 and the OR gate group 516
selects the output of adder 509 and a signal obtained by shifting this output by one bit to the upper bit side, and the unshifted signal is selected as B input B of adder 518.
The signal shifted by 1 bit from 1 to B6 is sent to adder 5.
It is applied to 18 A inputs A2 to A7, respectively.
The adder 518 combines the signal added to the B input and the A
The signals applied to the inputs are summed and applied to the A input of adder 520. Furthermore, the AND gate group 515 and the OR gate group 517 select the unshifted signal of the adder 511 and input it to the B input B1 of the adder 519.
B inputs B1 to B6 of adder 520 via ~B6
Add to. The adder 520 adds the signal applied to the A input and the signal applied to the B input, and sends this out from the addition output S. That is, in this case, the calculation (EV+OD)×1+EV×2 has been performed. Similarly, when only the signals X1 and O2 are "1", the output of adder 509 is added to the A input of adder 520 via the B input of adder 518, and the output of adder 511 and this output are added to the upper The signals shifted one bit in bit order are added in an adder 519 and then applied to the B input of an adder 520. That is, the calculation (EV+OD)×1+OD×2 will be performed. Furthermore, when only the signals E2 and O2 are "1", a signal obtained by shifting the output of the adder 509 by one bit to the higher bit side is selected by the AND gate group 514 and the OR gate group 516, and is sent via the A input of the adder 518. A signal obtained by shifting the output of the adder 511 by one bit to the higher bit side is selected by the AND gate group 515 and the OR gate group 517, and is applied to the A input of the adder 519.
is applied to the B input of adder 520 via the input. Then, both signals are added by an adder 520 and sent out from the addition output S. In other words, EV×2+
This means that the calculation of OD×2 has been performed. Moreover, when only the signal E2 is "1", the adder 5
The signal obtained by shifting the output of 09 by 1 bit to the upper bit side is the AND gate group 514 and the OR gate group 51.
6 and sent via the A input of adder 518 and the A input of adder 520. That is, the calculation of EV×2 is performed. Similarly, when only the signal O2 is "1", a signal obtained by shifting the output of the adder 511 by 1 bit to the upper bit side is selected by the AND gate group 515 and the OR gate group 517, and the A input of the adder 519, 520 via the B input. That is, the calculation of OV×2 is performed. The calculation circuit 513 is the calculation control data generation circuit 51
One of the above calculations is performed in response to the signals X1 to O4 generated from 2, and a signal indicating the interpolated amplitude value of each sample point is sequentially output. The circuit shown in FIG. 3 including the arithmetic circuit 513 operates in a time-division manner for each channel because the address data signals AD0 to AD7 are supplied to each channel in a time-division manner, and the arithmetic circuit 513 receives sample point amplitude values for each channel. The signals shown are output in a time-division manner. The output of this arithmetic circuit 513 (tone generator 5
output) is applied to the multiplier 7 shown in FIG. An envelope signal EVS generated for each channel from an envelope generator 6 in response to the key-on signal KON output from the key assigner 2 is added to the multiplier 7.
The multiplier 7 multiplies the signal representing the amplitude value of each sample point generated by the tone generator 5 by the envelope signal EVS, and performs amplitude control for each channel in accordance with the key depression. The signal whose amplitude has been controlled by the multiplier 7 is applied to the accumulator 8, where the values of each channel are summed, and then applied to the D/A converter 9, where it is converted into an analog signal, and then sent to the sound system 10 for sound generation.
supplied to In the above embodiment, two memories, the even waveform memory 501 and the odd waveform memory 502, are used to store the positive half waveform of the musical sound waveform, and when the reading direction is reversed, the read values of the same memory are Although the configuration has been described so as to perform interpolation calculations, a similar configuration can be made using a single memory. In this case, when the reading direction is reversed, an interpolation operation may be performed between two values having different signs based on the stored value at the same address. Further, the waveform stored in the waveform memory is not limited to a sine wave, but any waveform that has symmetry may be used. Furthermore, in the above embodiment, when the octave is high, the least significant bit or the lower two bits of the address data signal applied to the tone generator 5 may always be 0. As a result, the number of interpolation steps decreases, but since the fundamental frequency is sufficiently high in high octaves, this has little effect on the timbre. Effects of the Invention As explained above, according to the present invention, the number of sample point amplitude values stored in the waveform memory can be significantly reduced, so the waveform memory can be configured using a small-capacity memory. Furthermore, a smooth musical sound waveform with few noise components can be obtained.

[Brief explanation of drawings]

Fig. 1 is a graph for explaining this invention, Fig. 2 is a block diagram showing an embodiment of an electronic musical instrument to which this invention is applied, and Fig. 3 is a block diagram showing an embodiment of the main part of this invention. , FIG. 4 is a timing chart explaining the operation of the circuit in FIG. 3, FIG. 5 is a circuit diagram showing a detailed configuration example of the arithmetic control data generation circuit shown in FIG. 3, and FIG. FIG. 7 is a circuit diagram showing a detailed configuration example of the illustrated arithmetic circuit, and is a graph explaining the interpolation operation according to the present invention. 1...Key switch circuit, 2...Key assigner, 3
... Address generator, 4... Shifter, 5... Tone generator, 6... Envelope generator, 7... Multiplier, 8... Accumulator,
9... D/A converter, 10... Sound system, 501... Even number waveform memory, 502... Odd number waveform memory, 512... Arithmetic control data generation circuit, 51
3... Arithmetic circuit.

Claims (1)

[Claims] 1. A plurality of sample point amplitude values in a positive or negative half waveform of a musical sound waveform are stored in a waveform memory, and the signs of each sample point amplitude value stored in the waveform memory are mutually inverted in both directions. In a musical sound waveform forming method for an electronic musical instrument, in which a desired musical sound waveform is obtained by sequentially reading out the reading values and appropriately interpolating between the read values, the amplitude value of the even-numbered sample point stored in the waveform memory is Sequentially interpolating between the original read value and the read value based on the odd-numbered sample point amplitude value, and when reversing the read direction of the waveform memory, interpolate between read values with different signs based on the same sample point amplitude value. A method for forming a musical sound waveform for an electronic musical instrument, characterized in that: 2. The waveform memory includes a first memory that stores even-numbered sample point amplitude values among the sample points at each address, and a second memory that stores odd-numbered sample point amplitude values at each address. The interpolation is performed between the read value of the first memory and the read value of the second memory, and when the read direction is reversed, the interpolation is performed between the read values of the same memory with different signs. A musical sound waveform forming method for an electronic musical instrument according to claim 1. 3. The first memory and the second memory are addressed by address signals that change over a predetermined time as a unit time, and changes in the respective address signals are shifted from each other by 1/2 of the unit time. , furthermore, the direction of the shift is switched each time the reading direction of the waveform memory is reversed, and the interpolation is performed every 1/2 period of the unit time synchronized with the address signal. A musical sound waveform forming method for an electronic musical instrument according to scope 2. 4. Of the N-bit binary digital signal in which the value of the signal of the upper n bits changes at a speed corresponding to the frequency of the musical tone to be generated, the signal of the upper n bits is used as a first address signal, and the signal of the upper n bits is set as a first address signal. A signal obtained by adding the contents of the (n+1)th bit from the higher order to the signal is used as a second address signal, and the first address signal and the second address signal are alternately switched when the reading direction is reversed to obtain the first address signal. 3. The musical sound waveform forming method for an electronic musical instrument according to claim 2, wherein the sound waveform is added alternately to the memory and the second memory.