JPH0340416B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an input/output control device that controls the flow of data between a plurality of central processing units and a plurality of input/output devices, and particularly relates to an input/output control device that controls the flow of data between a plurality of central processing units and a plurality of input/output devices. The present invention relates to an input/output control device that optimally controls a start signal.

Generally, in modern computer systems, a central processing unit (hereinafter referred to as CPU) checks whether an external asynchronous event has occurred each time each program instruction is executed, and if no external asynchronous event has occurred, the next instruction is executed. An interrupt mechanism is provided that executes the interrupt according to the logic of the program and transfers control to a specific address if an interrupt occurs.

Interrupt control is normally performed when an interrupt cause occurs.
This causes a forced transfer of control that is different from the progress of the program's logic, ie, transfer of control to a high-priority control program.

However, depending on the content of the interrupt cause, it may not necessarily be a high priority one; for example, an interrupt to report the end of a program instruction to the CPU, etc. There are things to do.

On the other hand, as computer systems become faster and larger, CPUs with fast calculation speeds are developed and put into practical use, and when these are combined into a complex computer system, a CPU with fast calculation speeds and a CPU with relatively slow calculation speeds are used. This results in an extreme imbalance in instruction processing time with the CPU.

When performing interrupt control in such a system, there is a demand for the development of an input/output control device that corrects these imbalances and performs optimized interrupt control.

[Conventional technology]

FIG. 3 shows a block diagram of a compound computer system that performs multiple processing.

In the system shown in FIG. 3, for example, a plurality of input/output devices 3a to 3n (hereinafter referred to as IODs 3a to 3n)
) for the host device 1a (for example,
In order to execute input/output commands from (CPU) via path 2a and report the completion of execution to the host device 1a, the corresponding IODs 3a to 3n, e.g.
The status interrupt from 3a is sent to input/output device 2.
(hereinafter referred to as IOC2) has traditionally been processed using the following two methods.

That is, the interrupt status from the IOD 3a is transmitted via the control unit 6 to the interrupt instruction circuit 7 and the startup priority instruction circuit 8.
, the startup priority instruction circuit 8 passes the preset signal S1=1 (startup priority signal) to the path 2a.
The signal is output to the activation determination circuit 4a.

At the same time, the interrupt instruction circuit 7
sends an interrupt instruction signal to a and activation determination circuit 4b,
The interrupt generation circuit 5a sends a request in to the host device 1a, and the activation determination circuit 4b reports to the host device 1b that IOC2 is in use.
Interrupt processing is executed.

(1): However, if the host device 1b continues to activate the path 2b after the interrupt status has occurred, the IOC 2 will give priority to activation because the signal output to the activation determination circuit 4a is S1 = 1. Since it is a signal, request-in processing is put on standby, and start-up processing is prioritized.

(2): On the other hand, when the signal preset in the startup priority instruction circuit 8 is S1=0 (interrupt priority signal), if a startup' is applied from the host device 1b,
Since the signal output to the activation determination circuit 4a is S1=0, IOC2 is in use.
The activation determination circuit 4b outputs this, and at the same time, requests from the interrupt generation circuit 5a are processed with priority.

[Problem that the invention seeks to solve]

In the two examples of conventional methods described above, in the case of outputting using method (1), for example, in the complex system shown in FIG. When the frequency of input/output commands from the host device 1b is high, the input/output command commands from the host device 1b are always processed with priority, so that a case may occur in which the interrupt status processing for the host device 1a does not proceed.

Furthermore, when processing using method (2), there were problems such as multiprocessing not progressing as expected.

That is, there was a problem in uniformly deciding which method (1) or (2) to use depending on the type of interrupt status.

[Means for solving problems]

It is an object of the present invention to realize a new input/output control device that solves the above-mentioned problems. The problem is solved by an input/output control device according to the present invention, which is provided and controls the flow of data between the plurality of host devices and the plurality of input/output devices by the priority selection means.

[Effect]

That is, when the input/output control device holds the interrupt status from a predetermined input/output device, either a means for prioritizing activation of the input/output device by an input/output command from a host device or a means for prioritizing the interrupt is provided. Using a startup/interrupt priority selection circuit that prioritizes selection at predetermined intervals, performs optimal status interrupt processing when an input/output control device is shared by a complex system, making the processing capacity of the complex system more efficient and appropriate. I tried to do this.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 and 2.

FIG. 1 shows a complex system having an input/output control device according to the present invention, A is a block diagram of the complex system, B is an embodiment of the activation/interrupt priority selection circuit according to the present invention, and C is a diagram of the complex system according to the present invention. FIG. 2 shows a time chart of the priority selection circuit and a flow chart of the input/output control device according to the present invention. The same symbols indicate the same objects or contents throughout the figures.

T1 shown in Figure 1B and C is the interrupt priority signal S1
=0 output section, T2 is activation priority signal S1=
1 output section is shown. Further, it is assumed that the ratio between the T1 output section and the T2 section is not a constant ratio, but cycles in a range of about 1:1 to 1:10 with a constant fluctuation period.

Note that T0 in FIG. 1B is a clock signal generated within the IOC2, and the numerical values in FIG. 1C indicate an example of the ratio between the T1 output section and the T2 output section. Next, it is assumed that 1:6 and 1:7 are sequentially circulated.

The activation/interrupt priority selection circuit 9 operates as follows. That is, the logic array 11 generates a ratio signal that is sequentially circulated from the output signal of the counter 10, and the decoder 12 outputs this output as the T1 signal and T2 signal to the activation determination circuits 4a and 4b.

Next, this embodiment will be explained based on the flow chart of FIG.

The area (a) in FIG. 2 is the operation area of the activation/interrupt priority selection circuit 9, and the area (b) is the operation area of the activation/interrupt priority selection circuit 9.
b. Operating area of interrupt generation circuits 5a and 5b; (c) is
(d) shows the set while IOC2 is in use, (d) shows the interrupt acceptance sequence, and (e) shows the startup acceptance sequence.

(ST-1): For example, when an interrupt signal is generated from the IOD3a to the IOC2, the control unit 6 determines whether the state of the activation/interrupt priority selection circuit 9 is in the T1 output section or T1.
Check whether it is in the 2 output section.

(ST-2): If it is T1 section, go to (ST-3), T
If it is a 2-output section, proceed to (ST-6).

(ST-3): Set the T1 signal and the interrupt signal to the activation determination circuit 4a in the path 2a (in the case of an interrupt to the host device 1a).

In addition, start for IOC2 from a path other than path 2a'
If so, the interrupt instruction circuit 7 causes the activation determination circuit 4b to display an indication that the IOC 2 is in use, and rejects the activation.

(ST-4): If there is activation from a path other than path 2a where the interrupt signal is set (path 2b, etc.)
Set IOC2 in use, and if there is no activation from another path, move on to the next operation.

(ST-5): Execute interrupt sequence (d) by instructing the interrupt generation circuit 5a to start.

(ST-6): Set the T2 signal and interrupt signal to the activation determination circuit 4a in the path 2a.

Note that if there is activation to a path other than path 2a, activation can be accepted.

(ST-7): If there is activation from a path other than path 2a where the interrupt signal is set (such as path 2b), execute activation acceptance sequence a (e), and if there is no activation from path other than path 2a, proceed to the next step. .

(ST-8): According to the instruction to the interrupt generation circuit 5a,
Execute interrupt sequence (d).

〔Effect of the invention〕

According to the present invention as described above, when the input/output control device is shared by a complex system, the interrupt processing of the input/output control device is optimized in accordance with the system, and input/output commands to the input/output device can be processed more smoothly. It has the effect of saying.

[Brief explanation of drawings]

FIG. 1 shows a complex system having an input/output control device according to the present invention, A is a block diagram of the complex system, B is an embodiment of the activation/interrupt priority selection circuit according to the present invention, and C is a priority according to the present invention. FIG. 2 is a flowchart of the input/output control device according to the present invention, and FIG. 3 is a block diagram of a multiprocessing computer system. In the figure, 1a and 1b are host devices, and 2 is
IOC, 2a, 2b are passes, 3a to 3n are IOD, 4
a and 4b are activation determination circuits, 5a and 5b are interrupt generation circuits, 6 is a control section, 7 is an interrupt instruction circuit, 8 is an activation priority instruction circuit, 9 is an activation/interrupt priority selection circuit, 10 is a counter, and 11 is logic 12 is a decoder, and 13 is an inverter.

Claims (1)

[Claims] 1. Startup that is located between multiple higher-level devices and multiple input/output devices, and even when the interrupt status for one of the higher-level devices is maintained, it receives input/output commands from the other higher-level device with priority. In a device having a priority means and an interrupt priority means for waiting the input/output command processing until the interrupt status is processed when the interrupt status is held, the activation priority means and the interrupt priority means are activated at a predetermined period. 1. An input/output control device comprising: a priority selection means for switching between the input and output devices; and the priority selection means controls the flow of data between the plurality of host devices and the plurality of input/output devices.