JPH0340555B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for digitizing an audio signal applied to a digital VTR (video tape recorder).

A digital device that records or plays back a digital video signal obtained by PCM modulating a television signal.
VTR is proposed. In this case, the audio signal in the television signal is digitized separately from the video signal, and is recorded on an audio track separate from the video track, or inserted into the same track as the video track in a time-division manner. . As is well known, a video signal is divided into units divided by a line period, a field period, a frame period, and a color frame period.
In addition, when digitizing an audio signal, it is sampled using a sampling signal,
The sample value is A/D converted into a one-word code. When recording and reproducing the audio PCM signal obtained in this manner, one block is configured such that errors can be corrected for each of a plurality of words. As described above, since the digital video signal is divided into predetermined units, it is desirable that the associated digital audio signal is also divided into similar units.

By the way, the standard format for television signals is that the number of lines and fields is 525 lines/60
There is a field EIA system and a 625 line/50 field CCIR system, and the former has 525 lines/59.94 fields for color television signals. It would be advantageous if a digital processing device for audio signals could be used in common for any of these standards.

An object of the present invention is to propose an audio signal digitization method that can divide digital audio signals in units such as fields for television signals of different standard formats. It is something.

In the present invention, the sampling frequency _fs and the block frequency _fb are made to satisfy the following relationship. First, set the sampling frequency _fs to 50Hz and 60Hz
Select so that it is a common multiple of. The block frequency f _b is also selected to be a common multiple of 50Hz and 60Hz. Of course, the sampling frequency f _s and the blocking frequency f _b
must satisfy other general conditions. Regarding the sampling frequency f _s , the highest frequency in the band of the audio signal (e.g. 20kHz)
need to be more than twice as large. sampling frequency f _b
Examples of the value include 50.4KHz, 44.1KHz, etc. (f _s = 50.4KHz), 1008 samples at 50Hz and 1008 samples at 60Hz
840 samples are included in one field.

Furthermore, regarding the block frequency f _b , it is necessary to consider the quality of the transmission path (recording/reproduction system) (the status of error occurrence) and the accuracy of editing. In other words, if an error correction code is configured for each block,
In order to improve the ability to correct long burst errors, it is desirable that the length of one block be long when the redundancy is constant, and when editing is performed with high precision, it is desirable that the length of one block be short. It is necessary to take this into account and determine the optimum value, and an example of the block frequency f _b is 300 Hz.

The sampling frequency f _s and block frequency f _b as described above are formed by dividing the master clock. When the standard format of 525 lines and 60 fields becomes 525 lines and 59.94 fields for a color television signal, the frequency of the master clock is changed by a factor of 1000/1001. By this, (f _s = 50.4KHz) (f _b =
300Hz) respectively (f _s ′=50.35KHz) (f _b ′=299.7Hz)
The number of samples and blocks in one field can be kept at 840 samples and 5 blocks, respectively.

In the above explanation, it is assumed that the video signal is switched in field units, so the sampling frequency f _s and the block frequency f _b were selected to be a common multiple of 50 Hz and 60. However, it is assumed that the video signal is switched in frame units. For example, the sampling frequency f _s and the block frequency f _b may be selected as integral multiples of 150 Hz, which is a common multiple of 25 Hz and 30 Hz. Furthermore,
When switching video signals in 4 fields, which is the EIA color frame, 75Hz
When the sampling frequency _fs and block frequency _fb are selected to be an integer multiple of 37.5Hz, and when the video signal is switched in 8 fields which are CCIR color frames, the sampling frequency fs and block frequency _fb are selected to be an integer multiple of 37.5Hz. f _b is selected.

An example of a digital VTR to which the present invention is applied will be described below. In this example, as shown in FIG. 1, four magnetic tracks T _A , T _B , T _C and T _D are formed. Video data for 1/4 field is recorded on each track. The audio data is recorded on each of the four tracks so as to be mixed with the video data. In this way, unlike recording audio data distributed on a single track,
As shown in FIG. 2, the data may be recorded collectively on each track. In the case of Figure 2, first,
Video data is recorded, and then a guard band is formed and audio data is recorded in the remaining track area. The video data and audio data are each subjected to error correction coding, then mixed, supplied to a rotating magnetic head, and recorded on a magnetic tape T.

In Figure 3, 1 is the total of CH1 to CH16.
A sample alternator is shown that is supplied with 16 channels of audio PCM signals. The audio PCM signal of each channel is sampled at, for example, 50.4 KHz, and one sample is 16 bits. This alternator 1 forms 16 data sequences consisting of a mixture of audio PCM signals of each channel. As mentioned above, 4
Since audio data is recorded as book tracks T _A , T _B , T _C , and T _D , CH1~
Four data series consisting of a mixture of PCM signals of CH4 (recorded as track T _A ) and CH5~
Four data series consisting of a mixture of PCM signals of CH8 (recorded as track T _B ) and CH9~
Four data series consisting of a mixture of PCM signals of CH12 (recorded as track T _C ) and CH1
Four data series (recorded as track T _D ) are formed by mixing the PCM signals of CH3 to CH16, and the 16 samples included in each data series are sent in parallel to the output of alternator 1. appear. This data is supplied to an interleave circuit 2 and a vertical parity generation circuit 3. One sample of vertical parity is formed from four samples of data and inserted into a time slot formed by interleave circuit 2. The interleave circuit 2 is composed of a memory, and a memory controller 4 is provided in association with the interleave circuit 2. Time slots to which horizontal parity and CRC codes are added are also formed by the interleaving circuit 2. CRC
is a type of error detection using a cyclic code.
Further, from the interleave circuit 2, the data series recorded as each of the four tracks are taken out, and the horizontal parity generation circuits 5A, 5B, 5 respectively
C, 5D. Horizontal parity generation circuit 5
The outputs of A to 5D are supplied to CRC generation circuits 6A to 6D, respectively, and a CRC code is added to every four samples. Each output of the CRC generation circuits 6A to 6D is supplied to the formatter 7. The formatter 7 performs interleaving and converts audio data into time series data necessary for mixing with video data, and is composed of a memory, and a memory controller 8 is provided in connection with this. It is being The output of the formatter 7 is mixed with video data and recorded as four tracks T _A to T _D.

A timing signal generator 9 is provided to perform each process of the audio encoder. The timing signal generator 9 includes a PLL circuit 10 to which a reference vertical synchronization signal VD is applied and a frequency divider circuit 1.
It is composed of 1. The PLL circuit 10 is configured to generate a master clock having a frequency of f ₀ =430080f _v by multiplying the field frequency f _v of the vertical synchronizing signal VD by 430080, and to switch to a master clock having a frequency 1000/1001 times that frequency. has been done. For example, this PLL circuit 10 is
As shown in the figure, a phase comparison circuit 101 to which a vertical synchronization signal VD is supplied is connected to a low-pass filter 102.
It is connected to the VCO circuit 103 via. and,
This VCO circuit 103 is connected to the phase comparator circuit 101 via a frequency division circuit 104 with a frequency division ratio of 1/430080, and a frequency division circuit 105 with a frequency division ratio of 1/1000.
connected to. This frequency dividing circuit 105 includes a phase comparison circuit 106, a low-pass filter 107,
It is connected via a VCO circuit 108 to a frequency dividing circuit 109 with frequency dividing ratios of 1/1000 and 1/1001. This frequency dividing circuit 109 switches the frequency division ratio between 1/1000 and 1/1001 in accordance with a switching signal.
This frequency dividing circuit 109 is connected to a duty shaping circuit 110. The duty shaping circuit 110 is connected to the phase comparator circuit 106 and also to the frequency dividing circuit 11. By the 1/512 frequency divider included in the frequency divider circuit 11, (f _s =
A sampling pulse of (50.4 KHz) is formed, and a block pulse of (f _v =300Hz) is formed by a 1/168 frequency divider to which the sampling pulse is supplied. These values are for (f _v = 60Hz),
In the case of (f _v = 50Hz), (f _s ′=50.35KHz) (f _b ′=
299.7Hz). In addition to these sampling pulses and blocking pulses, the timing signal generator 9 generates various timing pulses necessary for encoder processing.

As mentioned above, (f _s = 50.4 KHz) (f _b = 300 Hz), so in the case of (f _v = 60 Hz), there are 5 interleaved blocks in one field, and each block has , 168 samples of audio PCM data are included per channel, and 1 field includes 840 samples of PCM data.

Figure 4 shows the configuration of one interleave block per track, which is (6 x 8
= 48) sub-blocks. In FIG. 4, S _i represents 4 samples of PCM data, VP _i represents 4 samples of vertical parity, and C _i represents 1 sample of CRC code. In Figure 4, for ease of illustration,
Display of CRC code C _i is omitted except for some parts. For example, one subblock containing PCM data of S ₁₁₁ , S ₂₁₁ , S ₃₁₁ , and S ₄₁₁ is as shown in FIG.
Contains (4×4=16) samples of PCM data, 1 sample of vertical parity VP is formed from 4 samples in the vertical direction, and CRC codes C ₁₁₁ , C ₂₁₁ , C ₃₁₁ , C are formed from 4 samples in the horizontal direction. ₄₁₁ and C ₅₁₁ are formed. Furthermore, horizontal parity HP _i is formed for each PCM data included in each horizontal direction of the interleave block. For example, S ₁₁₁ , S ₁₁₂ , S ₁₁₃ ,
Horizontal parity HP ₁₁₈ from S ₁₁₄ , S ₁₁₅ , S ₁₁₆ , S ₁₁₇ ,
is formed. This horizontal parity H _i also consists of four samples. Vertical parity VP _i and CRC code C _i are also added to horizontal parity HP _i .
Subblocks similar to PCM data are formed.

As shown in FIG. 4, if codes N ₁ to N ₃₀ are assigned to each horizontal row series of one interleave block, one track is divided into (N ₁ N ₇ N ₁₃ N ₁₉ ) appear in parallel, then the four sequences (N ₂ N ₈ N ₁₄ N ₂₀ ) appear in parallel, and then the four sequences (N ₃ N ₉ N ₁₅ N ₂₁ ) appear in parallel. series, four series of (N ₄ N ₁₀ N ₁₆ N ₂₂ ),
4 series of (N ₅ N ₁₁ N ₁₇ N ₂₃ ), (N ₆ N ₁₂
N ₁₈ N ₂₄ ) appear sequentially in parallel. And of the 4 samples taken from each series,
From PCM data N ₂₅ , N ₂₆ , N ₂₇ , N ₂₈ , N ₂₉ ,
A vertical parity series designated N ₃₀ is formed by the vertical parity generation circuit 3. The interleave circuit 2 converts each track into one data series. As shown in Figure 6A, N ₁ →N ₂ →
A data series arranged in the order N ₃ →N ₄ ...N ₃₀ appears from the interleaving circuit 2, and is added with horizontal parity and CRC codes by passing through the horizontal parity generation circuit 5A and CRC generation circuit 6A. Ru.

The formatter 7 further performs interleaving on the data series for each track.
That is, 5 samples S ₁₁₁ and C ₁₁₁ of data series N ₁
After that, 5 samples of data series N ₂ S ₁₂₁ and C ₁₂₁
Interleaving is performed such that the data is located, and a data series arranged as shown in FIG. 6B is extracted. PCM data forming common horizontal parity data e.g. S ₁₁₁ and S ₁₁₂ forming HP ₁₁₈
are separated by 30 samples as shown in Figure 6B. This 30 samples is the horizontal interleaving length, and prevents uncorrectable multiple errors in PCM data forming common horizontal parity data due to burst errors.
It also forms a common vertical parity data
PCM data, for example, S ₁₁₁ and S ₂₁₁ forming VP ₅₁₁ are located 240 samples apart, as shown in FIG. 6B. These 240 samples are the vertical interleaving length, and burst errors can be dispersed in the same way as described above.

Although not shown in FIGS. 6A and 6B, synchronization signals are added to each predetermined number of samples and each interleave block. As shown in FIG. 6C, the block frequency f _b of one interleave block is set to 300 Hz, and the period
One interleave block is completed in T _b (=1/300 seconds). Therefore
During one field (=1/60 second) of the EIA method,
Each time slot from T _b1 to T _b5 will contain five interleave blocks. Also, as is clear from the above explanation, (4×4×6×7
= 672) samples of information samples and 528 samples of redundancy samples (parity and CRC codes) and 60
A total of 1260 samples including the sample synchronization signal are included in one interleave block. If the field frequency is 50 Hz in the CCIR system, one field will contain six interleave blocks.

The above-described error correction encoding method is just one example, and various modifications such as using an error correction code other than parity are possible.

As understood from the above description, according to the present invention, an integer number of blocks of digital audio signals are included in a unit in which a digital video signal is divided, so that audio signals related to video data are It can simplify the process of recording and reproducing data, and is suitable for use when recording and reproducing both video and audio data on the same magnetic tape using a rotating magnetic head, such as in a digital VTR. . Furthermore, when a color television signal with a field frequency of 59.94Hz is input, the master clock frequency is set to 525Hz.
If one frame is made up of lines and a television signal with a field frequency of 60 Hz is input, and the master clock frequency is switched to 1000/1001 times, the television standard system will comply with EIA and CCIR. In different cases, an integer number of samples and blocks can be included in a field, frame, or color frame unit for both the EIA system, black-and-white television system, and color television system. A digital audio signal processing device that is compatible with any system can be realized.

[Brief explanation of drawings]

1 and 2 are schematic diagrams showing one example and another example of a track pattern of a digital VTR to which the present invention can be applied, and FIG. 3 shows the configuration of an example of a device to which the present invention is applied. 4 and 5 are schematic diagrams used to explain error correction encoding, FIG. 6 is a time chart used to explain the operation of this device, and FIG. 7 is a block diagram showing an example of the configuration of the PLL circuit 10. It is a diagram. T is a magnetic tape, T _A to T _D are tracks, 3 is a vertical parity generation circuit, 5A to 5D are horizontal parity generation circuits, and 9 is a timing signal generator.

Claims (1)

[Claims] 1. A step of generating a master clock, and dividing the frequency of this master clock,
A block pulse having a block frequency fb selected to be a common multiple of any one of the field frequencies, frame frequencies, or color frame frequencies of a plurality of mutually different television systems and a sampling pulse having a sampling frequency fs. and an audio signal corresponding to an input television signal of any one of the plurality of television systems using the sampling pulse.
An audio signal characterized by comprising a step of PCM modulating the PCM audio signal to obtain a PCM audio signal, and a step of converting the PCM audio signal into blocks using the block pulses so that each predetermined plurality of words constitutes one block. digitization methods. 2 The above step of generating the master clock is performed when one frame consists of 525 lines and when a color television signal with a field frequency of 59.94Hz is input, one frame consists of 525 lines and the field frequency is 60Hz. The digital audio signal according to claim 1, further comprising a step of generating a master clock having a frequency 1000/1001 times higher than the frequency of the master clock generated when a television signal is input. method.