JPH0340556B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a predictive coding device for image signals.

The predictive coding method is a method developed based on the operating principle of reducing the amount of transmitted information by transmitting the difference between the input signal that should originally be transmitted and the predicted value. In image signal transmission systems such as television, for example, in interframe coding, still images,
Alternatively, prediction errors with large amplitudes occur less frequently for quasi-still images that contain little movement, so the amount of generated information is small, and the amount of generated information increases for images that include a lot of movement. In other words, the less motion there is, the better the encoding efficiency is. Therefore, attempts have been made to improve efficiency even when motion is involved. In other words, since motion included in television signals is often considered to be due to parallel movement, high coding efficiency can be achieved even for moving images by performing interframe prediction that takes into account the amount of change in the position of the subject between frames. This is what we are trying to achieve.

As shown in FIG. 1, it is assumed that a figure located near the coordinates (x ₀ , y ₀ ) at time t=T ₀ moves to (x ₁ , y ₁ ) after one frame time (τ). At this time, in normal interframe predictive coding, 1
By using the previous frame as a prediction signal, pixels near (x ₀ , y ₀ ) at t=t ₀ are used to predict pixels near (x ₀ , y ₀ ) at t=t ₀ +τ. . Therefore, as is clear from Figure 1, at t = t ₀ + τ, the difference value (prediction error) that is not zero is near both points (x ₀ , y ₀ ) and (x ₁ , y ₁ ). occurs in Here, if we can somehow detect the amount of displacement of the figure from (x ₀ , y ₀ ) to (x ₁ , y ₁ ), then the figure near (x ₀ , y ₀ ) at t=t ₀ The figure in the vicinity of (x ₁ , y ₁ ) at t=t ₀ +τ can be predicted using , and the amount of generated information is greatly reduced. This is the principle of so-called "motion compensation."
In other words, the optimal prediction point for a figure near (x ₁ , y ₁ ) at t=t ₀ +τ is near (x ₀ , y ₀ ) at t=t ₀ . When this optimal prediction point is expressed by a function using time or space coordinates, this is called an optimal prediction function. Usually, this determination of the optimal prediction function is carried out in units of blocks consisting of a plurality of pixels, predictive coding is performed using the detected optimal prediction function, and a signal indicating the optimal prediction function is transmitted together with a prediction error signal.

As a method for determining this optimal prediction function, for example, in order to make a determination exhaustively and within a limited time for the entire range corresponding to the speed to be compensated for in block units, the prediction error amount (the following The explanation uses prediction error power as an example)
There is a way to perform the calculation. However, this method requires a very large and complicated circuit, making it almost impossible to implement it using actual hardware.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a highly efficient predictive encoding device that has simplified hardware and is capable of predictively encoding an image signal at high speed.

The image signal predictive encoding device according to the present invention constructs a two-dimensional block consisting of M pixels (M is an integer of 2 or more) extending between a plurality of scanning lines from an image signal input as a time series, and scan conversion means for outputting image signals in an order different from the time series of the scan conversion means; means for comparing the amount of prediction error of the two-dimensional block by repeatedly using at most M calculation means, and means for generating a prediction signal for the two-dimensional block in accordance with the optimal prediction function for which the amount of prediction error is determined to be small by the comparison means. a means for generating a prediction error signal upon receiving the output of the prediction signal generation means and the output of the scan conversion means; and a means for generating a prediction error signal upon receiving the output of the prediction signal generation means and the output of the prediction error signal generation means; local decoding means for generating a decoded image signal and supplying it to the comparison means and the prediction signal generation means;
The present invention is characterized by comprising code conversion means for compressing and encoding at least a signal representing the optimal prediction function obtained from the comparison means and a prediction error signal obtained from the prediction error signal generation means.

Here, the basis for the creation of the present invention and its features will be briefly described. First, the speed of motion to be compensated is assumed to be ±m pixels/frame in the horizontal scanning line direction (x direction) and ±n lines/frame in the direction perpendicular to the horizontal scanning line (y direction). In this case, there are a total of N=(2m+1)×(2n+1) types of quantities (motion vectors) representing the speed and direction of movement: (2m+1) types in the x direction and (2n+1) types in the y direction. It is sufficient to prepare as many prediction functions as there are motion vectors. Assume that there is an object moving at a speed of V _x pixels/frame in the x direction and V _y pixels/frame in the y direction. However, it is assumed that both V _x and V _y are within the scope of the above compensation. That is, −m≦V _x ≦m −n≦V _y ≦n. According to this, prediction from a point shifted by −V _x in the x direction and −V _y in the y direction from a spatially corresponding point in the previous frame minimizes the prediction error power P and becomes optimal. That is, the prediction function expressed using the vector (-V _x , -V _y ) becomes the optimal prediction function.

In order to calculate this prediction error power P (the square of the difference value) in units of blocks and find the optimal prediction function at high speed, it is effective to perform parallel calculations on signals that can be processed simultaneously. For example, when calculating the prediction error power P to determine the optimal prediction function, (A) the range N of motion compensation, and (B)
Concerning the number of pixels M in a block, parallel calculations can be considered. This example will be explained below using a block consisting of four pixels (M=4) as an example. In Figure 2, a shows an example of the arrangement of pixels D 1 to D 4 of a block of an input image to be predicted, and b shows an example of the arrangement of pixels D ₁ to _{D 4} of the block of the input image to be predicted, and b shows the two-dimensional arrangement used for prediction in order to efficiently perform motion compensation. The arrangement of pixels is shown for m=n=1. (0,0), (1,0) in Figure 2b,
..., (-1, -1), etc. symbols represent motion vectors. For example, (0, 0) is a point exactly one frame before, (1, -1) is one pixel to the right in the horizontal direction, In the vertical direction, each point is shown one line down. The same applies to others. For example, to specifically explain the above calculation methods (A) and (B) performed according to the motion vector (1, -1), in the case of (A), (D ₁ -X ₅ ) ² , (D ₁ −X ₆ ) ² , (D ₁ −X ₇ ) ² , (D ₁
−X ₉ ) ² , (D ₁ −X ₁ ) ² , (D ₁ −X ₂ ) ² , (D ₁ −X ₁₀ ) ² ,
Calculations for nine types (D ₁ −X ₃ ) ² and (D ₁ −X ₄ ) ² are performed simultaneously. The same procedure is repeated for D ₂ , D ₃ , and D ₄ .

In the case of (B), (D ₁ −X ₄ ) ² , (D ₂ −X ₁₂ ) ² , (D ₃
-X ₁₅ ) ² and (D ₄ -X ₁₆ ) ² are performed simultaneously. The same process is repeated for the remaining eight types of motion vectors.

becomes. Therefore, the total number of operations is 4×9=36
(A) and (B) are also the same. In this way, in both cases (A) and (B), the number of operations required to determine the optimal prediction function is M×N.

Considering the case where this parallel operation is executed on actual hardware, (D ₁ −X ₅ ) ² , (D ₁ −X ₆ ) ² ,...
Alternatively, one calculation unit calculates any one of (D ₁ −X ₄ ) ² , (D ₂ −X ₁₂ ) ² , . . . and,
Let the calculation result be P _ij . However, it is assumed that i represents a pixel within a block and j represents one of a plurality of prediction functions. In case (A), P _ij is first calculated in parallel for j=1, 2, 3, ..., N,
Next, calculations for i=1, 2, 3, . . . , M are performed for each i. Therefore, unless _M 〓 ⁱ⁼¹ P _ij is stored for each j, it is not possible to compare and determine the minimum prediction error power per block. In case (A), at least N arithmetic units, an accumulation circuit for adding and storing N prediction error powers, and a comparison circuit for N prediction error amounts are required. In case (B), _M 〓 ⁱ⁼¹ P _ij ,
That is, since P _ij is first calculated and added in parallel for i=1, 2, 3, . . . , M, the prediction error power per block for one prediction function can be obtained at once. Then, it is sufficient to compare this prediction error power with the prediction error power for other prediction functions and determine the smaller one, and it is possible to complete the comparison and determination at most N times. That is, M arithmetic units and M
The input adder and comparator circuit can be used N times. Generally, when performing a large number of the same calculations, the hardware scale can be reduced by repeatedly using the same calculation circuit. In case (A), once the number N of motion vectors is determined, the calculation is repeated for the number M of pixels in the block, so the hardware scale is approximately determined by the value of N. In a television signal, which is a typical image signal that includes motion, motion with various speeds appears, but motion compensation is required for motion within the range of 6 pixels/frame left and right and 6 lines/frame up and down. , the number N of motion vectors is 169. On the other hand, regarding the number of pixels M in a block, it is convenient to set M as small as possible, since the larger M is, especially the wider it is in the vertical direction (line direction), the larger the device scale will be. Even for a block of 8 lines x 16 pixels, which is considered to be a relatively large block, M=128, and the relationship M<N holds.

In a predictive encoding device using motion compensation, it is desirable to make the range of motion compensation, that is, the number of motion vectors N, as large as possible, and to make the number M of pixels in a block as small as possible. From this point of view, since the hardware scale of method (A) is determined approximately by the value of N, it is difficult to widen the range of motion compensation because this increases the hardware scale. In this respect, since the method (B) mainly uses M arithmetic units repeatedly N times, the hardware scale is approximately determined by the value of M. In other words, it can be seen that method (B) is more advantageous.

By the way, when processing in units of two-dimensional blocks as described above, it is more advantageous to use an image signal that has been scan-converted in advance. According to this, the pixels in a two-dimensional block spanning multiple scanning lines are rearranged, and the pixels in each block are scan-converted so that they are continuous, so that all pixels in the two-dimensional block are serially arranged. are arranged according to Therefore, 2
There is no need to pay attention to the existence of scanning lines when predictively encoding pixels within a dimensional block, and a 2-dimensional block can be treated in the same way as a 1-dimensional block made from M pixels on the same scanning line. . As can be seen, if scan conversion is performed in advance, predictive coding using two-dimensional blocks is no different from predictive coding using one-dimensional blocks. Further, according to the present invention, the above (B)
By realizing the case of , it is possible to determine the optimal prediction function by repeating M calculation units N times, and for this purpose, when the number M of pixels included in a block is small, the hardware can be made smaller. becomes possible. Of course, when the value of M is large, the number of arithmetic units can be made smaller than M. Furthermore, since the prediction error power per block for one prediction function is calculated in one calculation, it is possible to select the prediction function to be compared next while performing the calculation, and the optimal prediction function can be determined. There is an advantage that it is not necessary to perform calculations for all N types until the calculation is completed.

Next, embodiments according to the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of a predictive coding apparatus according to the present invention. In this device, an input image signal is fed via line 100 to a scan conversion circuit 1, where a block of pixels is formed. The blocked image signal is transmitted through lines 101a and 10 branched from line 101.
The signals are respectively supplied to a delay circuit 2a and an optimal prediction function determination circuit 8 via 1b. This delay circuit 2a delays the blocked image signal by the time required to determine the optimal prediction function. The delay time is approximately the time relative to the number of pixels included in the block. The difference between the image signal supplied from the delay circuit 2a to the subtraction circuit 2b and the prediction signal supplied via a line 105a branched from the output line 105 of the prediction signal generation circuit 5 is calculated, and this difference, that is, a prediction error signal is supplied to a quantization circuit 3 which normally has the function of limiting the number of possible levels. The quantized prediction error signal is supplied to the information compression circuit 7 via a line 103a branched from the line 103. At the same time, the predicted signal output from the predicted signal generation circuit 5 is supplied via line 105b to adder 4, which generates a locally decoded signal by addition with the quantized prediction error supplied via line 103b. This locally decoded signal is supplied via line 104 to a delay circuit 6 for use in generating a subsequent prediction signal. The delay time of the delay circuit 6 depends on the prediction function used, but in this embodiment, it is set to about one frame time, and the local signal is transmitted to the optimum prediction signal generation circuit 5 and the optimum prediction function determination circuit 8 via lines 106a and 106b, respectively. It is supplied as a decoded signal. In the predicted signal generation circuit 5,
1 from the stranded wire 108 of the optimum prediction function determination circuit 8
Based on the information indicative of the optimal prediction function provided via line 108a, a delayed locally decoded signal provided via line 106a is used to generate a prediction signal, referred to as the optimal prediction signal as described above. . This determination of the optimal predicted signal is performed on a block-by-block basis, and the aforementioned predictive encoding using the optimal predicted signal is executed according to this result. The optimal prediction function determination circuit 8 determines the optimal prediction function using the blocked input image signals supplied through the lines 101b and 106b, respectively, and the delayed locally decoded signal output from the delay circuit 6.

Information indicating the optimal prediction function determined as described above is simultaneously supplied to the information compression circuit 7 via line 108b. The information compression circuit 7 receives the information indicating this optimal prediction function and the prediction error signal output from the quantization circuit 3 when using this prediction function together with the synchronization signal necessary for decoding, and reduces the amount of code as much as possible. Perform compression conversion so that it can be expressed as This compressed and converted signal is sent to a transmission path or a recording medium via line 107. Note that the information compression circuit 7 also has a speed matching function so that compressed information can be output at a constant speed.

FIG. 4 is a block diagram showing a specific example of the configuration of the scan conversion circuit 1 shown in FIG. 3. In this embodiment, as shown in FIG. 5, a 2.times.2 two-dimensional block with two pixels horizontally and two lines vertically is used as the image block. In FIG. 5, _one block is composed of four pixels (indicated by circles) surrounded by broken lines such as a ₁₁ , a ₁₂ , a ₂₁ , and a 22 . The scanning direction in normal television is from left to right in the figure, for example a ₁₁ , a ₁₂ ,
A ₁₃ , a ₁₄ are scanned in the order, and the next scanning line is a ₂₁ , a ₂₂ ,
This includes a ₂₃ and a ₂₄ . Therefore, in the circuit of FIG. 4, the scanning line including pixels a ₁₁ to _{a 14}
The signal of _S1 is sequentially stored in the line memory 1-1, and the scanning line _S2 including _a21 to _a24 is sequentially stored in the line memory 1-2. Then, while the next scanning lines S ₃ and S ₄ of a ₃₁ to a ₃₄ and a ₄₁ to _{a 44} are stored in the line memories 1-3 and 1-4, respectively, the line memories 1-1 and 1 are stored in the same way. -2, the blocks are read out in block order, that is, a ₁₁ , a ₁₂ , a ₂₁ , a ₂₂ , a ₁₃ , a ₁₄ , a ₂₃ , a ₂₄ , . . . . In the following explanation, reading in this block order will be used, but in addition, a ₁₁ , a ₂₁ , a ₁₂ ,
It is also possible to read out in the order of a ₂₂ , a ₁₃ , a ₂₃ , a ₁₄ , a ₂₄ , . . . The time required to finish reading the scanning lines S ₁ and S ₂ in such a scan-converted format is the same as in the case without scan conversion, so when you finish reading S ₁ and S ₂ , the data is transferred to line memories 1-4. S ₄ memory ends. Therefore, at this point, line memory 1-
3 and 1-4 are read out in the aforementioned scan-converted format, and the next scanning lines S ₅ and S ₆ are stored in order in line memories 1-1 and 1-2, respectively. .

In this way, line memories 1-1, 1-2 and 1
-3 and 1-4 are paired and stored and read out alternately, so that an image signal in a format in which the scanning order is converted, that is, an image signal that is two-dimensionally blocked, is output one pixel at a time. Ru. Thus, one of the two outputs from the pair of line memories being used for reading is sent to multiplexer 1.
-5 is selectively output. The output of the blocked image signal is branched to lines 101a and 101b via line 101, and supplied to delay circuit 2a and optimal prediction function determining circuit 8, respectively. This scan conversion is useful in order to avoid complicating a predictive encoding circuit when using two-dimensional blocks. If some calculation is performed in units of two-dimensional blocks without performing scan conversion, the scanning of the image signal in FIG. 5 will be a ₁₁ , a ₁₂ , a ₁₃ , a ₁₄ , . . .
To calculate a two-dimensional block consisting of four pixels a ₁₁ , a ₁₂ , a ₂₁ , a ₂₂ , it is necessary to calculate until the pixels a ₂₁ , a ₂₂ , a ₂₃ , a ₂₄ , etc. on the next scanning line arrive. It is necessary to interrupt the calculation and wait. Although there are a considerable number of blocks in between, the computation remains suspended for all of these blocks. However, after performing scan conversion, the image signals are a ₁₁ , a ₁₂ , a ₂₁ , a ₂₂ , a ₁₃ , a ₁₄ , a ₂₃ , a ₂₄ ,...
Therefore, the calculation for the two-dimensional block is a ₁₁ , a ₁₂ , a ₂₁ , a ₂₂ , or a ₁₃ , a ₁₄ , a ₂₃ ,
A ₂₄ , which is just 4 pixels, generally takes M pixels. If scan conversion is performed in advance in this way, operations on two-dimensional blocks can be performed on one-dimensional blocks without scan conversion, such as a ₁₁ ,
The calculation is the same as for the block consisting of a ₁₂ , a ₁₃ , and a ₁₄ , and the control of the calculation becomes very easy.

FIG. 6 shows a specific example of the configuration of the optimum prediction function determination circuit 8 in FIG. 3, and FIG. 7 shows a specific example of the arithmetic unit 8-1 in FIG. 6, using blocks. First, as shown in FIG. 6, for example, the output signal of the delay circuit 6 supplied to the arithmetic unit 8-1 via the line 106b is sent to the predicted signal generation memory 8-11a in the arithmetic unit 8-1. It will be remembered once. On the other hand, the blocked input image signal is supplied to the pixel expansion circuit 8-6 via line 101b, where all four pixels in the block, for example D ₁ , D ₂ ,
D ₃ and D ₄ are expanded in parallel and output simultaneously.

One pixel among these four pixel parallel outputs is line 108-
6a to the subtraction circuit 8 in the arithmetic unit 8-1.
-12a. Hereinafter, the position of the pixel processed by this arithmetic unit 8-1 within the block will be referred to as pixel point _D1 , as shown in FIG. 2a. The calculation units 8-2 to 8-4 are considered in the same way, and the calculation unit 8-1 calculates the pixel point _D1 as follows.
The other calculation units 8-2 to 8-4 each have a pixel point _D2 to
If it is assumed to be responsible for the calculation of _D4 , one block of calculation can be executed in parallel by using a total of four calculation units in parallel.

Hereinafter, 8-1 will be taken up as a representative arithmetic unit and will be explained in detail with reference to FIG. As shown in the figure, the arithmetic unit 8-1 can be roughly divided into a two-dimensional memory 8-11 and an evaluation signal generation circuit 8-1.
12. Among these, the two-dimensional memory 8-11 is the predicted signal generation memory 8-11a.
and a write control circuit 8 that controls the address, timing, etc. of writing and reading image signals thereto.
-11b, a read control circuit 8-11c, and a constant generation circuit 8-11d. This predicted signal generation memory 8-11a is easily and compactly constructed by using a register file, RAM (random access memory), and the like. The write control circuit 8-11b executes an operation of writing the output signal of the delay circuit 6 into the predicted signal generation memory 8-11a at a predetermined address as a supplementary image signal to be used for generating a predicted signal in the next block. Prediction function instruction circuit 8-5 in FIG.
The determination can be made based on the motion vector (0, 0) included in the prediction selection signal supplied via the line 108-5a, that is, the address corresponding to interframe prediction. Read control circuit 8-1
1c is stored with unique values assigned to each of the arithmetic units 8-1 to 8-4 given by the constant generating circuit 8-11d based on the predictive selection signal supplied via the line 108-5a. One of the image signals is selected and read out. That is, if the prediction selection signal supplied via line 108-5a is the motion vector (0,0) in FIG.
The two-dimensional memory 8-11 of unit 1 outputs X= _X1 , and the two-dimensional memories of calculation units 8-2 to 8-4 output _X2 , _X3 , and _X4, respectively. This means that when reading an image signal, the arithmetic unit 8-1 reads (x, y) for the read address (x, y) of the prediction signal generation memory 8-11a expressed by the prediction selection signal. In 8-2, (x+1,
y), 8-3 and 8-4 respectively (x, y+1)
This can be easily executed by modifying the read address so that it becomes (x+1, y+1). In this way, in the constant generating circuit 8-11d, each of the arithmetic units 8-1 to 8-4 (0,
0), (1, 0), (0, 1), and (1, 1) for address modification are set, and the same prediction selection signal is given to the calculation units 8-1 to 8-4. Therefore, parallel calculations are executed for all pixels within one block. According to this, it will be understood that all of the arithmetic units 8-1 to 8-4 can be realized by circuits having the same configuration by simply changing the constant value in the constant generating circuit 8-11d.

Here, the pixels included in the block are in a two-dimensional array of 2x2=4 as explained in Fig. 5, and the range of motion compensation for this block is as explained in Fig. 2. Assuming that the speed is ±1 pixel/frame in the horizontal direction and ±1 line/frame in the vertical direction, as is the case with the motion compensation range used, in order to motion compensate for this block within this range, as shown in Figure 2. As shown in b, (0,
0), which is mainly used for images that are still one frame before.
1), (1, 0), ..., (-1, -1), 16 prediction signals from _X1 to _X16 are required for nine motion vectors. For example, when (0, -1) is used as a prediction function, X ₃ , X ₄ , X _{14 ,} This means performing an operation with the block to be predicted, such as the block including a ₁₁ , a ₁₂ , a ₂₁ , and a ₂₂ in FIG. Furthermore, when (1, -1) is used as a prediction, calculations with X ₄ , X ₁₂ , X ₁₅ , and X ₁₆ are performed. In this way, regarding the above motion compensation range,
Sixteen types of prediction signals are required.

The blocks to be predicted at present, for example the blocks a ₁₁ , a ₁₂ , a ₂₁ , a ₂₂ in FIG. 5, are X ₁ , X ₂ ,
Assuming that it is exactly one frame time apart from the blocks of X ₃ and X ₄ , the block has a width of 2 pixels in the horizontal direction (2×2), _so
The predicted signals during motion compensation for a ₁₂ , a ₂₁ , and a ₂₂ are
As mentioned earlier, there will be 16 types from X ₁ to X ₁₆ . Similarly, there are 16 types of prediction signals for the next blocks a ₁₃ , a ₁₄ , a ₂₃ , and a ₂₄ , and the breakdown is X ₂ , X ₄ ,
They are X ₇ , X ₈ , X ₁₁ , X ₁₂ , X ₁₅ , X ₁₆ and A ₁ to _{A 8} .
Therefore, while performing predictive coding using motion compensation for blocks a ₁₁ , a ₁₂ , a ₂₁ , and a ₂₂ , the 8 pixels A ₁ to A ₈ necessary for the next block are I have to replenish it. The delay circuit 6 supplies A ₁ to _{A 8} to the predicted signal generation memory 8-11a.
This is done by providing an output on line 106b. For each read and refill,
If the same amount of time, for example 4 pixel times, is allocated to each pixel, in order to store 8 pixels within this time, it is necessary to supplement 2 pixels in parallel per pixel time. That is, line 10
6b must be configured to be able to supply two pixels in parallel. The number of parallel lines of this line 106b is determined by the number of pixels (M) constituting the block, the shape of the block, the range of motion compensation, and the time (T) allowed for determining the optimal predicted signal. That is, it is assumed that there is a block (M=k×l) with k pixels in the horizontal direction and l lines in the vertical direction. The target range of motion compensation is |V _x |≦m, |V _y |≦n, and the time T is only given as the time equal to the total number of pixels M in the block. In other words, if we consider the case where predictive encoding processing is performed on an input image in real time, the number of supplementary pixels k x (2n + l) required to determine the optimal prediction function for the next block can be supplemented within time T. I have to. In the above example, k=2,
Since l=2 and m=n=1, the number of supplementary pixels was 2×(2×1+2)=8 pixels. Therefore, in order to replenish these k×(2n×l) pixels within T=M pixel time, the number of parallel lines used for replenishment must be k×(2n×l)/M, that is, 2×(2
×1+2)/(2×2)=2 pieces are required. As another example, for example, k=8, l=4, m=n=
In case of 6, 8×(2×6+4)/(8×4)=4
I need a book.

Prediction signal generation memory 8- for the supplementary pixel
It is easier to control writing and reading when the writing address to 11a follows the address where the pixels necessary for determining the optimal prediction function for the current block are stored. To do this, as shown in FIG. 7, A ₁ to _{A 8} are written following the address where X ₁ to X ₁₆ are stored. The storage capacity of the prediction signal generation memory 8-11a is expressed using the above-mentioned symbols (k, l, m, n), and is (2m+k) x (2n+l) pixels for determining the optimal prediction function of the current block. , k for supplementary pixels for determining the optimal prediction function in the next block.
Since ×(2n+l) pixels are required, the total is 2(m+k)×(2n+l) pixels.

Now, the prediction signal X selected and output from the prediction signal generation memory 8-11a and the surface image signal supplied via the line 108-6a are the same as the subtraction circuit 8-12.
a, and this difference value is subtracted in arithmetic circuit 8-
12b, when expressing the amount of prediction error, for example, prediction error power, a square calculation such as (a ₁₁ -X ₃ ) ² is performed, and the calculation result is outputted via line 108-1. Similarly, each calculation result for the calculation units 8-2 to 8-4 is shown on the line 108-
2,108-3,108-4. Hereinafter, prediction error power will be explained as an example of the prediction error amount.

Referring again to FIG. 6, a prediction signal is selected by a prediction selection signal supplied to each of the calculation units 8-1 to 8-4 from the prediction function instruction circuit 8-5 via a line 108-5a, and a prediction signal is selected via a line 106b. A difference signal is generated from the image signal supplied through the signal and these predicted signals, and the result of the square calculation is 108-1,10
The signals 8-2, 108-3, and 108-4 are supplied to the adder circuit 8-7, respectively. In the adder circuit 8-7, the sum of these four inputs, for example, when a motion vector of (0, -1) is used, (a ₁₁ -X ₃ ) ² +
The sum of (a ₁₂ −X ₄ ) ² + (a ₂₁ −X ₁₄ ) ² + (a ₂₂ −X ₁₅ ) ² is calculated, and the addition result is supplied to the prediction function comparison circuit 8-8. The result of this addition, that is, the prediction error power per block, is for one prediction function (or motion vector) specified by the prediction function instruction circuit 8-5 in a predetermined order.
In the prediction function comparison circuit 8-8, this addition result is compared with the addition result for the stored prediction function, and the smaller addition result is compared with the addition result for the next prediction function. hold until When an addition result smaller than the addition result already held is supplied to the prediction function comparison circuit 8-8, the addition result already held is replaced with the smaller addition result, and at the same time, the replacement occurs. A selection circuit 8 predicts and selects a replacement signal indicating
-9. When the prediction selection circuit 8-9 is supplied with this substitution signal, the prediction function instruction circuit 8-9
5 through line 108-5b. If there are a large number of prediction functions and it is difficult to determine the optimal prediction function within the specified calculation time because the calculation time will increase if the above calculation is performed for all prediction functions one by one, first calculate the Select some and perform the above calculation.
Then, determine an approximate optimal prediction function among them, and then do the same for some of the previously unused prediction functions that have vectors that are relatively similar to the motion vector corresponding to this prediction function. By repeating this a necessary number of times, the optimal prediction function among all prediction functions can be found with a small number of calculations. The accuracy of the information indicating the approximate optimal prediction function is thus gradually improved with each repetition, and is fed back to the prediction function instruction circuit 8-5 via line 108-9. The prediction function designation circuit 8-5 uses the fed back approximate optimal prediction function to sequentially designate several prediction functions to be compared in the next iteration.

FIG. 8 shows the prediction signal generation circuit 5 in FIG.
A specific example of the configuration is shown in a block diagram. In this figure, a two-dimensional memory 5-1 has almost the same configuration as the two-dimensional memory 8-11 included in the arithmetic unit 8-1 described above.
The difference is that the built-in prediction signal generation memory (abbreviated as P memory) is 8-11a.
) receives the output from the register 5-2 that holds information indicating the optimal prediction function for one block time, and then automatically reads the information according to the contents by the readout control circuit corresponding to the built-in 8-11c. All pixels in the block are sequentially read out and output from line 105. The constant generation circuit built in the two-dimensional memory 5-1 is set to (0, 0) like the constant generation circuit 5-11d in FIG. 7, for example, (0, -1).
If is the motion vector corresponding to the optimal prediction function, then X ₃ , X ₄ , X ₁₄ , and X ₁₅ are obtained from line 105 as optimal prediction signals in that order. While the two-dimensional memory 5-1 is outputting the optimal prediction signal, it replenishes the P memory with the locally decoded signal supplied via the line 106a in order to generate the optimal prediction signal for the next block. Although it is necessary,
The method is the same as the method of replenishing the predicted signal generation memory 8-11a in the arithmetic unit described above. Therefore, compared to the arithmetic unit 8-1, the predictive signal generating circuit 5 has only the function of the read control circuit slightly expanded.

The present invention is of course not limited to the range of motion compensation illustrated in the above embodiments, that is, the type of prediction function or the number of pixels included in a block. ±6 pixels/frame, ±6 respectively
line/frame (169 types of prediction functions), and the number of pixels included in a block is 4 lines x 8
Assuming that pixels = 32 pixels, the optimum prediction function can be obtained by preparing 32 calculation units and performing repeated calculations for determining the optimum prediction function in the optimum prediction function judgment circuit 8 up to 169 times. When determining the optimal prediction function in real time, assuming that one block consists of 32 pixels, it must be performed within 32 pixel time. Therefore, in this case, it is necessary to use a slightly different method for determining the optimal prediction function.
A method such as that introduced in "Study of motion compensated interframe coding system" by Mr. Hirano et al., described in , can be applied. That is, for the 169 types of motion vectors, in the first round, 9 motion vectors were selected to find an approximate optimal prediction function, and in the second round, nine motion vectors were selected to find an approximate optimal prediction function.
In the third calculation, nine types of motion vectors similar to the approximate optimal prediction function obtained in the first calculation were selected, and in the same way, an approximate optimal prediction function with increased accuracy was determined. In addition to the approximate optimal prediction function, which is the result of the second round with improved accuracy, we also used a total of nine motion vectors that differed by only one pixel or one line in either the horizontal or vertical direction. Once calculated, the optimal prediction function can be determined. By using the above method, 169
27 to determine the optimal prediction function from the species prediction function.
Therefore, even though there are many prediction functions, execution in real time is possible.

FIG. 9 is a block diagram showing an example of the configuration of a receiving side predictive decoding device opposite to the predictive coding device of FIG. 3. In FIG. In the figure, when an image signal that has been predictively encoded and information-compressed by the predictive encoding device shown in FIG. A synchronization signal necessary for restoring the original image inserted by the information compression circuit 7 on the side, information representing the optimal prediction function, and a prediction error signal for the optimal prediction function are each expanded and separated.
The information representing the expanded and separated optimal prediction function and the prediction error signal are shown on lines 211-2 and 21, respectively.
The signal is supplied to the prediction signal generation circuit 12 and the addition circuit 13 via 1-1. The prediction signal generation circuit 12 generates an optimal prediction signal according to information representing the optimal prediction function, and its function and configuration are the same as the prediction signal generation circuit 5 of the predictive encoding device. The generated prediction signal is sent to the adder circuit 13 via a line 212.
and the prediction error signal supplied via the line 211-1 is taken to obtain a reproduced image signal. The reproduced image signal is supplied to the scanning inverse conversion circuit 14 and the delay circuit 15 through lines 213a and 213b branched from the line 213, respectively.

The delay time of the delay circuit 15 is approximately one frame time, which is the same as that of the delay circuit 6 of the predictive encoding device.
The delayed reproduced image signal output from the delay circuit 15 is sent to the prediction signal generation circuit 1 as a supplementary pixel signal via a line 215 in order to generate a prediction signal in the prediction signal generation circuit 12 necessary for the next block.
2. The number of parallel lines for this line 215 is determined by the number of pixels included in the block, the shape of the block, the range of motion compensation, and the time allowed for determining the optimal prediction function, like the line 106a of the predictive encoding device. Addition circuit 13 via line 213a
Since the reproduced image signal supplied from the source remains blocked, it cannot be displayed correctly on a normal monitor or display. For this purpose, it is applied to the scanning inverse conversion circuit 14, returned to the original time-series image signal, and as a decoded image signal on the line 21.
It is taken out from 4.

As a modified example of the embodiments shown in FIGS. 3 and 9 above, a television signal having a color signal subcarrier such as an NTSC color TV signal in which the color signal phase is inverted between lines is scanned in FIG. When the image signal is supplied to the conversion circuit 1 as an input image signal, the delay time of the delay circuit 6 that delays the locally decoded signal is increased to about two frame times. As a result, the image signal delayed by about two frames and the image signal delayed by about one frame and about one field (for example, equivalent to 262 lines before scan conversion) by tapping in the middle of the delay circuit 6 are transmitted to the lines 106a and 106a. The signal is supplied to the prediction signal generation circuit 5 and the optimum prediction function determination circuit 8 via the signal 106b. Accordingly, in the predictive decoding device shown in FIG. 9, the delay circuit 15 is configured to have a two-frame time delay in exactly the same way as the delay circuit 6, and the taps are taken midway to detect the approximately two frames, approximately one frame, and approximately one field. The respective delayed image signals are sent to the prediction signal generation circuit 1 via a line 215.
Change it to supply 2. By making this change, it is possible to generate a large number of prediction functions using pixel points showing the same color signal subcarrier phase even for color television signals. High predictive coding efficiency can be obtained.

In the embodiment shown in FIG. 3, the prediction signal output from the two-dimensional memory 8-11 in the arithmetic unit 8-1 of the optimum prediction function determination circuit is the best prediction signal that does not use interpolation etc. Although a simple example has been chosen, a case where interpolation is used as a modification will be described below. Prediction signal X is an image signal
Assuming that it is generated using X ₁ to X ₁₆ , the predicted signal X is generally given by X= ₁₆ 〓 ⁱ⁼¹ ρ _i X _i . However, ρ ₁ to ρ ₁₆ are weighting coefficients for the image signals X ₁ to X ₁₆ , respectively. In the above-mentioned FIG. 7, since X=X ₁ is output for the predicted vector (0, 0), ρ ₁ =1, and all others are zero. However, the amount of prediction error is often smaller when using interpolated values. For example, for a motion vector (0,0), X=ρ ₁ X ₁
+ρ ₉ X ₉ , or something more complex is also possible. Here, a case of interpolation of two image signals will be explained.

FIG. 10 shows an arithmetic unit 8'-1 (representative of 8'-1 to 8'-4) configured so that two image signals can be output in parallel from the predicted signal generation memory.
This is a block diagram showing an example of the configuration.
In this figure, when a motion vector is supplied via line 108-5a, readout control circuit 8'-1
1c is two image signals to be read out, for example, X ₁ ,
Each memory address of _X9 is simultaneously supplied to the prediction signal generation memory 8'-11a via lines _AD1 and _AD2 .
These two image signals are simultaneously read out and multiplied by, for example, ρ ₁ X ₁ and ρ ₉ X ₉ , respectively, in multiplication circuits 8'-11e and 8'-11f. This multiplication result is added by an adder circuit 8'-11g, and becomes an output prediction signal X of a two-dimensional memory 8'-11. For example, as in the previous example, the motion vector is (0, 0)
If it is, then the interpolable arithmetic unit 8'
The output signal X of −1 becomes X=ρ ₁ X ₁ +ρ ₉ X ₉ . Of course, by changing the two-dimensional memory in the prediction signal generation circuit 5 to a similar configuration, the interpolation result can be changed to the line 105.
It is possible to output from. Other operations are the same regardless of whether interpolation is used or not.

FIG. 11 shows an arithmetic unit 8''-1 (representative of 8''-1 to 8''-4) which is suitable when the operating speed of the memory element used in the prediction signal generation memory is sufficiently fast for the required processing speed. A configuration example is shown in a block diagram. For example, 2
For example, in the case where the speed is high enough to read out pixels continuously, in the figure, the image signal read out first, for example, _X1 , is transferred to register 8''-11h.
, and then read out X ₉ . The output X ₁ (generally X _a ) of the register 8''-11h and the X ₉ (generally X _b ) read out later are output from the multiplier circuits 8''-11e and 8''-11f, respectively. _{The products ρ 1 _ _ _ _} The two-dimensional memory within the predicted signal generation circuit 5 is similarly configured with a high-speed memory. Other operations are the same as the example shown in FIG.

As is clear from the above description, according to the present invention, an optimal prediction function is selected by using an image signal that has been scan-converted in advance in units of two-dimensional blocks, and comparing the amount of prediction error per block for a plurality of prediction functions. , an optimal prediction signal is created from the information indicating this optimal prediction function, and a prediction error signal obtained by subtraction with the scan-converted image signal is compressed and encoded together with the information indicating the optimal prediction function. Not only can the processing speed be increased equivalently to using a one-dimensional block, but also the optimal prediction function can be determined by repeatedly using the number of calculation units corresponding to the number of pixels in the block. It is possible to improve economy by simplifying the scale of hardware and to speed up encoding processing.

[Brief explanation of drawings]

Figure 1 is a diagram explaining the principle of motion compensation for figures, and Figures 2 a and b are examples of pixel arrangement of input image blocks and pixels used for prediction, respectively, to explain the parallel calculation method. Layout example,
FIG. 3 is a block diagram showing an embodiment of the predictive encoding device according to the present invention, and FIG. 4 is a block diagram showing a specific example of the configuration of the scan conversion circuit 1 in FIG.
5 is a diagram illustrating a method of blocking a scanning signal, FIG. 6 is a block diagram showing a specific configuration example of the optimal prediction function determination circuit 8 in FIG. 3, and FIG. Arithmetic unit 8-
8 is a block diagram showing a specific example of the configuration of the predictive signal generation circuit 5 in FIG. 3, and FIG. 9 is a block diagram showing a specific example of the configuration of the predictive signal generation circuit 5 in FIG. FIG. 10 is a block diagram showing an example of the configuration of a receiving-side predictive decoding device facing the receiver. FIG. 10 is a block diagram showing another modification of the arithmetic unit shown in FIG. 7, and FIG. FIG. 7 is a block diagram showing still another modification example. In the figure, 1 is a scan conversion circuit, 2a and 6 are delay circuits, 2b is a subtraction circuit, 3 is a quantization circuit, 4 is an addition circuit, 5 is a prediction signal generation circuit, 7 is an information compression circuit, and 8 is an optimal prediction function. Judgment circuit, 1-1, 1-
2, 1-3, 1-4 are line memories, 1-5 are multiplexers, 5-1 are two-dimensional memories, 5-2 are registers, 8-1, 8-2, 8-3, 8-4 are operations unit, 8-5 is a prediction function instruction circuit, 8-6
is a pixel expansion circuit, 8-7 is an addition circuit, 8-8 is a prediction function comparison circuit, 8-9 is a prediction selection circuit, 8-1
1,8'-11,8''-11 is two-dimensional memory, 8-
11a, 8'-11a, 8''-11a are predictive signal generation memories; 8-11b, 8'-11b, 8''-11
b is a write control circuit, 8-11c, 8'-11
c, 8″-11c is a readout control circuit, 8-11
d, 8′-11d, 8″-11d are constant generation circuits,
8'-11e, 8''-11e, 8'-11f, 8''-
11f is a multiplication circuit, 8'-11g, 8''-11g is an addition circuit, 8''-11h is a register, 8-12 is an evaluation signal generation circuit, 8-12a, 8'-12a,
8''-12a is a subtraction circuit, 8-12b, 8'-12
b, 8″-12b is an arithmetic circuit, 11 is an information expansion circuit, 12 is a prediction signal generation circuit, 13 is an addition circuit,
14 is a scanning inverse conversion circuit, and 15 is a delay circuit.

Claims (1)

[Claims] 1 M pieces spanning multiple scanning lines from image signals input as time series (M is an integer of 2 or more)
scan converting means that configures a two-dimensional block consisting of pixels, and outputs image signals in an order different from the input time series; Means for comparing the prediction error amount per two-dimensional block for each of the two-dimensional prediction functions by repeatedly using at most M calculation means whose addresses can be modified using addresses corresponding to each pixel position in the two-dimensional block. and means for generating a prediction signal for the two-dimensional block according to the optimal prediction function for which the amount of prediction error is determined to be small by the comparison means, and an output of the prediction signal generation means and an output of the scan conversion means. means for generating a prediction error signal in response to the prediction error signal; generating a locally decoded image signal in response to the output of the prediction signal generation means and the output of the prediction error signal generation means; comprising local decoding means for supplying the signal to the generation means, and code conversion means for compressing and encoding at least a signal representing the optimal prediction function obtained from the comparison means and a prediction error signal obtained from the prediction error signal generation means. A predictive coding device for an image signal, characterized in that: