JPH0340949B2 - - Google Patents
Info
- Publication number
- JPH0340949B2 JPH0340949B2 JP57111021A JP11102182A JPH0340949B2 JP H0340949 B2 JPH0340949 B2 JP H0340949B2 JP 57111021 A JP57111021 A JP 57111021A JP 11102182 A JP11102182 A JP 11102182A JP H0340949 B2 JPH0340949 B2 JP H0340949B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- adhesive
- tape
- protective film
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
- H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W42/25—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons against alpha rays, e.g. for outer space applications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は半導体装置の製造方法、詳しくはセラ
ミツクパツケージに内蔵される半導体集積回路の
保護膜を形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a protective film for a semiconductor integrated circuit built into a ceramic package.
(2) 技術の背景
セラミツクパツケージにおいて、セラミツクに
含まれるウラン、トリウム等の放射性元素からα
線が放射され、このα線がセラミツクパツケージ
の内蔵された半導体チツプ（以下チツプと略称す
る）のメモリまたはビツト線を通ると、通つた跡
に＋と−の電荷が発生し、それによつて蓄えられ
た情報が逆転するソフトエラーは知られている。(2) Background of technology In ceramic packaging, α is removed from radioactive elements such as uranium and thorium contained in ceramic.
When a ray is emitted, and this alpha ray passes through the memory or bit line of a semiconductor chip (hereinafter referred to as a chip) built into a ceramic package, + and - charges are generated in the path that it passes through, which causes it to accumulate. Soft errors are known in which the received information is reversed.
かかるソフトエラー防止するには、チツプ上に
なんらかの物を配置し、その物によつてα線をブ
ロツク（阻止）するしかない。そのために現在と
られている方法を説明すると、第１図に示される
如く、セラミツクベース基体１のキヤビテイ２内
に付着されたチツプ３上にポリイミド（以下PI
と略記する）溶液を滴下し（ドロツピング）、そ
れをチツプ全面上に拡げた後硬化させて（キユア
して）形成した保護膜４によつてチツプをα線か
ら保護する。なお同図において５はボンデイング
ワイヤを示す。 The only way to prevent such soft errors is to place something on the chip and use that object to block the alpha rays. To explain the method currently used for this purpose, as shown in FIG. 1, polyimide (hereinafter referred to as PI
The chip is protected from alpha rays by the protective film 4 formed by dropping a solution (abbreviated as ``dropping''), spreading it over the entire surface of the chip, and then curing it. Note that in the figure, 5 indicates a bonding wire.
上記の如くにして形成されたPIの保護膜４は、
上に凸に（山なり）に形成され、チツプの端の部
分（チツプの周縁の近くの部分）で保護膜は薄く
なる。その結果、チツプの端の部分でメモリ等が
α線に対し十分に保護されない。 The PI protective film 4 formed as described above is
It is formed in an upwardly convex (mountain-like) manner, and the protective film becomes thinner at the edge of the chip (near the periphery of the chip). As a result, memories and the like at the edges of the chip are not sufficiently protected against alpha rays.
かくして、チツプの端部分においても十分な厚
さの保護膜を設けるために、PIテープを用いる
技術が開発され、併せてPIテープをいかなる接
着剤を用いてチツプ上にはり付けるかが研究され
た。 Thus, in order to provide a sufficiently thick protective film even at the edges of the chip, a technique using PI tape was developed, and research was also conducted on what kind of adhesive should be used to attach the PI tape to the chip. .
第１図に示すセラミツクパツケージを完成する
には、480℃程度の温度でガラス封止（ガラス接
着剤を用いるキヤツプのろう付け）をなす。この
480℃程度の温度に耐えうる有機ポリマーはPIし
かないので、PIテープの接着にPI接着剤を用い
ることがなされる。 To complete the ceramic package shown in Figure 1, glass sealing (brazing the cap using glass adhesive) is performed at a temperature of approximately 480°C. this
Since PI is the only organic polymer that can withstand temperatures of around 480°C, PI adhesives are used to bond PI tapes.
かくして、現在とられている耐α線保護膜の形
成方法においては、PI接着剤を少量チツプ上に
ドロツピングし、それをチツプ上に拡げ、次いで
PIテープを接着剤の上におき、加熱してPI接着
剤をキユアし、PIテープをはり付ける。 Thus, in the currently used method of forming an α-ray resistant protective film, a small amount of PI adhesive is dropped onto the chip, it is spread over the chip, and then
Place the PI tape on top of the adhesive, heat to cure the PI adhesive, and apply the PI tape.
(3) 従来技術と問題点
上記の加熱キユアにおいて、PI接着剤とチツ
プの接着剤が強すぎるため、PI接着剤の硬化収
縮時に接着剤とチツプの接着が不安定になること
が製品の最終検査で見出された例がある。しか
し、現在セラミツクパツケージの製造には480℃
前後でのガラス封止は不可欠であるので、PIに
代る接着剤が見出されるまではそれを用いざるを
えない状況にある。(3) Conventional technology and problems In the heating cure described above, the adhesive between the PI adhesive and the chip is too strong, so when the PI adhesive hardens and shrinks, the adhesion between the adhesive and the chip becomes unstable. There are examples that have been found through testing. However, currently, ceramic packages are manufactured at 480°C.
Since glass sealing at the front and rear is essential, we have no choice but to use that adhesive until an alternative adhesive to PI is found.
(4) 発明の目的
本発明は上記従来の問題点に鑑み、PIテープ
とPI接着剤とを用いチツプのための耐α線保護
膜を形成する方法において、チツプと接着剤との
間に安定した接着力を発生させうる保護膜の形成
方法を提供することを目的とする。(4) Purpose of the Invention In view of the above-mentioned conventional problems, the present invention provides a method for forming an α-ray-resistant protective film for a chip using a PI tape and a PI adhesive. An object of the present invention is to provide a method for forming a protective film that can generate a strong adhesive force.
(5) 発明の構成
そしてこの目的は本発明によれば、PIテープ
上にPI接着剤を塗布した後にチツプ上にはり付
け、加熱加圧によりPIテープをチツプ上に接着
する方法を提供することによつて達成される。ま
た、上記工程において、チツプ上に予めなんらか
の材料で保護膜を形成しておいてもよい。(5) Structure of the Invention According to the present invention, the object is to provide a method of applying a PI adhesive onto a PI tape, pasting it onto a chip, and then bonding the PI tape onto the chip by applying heat and pressure. achieved by. Further, in the above step, a protective film may be formed on the chip in advance using some material.
(6) 発明の実施例 以下本発明の実地例を図面によつて詳述する。(6) Examples of the invention Practical examples of the present invention will be explained in detail below with reference to the drawings.
第２図に本発明の方法を実施する工程における
セラミツクパツケージの要部が断面で示され、同
図および次の第３図において既に図示した部分と
同じ部分は同一符号を付して表示する。 FIG. 2 shows a cross section of the main parts of a ceramic package in the process of carrying out the method of the present invention, and in this figure and the following FIG.
セラミツクベース基体１のキヤビテイ２にはチ
ツプ３が付着され、ボンデイングワイヤ５が接着
されるまでは、従来技術における工程と同様であ
る。他方、PIテープを用意し、その上に液状の
PI接着剤を塗布し、取り扱い中に接着剤が作業
者の指等によつてぬぐわれることのないよう暫時
放置して接着剤に含まれる溶剤を部分的に発揮さ
せる。この状態で、接着剤は若干べたつくが、テ
ープから剥がれることはない。 The process is similar to that in the prior art until the chip 3 is attached to the cavity 2 of the ceramic base substrate 1 and the bonding wire 5 is bonded. On the other hand, prepare PI tape and apply liquid on it.
Apply the PI adhesive and leave it for a while to prevent the adhesive from being wiped off by the operator's fingers during handling, so that the solvent contained in the adhesive can be partially released. At this point, the adhesive will be slightly sticky, but will not peel off from the tape.
次にPIテープをチツプにはり付ける。第２図
にはチツプ３上にはり付けられたテープ７をPI
接着剤６（誇張的に図示される）と共に示す。 Next, attach PI tape to the chip. Figure 2 shows tape 7 pasted on chip 3.
It is shown with an adhesive 6 (shown exaggeratedly).
次いで、480℃程度の温度でキユアし、100ｇ／
mm2程度の力でPIテープ７をチツプ３に向けて圧
着して保護膜を形成する。この圧着によつて、チ
ツプのデバイスを損傷することがなく、PIテー
プはチツプ３上に均一にはり付けられる。かかる
保護膜を検査したところ、チツプ３とPIテープ
との間に安定した接着力が得られたことが確認さ
れた。なお、上記したPIテープ、PI接着剤は市
販の製品を用いる。 Next, it is cured at a temperature of about 480℃, and 100g/
The PI tape 7 is pressed against the chip 3 with a force of about mm 2 to form a protective film. This crimping allows the PI tape to be applied uniformly onto the chip 3 without damaging the device of the chip. When this protective film was inspected, it was confirmed that stable adhesive force was obtained between Chip 3 and the PI tape. Note that commercially available products are used for the above-mentioned PI tape and PI adhesive.
本発明の他の実施例においては、上記したPI
テープのはり付けの前に、チツプ３上に、PI、
りん・シリケートガラス（PSG）、二酸化シリコ
ン等のウエハコーテイング８を通常の技術で形成
しておく。かくすることによつて、チツプ上に既
に形成されたPSG膜等が前記したPIの硬化収縮
から保護されることが確認された。 In another embodiment of the invention, the above-mentioned PI
Before pasting the tape, place PI,
A wafer coating 8 of phosphorous silicate glass (PSG), silicon dioxide, etc. is formed using conventional techniques. It was confirmed that by doing so, the PSG film etc. already formed on the chip were protected from the curing shrinkage of the PI described above.
なお以上説明した実施例において、PI接着剤
の塗布のときの膜厚を５〜20μｍ、PIテープの厚
さを50〜125μｍ、ウエハコーテイングの膜厚を
５〜15μｍに設定して良好な結果を得た。 In the examples described above, good results were obtained by setting the film thickness when applying the PI adhesive to 5 to 20 μm, the thickness of the PI tape to 50 to 125 μm, and the film thickness of the wafer coating to 5 to 15 μm. Obtained.
(7) 発明の効果
以上、詳細に説明したように、本発明の方法に
よるときは、チツプをα線から守る保護膜が、安
定した接着力でもつてチツプに形成され、セラミ
ツクパツケージの信頼性向上に効果大である。(7) Effects of the Invention As explained in detail above, when the method of the present invention is used, a protective film that protects the chip from alpha rays is formed on the chip with stable adhesive strength, improving the reliability of the ceramic package. It is highly effective.
第１図は従来技術によりPI接着剤をキユアし
たときのセラミツクパツケージの要部の断面図、
第２図と第３図とは本発明の方法を実施する工程
におけるセラミツクパツケージの要部の断面図で
ある。
１……セラミツクベース基体、２……キヤビテ
イ、３……半導体チツプ、４，６……PI接着剤、
７……PIテープ、８……ウエハコーテイング。
Figure 1 is a cross-sectional view of the main parts of a ceramic package when PI adhesive is cured using the conventional technique.
FIGS. 2 and 3 are cross-sectional views of essential parts of a ceramic package in the process of carrying out the method of the present invention. 1... Ceramic base substrate, 2... Cavity, 3... Semiconductor chip, 4, 6... PI adhesive,
7...PI tape, 8...wafer coating.
Claims (1)
護膜を形成する方法において、ポリイミド接着剤
を塗布したポリイミドテープを前記半導体チツプ
上に置き、加熱圧着によつて前記ポリイミドテー
プを半導体チツプにはり付けることを特徴とする
半導体装置の製造方法。1. A method for forming a protective film on a semiconductor chip incorporated in a package includes placing a polyimide tape coated with a polyimide adhesive on the semiconductor chip, and attaching the polyimide tape to the semiconductor chip by heat and pressure bonding. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57111021A JPS592353A (en) | 1982-06-28 | 1982-06-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57111021A JPS592353A (en) | 1982-06-28 | 1982-06-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS592353A JPS592353A (en) | 1984-01-07 |
| JPH0340949B2 true JPH0340949B2 (en) | 1991-06-20 |
Family
ID=14550376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57111021A Granted JPS592353A (en) | 1982-06-28 | 1982-06-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS592353A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59121956A (en) * | 1982-12-28 | 1984-07-14 | Tomoegawa Paper Co Ltd | Heat-resisting adhesive sheet |
-
1982
- 1982-06-28 JP JP57111021A patent/JPS592353A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS592353A (en) | 1984-01-07 |
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