JPH0341849B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a microprogram loading method, and more particularly, the present invention relates to a microprogram loading method, in which a microprogram that has a service processor and is stored in an external storage device under an input/output channel device is loaded into a central processing unit. and a microprogram loading method for storing in the control memory of an input/output channel device.

[Background of the invention]

Conventionally, the initial microprogram loading method of a data processing device that employs a microprogram method is a floppy disk or hard disk connected to a service processor, as described in Japanese Patent Application Laid-Open No. 58-208850. A method is known in which a microprogram held in an external storage device is read out and stored in a control memory of a central processing unit or the like. In addition, on the central processing unit side, in addition to the control memory that stores microprograms, there is a read-only memory (ROM) for initial microprogram load (IMPL).
It is normal to have However, such conventional technology has the following problems.

(1) In addition to the external storage device connected to the input/output channel device, it is necessary to provide an external storage device for holding the microprogram under the service processor, resulting in high system costs.

(2) Usually a service processor and a central processing unit.
The data transfer rate between input and output channel devices is slow, so the IMPL time is long.

(3) IMPL of central processing unit and input/output channel device
The cost is high because the control unit needs to be equipped with a ROM. Furthermore, in a system consisting of a plurality of central processing units and a plurality of input/output channel devices, if a microprogram stored in the ROM is defective, all the ROMs must be replaced.

(4) Since multiple central processing units and multiple input/output channel devices cannot be IMPLed at the same time, the IMPL time for the entire system is long.

[Purpose of the invention]

An object of the present invention is to connect a central processing unit and an input/output channel via a shared storage device from an external storage device connected to an input/output channel device without providing an external storage device for holding a microprogram under a service processor. The objective is to reduce system costs and shorten the time required for IMPL by enabling equipment to perform IMPL.

[Summary of the invention]

The first feature of the present invention is that the microprograms for the central processing unit and the input/output channel device are held in an external storage device such as a disk device connected to the input/output channel device, and the microprogram is held under the service processor. This eliminates the need for a dedicated external storage device.

The second feature of the present invention is that the central processing unit and the input/output channel device do not have a ROM for IMPL.
Immediately after the system is powered on, the service processor executes a boot program (second boot program) that stores the microprogram in the external storage device from the ROM in the service processor into the control memory of the central processing unit and input/output channel device via the shared storage device. microprogram) is stored in advance in the control memory of the central processing unit and input/output channel device, and the IMPL of each device is executed by this boot program.

Furthermore, a third feature of the present invention is that the microprograms for the central processing unit and the input/output channel device read by the boot program stored in the control memory of the input/output channel device are once expanded onto the shared storage device. This enables a plurality of central processing units and a plurality of input/output channel devices to execute IMPL in parallel using the boot program.

[Embodiments of the invention]

Next, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Note that FIG. 1 shows only one central processing unit and one input/output channel device to simplify the explanation.

The service processor 1 is connected to a central processing unit 3 and an input/output channel device 4, and is also connected to a console display 2. The shared storage device 6 is located between the central processing unit 3 and the input/output channel device 4. There are a plurality of input/output control devices 23 below the input/output channel device 4, and the disk control device 22 is located in one of these. A disk device 5 is connected to the disk control device 22, and a central processing unit microprogram 24 and an input/output channel device microprogram 25 are stored in a part of the disk device 5.

Inside the service processor 1, there is a central processing unit 3.
There is a ROM 7 that holds a boot program 8 for the input/output channel device 4 and a boot program 9 for the input/output channel device 4.
The control storage register 16 of the central processing unit 3 and the input/output channel device 4 via the data register 10
is connected to the control storage register 19 of. The control storage address control circuit 11 in the service processor 1 also controls the control storage address register 14 of the central processing unit 3 and the input/output channel device 4.
is connected to the control storage address register 20 of.
The control memory 13 of the central processing unit 3 includes the control memory in register 16 and the control memory address register 1.
4 and is connected to the processor 12 via a control storage data register 15. Similarly, in the input/output channel device 4, the control memory 18 is connected to the processor 17 through the control memory in register 19 and the control memory address register 20 as well as the control memory data register 21.

The address register 29 in the shared storage device 6 is
The shared memory 26 is connected to the processors 12 and 17, and is connected to the disk controller 22 via a data buffer 27. The data register 28 on the output side of the unused memory 26 is connected to the control storage in register 16 of the central processing unit 3 and the control storage in register 19 of the input/output channel device 4 .

Next, the operation shown in FIG. 1 will be explained. Immediately after powering on the system, service processor 1
The boot program 8 of the central processing unit 3 in the ROM 7 is stored in the control memory 13 of the central processing unit 3 via the data register 10 and the control memory register 16. At this time, the address of the control memory 13 is controlled by the control memory address control circuit 11 in the service processor 1 via the control memory address register 14. The boot program 8 stored in the control memory 13 of the central processing unit 3 is stored in the unused memory 26.
After the microprogram 24 of the central processing unit 3 is stored in the control memory 1, the microprogram 24 is stored in the control memory 1.
It is used for storing data in 3.

Next, the service processor 1 stores the boot program 9 of the input/output channel device 4 in the ROM 7 into the control memory 18 of the input/output channel device 4 via the data register 10 and the control memory register 19. In this case as well, the address of the control memory 18 is controlled by the control memory address control circuit 11 in the service processor 1 via the control memory address register 20. The boot program stored in the control memory 18 of this input/output channel device 4 is the microprogram 24, 25 in the disk device 5.
is stored in the shared memory 26, and after the storage,
Microprogram 25 of input/output channel device 4
It is used to store in the control memory 18.

When the boot program 9 is stored in the control memory 18 of the input/output channel device 4, the service processor 1 starts the processor 17 of the input/output channel device 4. The processor 17 starts the boot program 9 in the control memory 18, reads out the microprograms 24 and 25 in the disk device 5 via the disk controller 22, and stores the data buffer 27.
The data is written to the shared storage 26 in the shared storage device 6 via the shared storage device 6. At this time, the address of the shared memory 26 is controlled by the processor 17 via the address register 29, and the microprograms of the central processing unit 3 and the input/output channel device 4 are stored at fixed addresses in the control memory 26, respectively.

Microprograms 24 and 25 in the shared memory 26
Once stored, the service processor 1 starts the processor 12 of the central processing unit 3. The processor 12 starts the boot program 8 in the control memory 13, reads out the microprogram 24 of the central processing unit 3 in the control memory 26 via the address register 29 via the data register 28, and controls it via the control memory register 16. It is stored in the memory 13. Next, the service processor 1 starts the processor 17 of the input/output channel device 4, and the processor 17 executes the microprogram 25 of the input/output channel device 4 on the control memory 26 under the control of the boot program 9 of the control memory 18. , read via the data register 28 and stored in the control memory 18 via the control memory in register 19.

In the above-mentioned operation, when service processor 1 processor 12 and processor 17 start up at the same time, both processors execute the corresponding control memory 1 in parallel processing of the microprogram in shared memory 26.
3 or 18 can be stored. That is,
While one processor stores the contents of the control store in register in control store, the other processor stores the contents of shared memory in the control store in register.

Although one embodiment of the present invention has been described above,
In FIG. 1, the shared memory 26 is not hardware dedicated to IMPL, but may be a buffer memory (not shown) for conversation between the central processing unit 3 and the input/output channel device 4 used during normal operation.
Further, it may be an area dedicated to the main memory or hardware of the main memory.

Furthermore, in a system consisting of a plurality of central processing units, after the power is turned on, the service processor 1 stores the boot program 8 of the central processing units in the control memory of all central processing units, and stores the boot program 8 of the central processing units in the shared memory 26. After the microprogram 24 is stored, the processors of all central processing units may be activated. This allows multiple central processing units to execute IMPL in parallel. The same applies to systems consisting of multiple input/output channel devices, but since there is only one input/output channel device that controls the disk device that stores the microprogram, in this case, the input/output channel device controls the microprogram. After storing the program in the shared memory 26, all input/output channel devices may store the microprogram in the control memory in parallel.

In addition, in FIG. 1, the control memories 13, 18
Although it is assumed that both the boot programs 8 and 9 and the microprograms 24 and 25 exist in the boot program, the microprogram may overwrite the boot program.

〔Effect of the invention〕

With the configuration as described above, the following effects can be obtained in the present invention.

(1) There is no external storage for storing microprograms under the service processor, but the microprograms for the central processing unit and input/output channel devices are stored in an external storage device connected to the input/output channel device, and from there. By making it possible to perform IMPL, system costs can be reduced.

(2) In order to temporarily store the microprograms of the central processing unit and input/output channel devices in a shared memory that can be accessed by both devices, multiple central processing units and multiple input/output channel devices are operated in parallel.
Can run IMPL. Therefore, the IMPL time can be shortened.

(3) Since the service processor stores the boot program for IMPL in advance in the control memory of the central processing unit and input/output channel device, each device does not need to have a ROM dedicated to the boot program, reducing costs. Furthermore, since the boot program is held in one place, it is easy to take measures against program defects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the microprogram loading method of the present invention. 1... Service processor, 2... Console display, 3... Central processing unit, 4... Input/output channel device, 5... Disk device, 6... Shared storage device, 7... ROM, 8... Central Processing device boot program, 9... Input/output channel device boot program, 13, 18... Control memory, 22
... disk control device, 23 ... input/output control device, 24 ... central processing unit microprogram,
25...I/O channel device microprogram, 26...Control memory.

Claims (1)

[Claims] 1. A central processing unit having a control memory for storing microprograms, an input/output channel device having a control memory for storing microprograms, an external storage device connected to the input/output channel device, and a service processor. In a data processing system consisting of a data processing system, a shared storage device accessible from the central processing unit and the input/output channel device is provided, and a microprogram (hereinafter referred to as a first microprogram) stored in the control memory of the central processing unit and the input/output channel device is provided. a microprogram (hereinafter referred to as a second microprogram) for loading the first microprogram into the service processor; Immediately after input, the service processor first stores the second microprogram in the control memory of the central processing unit and the input/output channel device, and then the input/output channel device stores the second microprogram in the external storage device. storing a first microprogram in the shared storage device;
Next, the central processing unit and the input/output channel device store the first microprogram of the shared storage device into their respective control memories using the second microprogram.