JPH0342505B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device having grid lines for dividing a plurality of semiconductor elements formed on the main surface of a semiconductor substrate into individual semiconductor pieces.

(Prior art) When forming a large number of semiconductor elements (integrated circuits) on the main surface of a semiconductor substrate (silicon wafer), semiconductor element boundaries are also formed in a lattice pattern in each photolithography process. It's called the grid line.

FIG. 1 is a cross-sectional view of the vicinity of a grid line of a conventional semiconductor device using platinum silicide as an ohmic contact. In this Figure 1, 1
2 is a semiconductor substrate, 2 is a field oxide film, 3 is a CVD film for passivation, and 4 is a platinum silicide layer.

In this FIG. 1, area A corresponds to the above-mentioned grid line. Area A of this grid line
is usually used to facilitate the division of a large number of semiconductor devices into individual semiconductor pieces, and to alleviate the thermal stress that occurs between the mask oxide film and the semiconductor substrate in the heat treatment that follows the photolithography process. In each photolithography process, the mask oxide film is removed in a grid pattern to expose the surface of the semiconductor substrate.

Therefore, for example, in a semiconductor device in which an ohmic contact is formed with platinum silicide, the region A of the grid line opened in the contact photolithography process (exposing the surface of the semiconductor substrate) is also affected by the formation of the platinum silicide layer. In the process, a platinum silicide layer 4 is simultaneously formed as shown in FIG.

The platinum silicide layer 4 in the grid line area A is likely to peel off during subsequent steps, such as hydrofluoric acid dipping, and each die is It remains in a straight line around the periphery and tends to peel off, and the peeled pieces adhere to other patterns and metal wires of bonding wires in the assembly process.

Therefore, conventionally, the above-mentioned peeled off pieces have caused short circuits, resulting in a decrease in yield.

Therefore, it may be possible to prevent the platinum silicide layer 4 from being formed in the grid line area A in FIG. 1 by leaving the thermal oxide film formed in the final heat treatment step in the grid line area A. .

However, in this method, the semiconductor substrate warps due to the thermal stress generated between the mask oxide film and the semiconductor substrate, which causes inconvenience in subsequent steps.

By preventing thermal stress occurring between the mask oxide film and the semiconductor substrate and leaving the thermal oxide film formed in the last heat treatment step in the grid line area A in FIG. In order to prevent the platinum silicide layer 4 from being formed on A, it is conceivable to arrange only the grid lines of the contact photolithography process independently at the periphery of the main surface of the semiconductor substrate (Japanese Patent Application No. 56-49265). (Improved grid line structure described in JP-A-57-164546).

A cross-sectional view of the vicinity of the grid line of a semiconductor device having this improved grid line structure is shown in FIG. In this FIG. 2, 1 is a semiconductor substrate, 2
is for field oxide film, 3 is for passivation
A CVD film, 4 is a platinum silicide layer, region A is a grid line for other photolithography processes other than the contact photolithography process, and region B is a grid line for the contact photolithography process.

However, in this method, the grid lines for the contact photolithography process are arranged at the periphery of the main surface of the semiconductor substrate 1 as shown in area B in FIG. The disadvantage is that it requires a larger area as shown in area C of FIG. 1 than the conventional structure shown in area A of the grid line in FIG.

(Object of the Invention) The present invention has been made to eliminate the above-mentioned conventional drawbacks, and it not only prevents peeling of the platinum silicide layer and reduces yield due to circuit shorting, but also prevents warpage of semiconductor substrates. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent a decrease in the degree of integration.

(Structure of the Invention) The present invention provides a method for manufacturing a semiconductor device in which a grid line portion of a substrate is covered with an oxide film thinner than a thick field oxide film in the periphery when forming electrodes of a device. A film is formed on the grid line portion of the substrate, an opening is formed in the thin oxide film at the center of the grid line, and the electrode of the device is formed with a metal layer, and then the metal layer remains in the opening when the electrode is formed. By forming a passivation film, the heated electrode metal is covered with a passivation film in a state separated from the passivation film around the grid line.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. FIG. 3a is a sectional view showing the structure of a semiconductor device manufactured according to one embodiment, and is a sectional view taken along line a-a in FIG. 3b. FIG. 3b is a plan view.
3a and 3b show the vicinity of the grid line of a semiconductor device using platinum silicide for ohmic contacts and shot key contacts.

In both figures 3a and 3b, 11
1 is a semiconductor substrate, and 12 is a thick oxide film formed thereon. This oxide film 12 is generally called a field oxide film.

In addition, 13 is a PSG formed by the CVD method.
14 is a binary alloy of the semiconductor substrate 11 and a metal, for example, a platinum silicide layer. Furthermore, 15 is a thin oxide film formed in the final heat treatment step.

In FIGS. 3a and 3b, the platinum silicide layer 14 is completely covered with the passivation film 13. Further, the width l of the platinum silicide layer 14, that is, the grid line width in the contact photolithography process is set to be 10 to 20 μm, which is sufficiently narrower than the width of the cutting margin produced in the subsequent scribing process.

The semiconductor device described above is shown in FIGS. 4 to 6.
It is manufactured by the following manufacturing method described with reference to the drawings.

FIG. 4 is a cross-sectional view of the state immediately before contact photolithography after all the diffusion steps have been completed.

In this FIG. 4, 11 is a semiconductor substrate, 12
1 is a thick oxide film, and 15 is a relatively thin oxide film formed on the portion A forming the grid line. This relatively thin oxide film 15 is formed at the same time as the impurity diffusion region (not shown) is formed on the semiconductor substrate 11. This relatively thin oxide film 1
5 causes the semiconductor substrate 11 to warp slightly.

Next, FIG. 5 shows a state in which the contact photolithography process has been completed. In this photolithography step, an opening 21 is formed in the center of the relatively thin oxide film 15 (the center of the grid line). The warpage of the semiconductor substrate 11 is repaired by the opening portion 21.

At this time, the width of the opening portion 21 (indicated by l in FIG. 5) is usually 50 μm to 100 μm, which is the width of the grid line formed before the contact photolithography process, that is, the width of area A (indicated by L in FIG. 5). It is set to be sufficiently thin, about 10 μm to 20 μm.

Next, a metal layer as an electrode material, such as platinum, is deposited on the entire surface including the opening portion 21 and heat-treated.
Then, in the opening portion 21, the semiconductor substrate 11
A binary alloy of silicon (ie silicon) and platinum is formed, leaving other areas as platinum.

Next, using a platinum etchant such as a mixture of nitric acid and hydrochloric acid, the platinum is removed by etching.
The binary alloy of silicon and platinum formed in the opening portion 21 remains without being removed.

This state is shown in FIG. In FIG. 6, 14 is the residual silicon-platinum binary alloy (ie, platinum silicide layer).

Next, the platinum silicide layer 1 on the semiconductor substrate 11 is
4 and the oxide films 12 and 15 as a passivation film (not shown), for example, is formed as a passivation film, and a part of the PSG film on the grid line is removed by etching using a photomask (not shown), thereby obtaining the semiconductor device shown in FIG. . At this time, the PSG film on the platinum silicide layer 14 is left separated from the PSG film on the oxide film 12.

As explained above, in the semiconductor device obtained by the semiconductor device manufacturing method of the above embodiment, the easily peelable platinum silicide layer 14 is covered with the passivation film 13, and in the subsequent steps, hydrogen fluoride, etc. The platinum silicide layer 14 is no longer exposed to the etching solution.

Therefore, there is an advantage that peeling of the platinum silicide layer 14 does not occur and the peeled pieces do not cause short circuits and reduce yield.

Furthermore, since the width l of the platinum silicide layer 14 existing in the area A of the grid line is as narrow as about 10 μm to 20 μm, when the scribing process is performed using a cutter blade of about 30 μm, for example, the platinum silicide layer 14 is formed on the scribe cross section after scribing. 1
4 remains, and the platinum silicide layer 14 is completely cut off.

Therefore, there is an advantage that thin line-like peeling of the platinum silicide layer 14 on the grid line due to scribe residue will not occur, resulting in short circuits and a decrease in yield.

Furthermore, if the platinum silicide layer 14 is covered with the passivation film 13, when one of the grid lines (vertical line or horizontal line) is scribed, the platinum silicide layer 14 remaining on the remaining grid line portion will peel off. can also be prevented.

Furthermore, by separating the passivation film 13 from the passivation film 13 around the grid line and leaving it on the platinum silicide layer 14,
When the passivation film 13 on the platinum silicide layer 13 is cut during scribing, it is possible to prevent the passivation film 13 around the grid line from being adversely affected.

Furthermore, as is clear from the above-described manufacturing method, there is an advantage that warpage of the semiconductor substrate 11 is eliminated. Moreover, according to this method, since the openings are formed in the grid line portions so as to subdivide the substrate in a grid pattern, the thermal stress during the formation of the oxide film 15 is sufficiently released, and the substrate 11 is reliably formed. You can remove warpage.

Further, according to the embodiments of the present invention, these advantages can be obtained without increasing the area compared to the grid line structure of a conventional semiconductor device, so that the disadvantage of lowering the degree of integration of the semiconductor device can be avoided. do not have.

In the above embodiments, the metal layer is a platinum silicide layer. ), the present invention can also be applied. Furthermore, the present invention can be applied to both multi-layer wiring and single-layer wiring.

(Effects of the Invention) As detailed above, according to the method of manufacturing a semiconductor device of the present invention, a relatively thin oxide film is formed on the main surface of the semiconductor substrate at the grid line, and the oxide film is thickened at the center of the grid line. forming an opening,
Since the electrode metal remaining in the opening is covered with a passivation film, peeling of the electrode metal during hydrofluoric acid dipping and scribing can be reliably prevented, and warpage of the substrate can be reliably removed. Thin line-like peeling due to metal scribe residue can also be eliminated, and these can be obtained without increasing the grid line area compared to the conventional method. Furthermore, since the passivation film covers the electrode metal separately from the passivation film around the grid line, when the passivation film on the electrode metal is cut during scribing, there is no possibility that the passivation film around the grid line will be adversely affected. can also be prevented.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional semiconductor device, FIG. 2 is a sectional view of a conventional improved semiconductor device, and FIG. 3a is a sectional view of a semiconductor device obtained by the method of manufacturing a semiconductor device of the present invention. 3B is a plan view of the same semiconductor device as described above, and FIGS. 4 to 6 are process explanatory diagrams for explaining one embodiment of the method for manufacturing the semiconductor device of the present invention. 11...Semiconductor substrate, 12...Thick oxide film, 1
3... Passivation film, 14... Platinum silicide layer, 15... Thin oxide film, 21... Opening portion, A... Grid line area.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device in which a grid line portion of a substrate is covered with an oxide film thinner than a surrounding thick field oxide film when forming electrodes of a device, comprising: a step of forming an opening in the grid line portion of the substrate; a step of forming an opening in the thin oxide film at the center of the grid line; a step of forming an electrode of the element with a metal layer; A method for manufacturing a semiconductor device, comprising the step of forming a passivation film on an electrode metal remaining on a grid line in a state where the passivation film is separated from the passivation film around the grid line. 2 The grid line part is 50 to 100 μm,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the opening portion has a diameter of 10 to 20 μm.