Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPH0342507B2 - - Google Patents
[go: Go Back, main page]

JPH0342507B2 - - Google Patents

Info

Publication number
JPH0342507B2
JPH0342507B2 JP58175794A JP17579483A JPH0342507B2 JP H0342507 B2 JPH0342507 B2 JP H0342507B2 JP 58175794 A JP58175794 A JP 58175794A JP 17579483 A JP17579483 A JP 17579483A JP H0342507 B2 JPH0342507 B2 JP H0342507B2
Authority
JP
Japan
Prior art keywords
insulating film
semiconductor wafer
semiconductor
metal layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58175794A
Other languages
Japanese (ja)
Other versions
JPS6066830A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP58175794A priority Critical patent/JPS6066830A/en
Publication of JPS6066830A publication Critical patent/JPS6066830A/en
Publication of JPH0342507B2 publication Critical patent/JPH0342507B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00Cutting or separating of wafers, substrates or parts of devices

Landscapes

  • Dicing (AREA)

Description

【発明の詳細な説明】技術分野 この発明は半導体装置の製造方法に関し、より
詳しくは半導体ウエーハから多数の半導体ペレツ
トを製造する方法に関する。背景技術 トランジスタ、ダイオード等の半導体装置を製
造する場合、第1図に示すように、一枚の半導体
ウエーハ1に多数の半導体素子2を形成し、表裏
面に金属層3,4を形成したのち、各半導体素子
2,2間を切断分離して、多数の半導体ペレツト
を製造する工程を経て製造する。こゝで、表面の
金属層3は各半導体素子2毎に独立しているが、
裏面の金属層4は一様に形成されており連続して
いることが多い。また、各半導体素子2,2間を
切断する場合、一般にダイシング法によることが
多い。ところが、裏面の金属層4が銀等の軟質の
ものである場合、ダイシングソウで完全カツトし
ようとすると、軟質の銀がダイシングブレードに
目詰りして、ダイシングが不可能になる。このた
め、第2図に示すように、半導体ウエーハ1の裏
面に接着テープ5を貼り付け、半導体ウエーハ1
の表面から所定の残り代tを設けてダイシング溝
6を形成した後、半導体ウエーハ1に撓屈力を作
用させて、第3図に示すように、前記ダイシング
溝6部分から破断7するブレーキング工程を経
て、多数の半導体ペレツトを製造している。しか
しながら、半導体素子2の寸法が1mm□以下の小
型のものでは、半導体ウエーハ1に大きな撓屈力
を作用させることができないこと、および裏面の
金属層4が軟質であるために、確実にブレーキン
グが行なえず、複数個の半導体ペレツトが金属層
4で連結状態になつた、いわゆるアベツク不良が
発生しやすかつた。
DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a large number of semiconductor pellets from a semiconductor wafer. BACKGROUND ART When manufacturing semiconductor devices such as transistors and diodes, as shown in FIG. , each semiconductor element 2 is cut and separated to produce a large number of semiconductor pellets. Here, the surface metal layer 3 is independent for each semiconductor element 2, but
The metal layer 4 on the back surface is formed uniformly and is often continuous. Moreover, when cutting between the semiconductor elements 2, 2, a dicing method is generally used in many cases. However, if the metal layer 4 on the back side is made of soft material such as silver, if an attempt is made to completely cut it with a dicing saw, the soft silver will clog the dicing blade, making dicing impossible. Therefore, as shown in FIG. 2, an adhesive tape 5 is pasted on the back surface of the semiconductor wafer 1.
After forming the dicing groove 6 with a predetermined remaining margin t from the surface, a bending force is applied to the semiconductor wafer 1 to break it 7 from the dicing groove 6 portion as shown in FIG. Through this process, a large number of semiconductor pellets are manufactured. However, if the semiconductor element 2 is small with dimensions of 1 mm□ or less, it is impossible to apply a large bending force to the semiconductor wafer 1, and the metal layer 4 on the back side is soft, so it is difficult to brake reliably. Therefore, a so-called average defect, in which a plurality of semiconductor pellets become connected by the metal layer 4, is likely to occur.

そこで、半導体ウエーハのスクライブラインに
沿つて絶縁膜を形成し、その上から全面に半田層
を形成した後、半田層を加熱溶融して溶融半田の
凝集力でもつて絶縁膜上の半田層を不連続状態と
し、次いで絶縁膜を溶解除去する薬品に浸漬し
て、絶縁膜をその上の半田層とともに除去する方
法が提案されている(特開昭51−58862号公報)。
Therefore, after forming an insulating film along the scribe line of the semiconductor wafer and forming a solder layer over the entire surface, the solder layer is heated and melted, and the cohesive force of the molten solder is used to bind the solder layer on the insulating film. A method has been proposed in which the insulating film is brought into a continuous state and then immersed in a chemical that dissolves and removes the insulating film, thereby removing the insulating film together with the solder layer thereon (Japanese Patent Application Laid-Open No. 58862/1983).

しかしながら、この方法によると、絶縁膜の薬
品による溶解除去が必要であるのみならず、薬品
の洗浄除去および乾燥工程が必要で工程が煩雑に
なるという問題点があつた。発明の開示 〔目的〕 この発明は、半導体素子の寸法が小さくかつ裏
面の金属層が銀等の軟質材料よりなる場合であつ
ても前述のように絶縁膜を除去することなく、ア
ベツク不良を生じない半導体装置の製造方法を提
供することを目的とする。
However, this method has the problem that not only is it necessary to dissolve and remove the insulating film using chemicals, but also cleaning and removal of chemicals and drying steps are required, making the process complicated. DISCLOSURE OF THE INVENTION [Purpose] The present invention provides a method for reducing average defects without removing the insulating film as described above even when the dimensions of the semiconductor element are small and the metal layer on the back surface is made of a soft material such as silver. The purpose of the present invention is to provide a method for manufacturing a semiconductor device.

〔構成〕〔composition〕

この発明は、半導体ウエーハに多数の半導体素
子を形成する工程と、半導体ウエーハの裏面の各
半導体素子間に対応する位置に絶縁膜を形成する
工程と、半導体ウエーハの裏面全面に軟質金属層
を形成する工程と、半導体ウエーハの裏面に接着
テープを貼り付けたのち剥離することにより、金
属層の半導体材料と絶縁膜への接着力の差を利用
して絶縁膜上の金属層を除去し、絶縁膜形成部分
以外に軟質金属層を形成する工程と、半導体ウエ
ーハを前記絶縁膜に対応する位置からダイシング
する工程とを含むことを特徴とするものである。
This invention includes a process of forming a large number of semiconductor elements on a semiconductor wafer, a process of forming an insulating film at a position corresponding to each semiconductor element on the back surface of the semiconductor wafer, and a process of forming a soft metal layer on the entire back surface of the semiconductor wafer. By applying adhesive tape to the back side of the semiconductor wafer and then peeling it off, the metal layer on the insulating film is removed by utilizing the difference in adhesive strength between the metal layer and the semiconductor material and the insulating film. This method is characterized by including a step of forming a soft metal layer in a region other than the film forming portion, and a step of dicing the semiconductor wafer from a position corresponding to the insulating film.

〔効果〕〔effect〕

この発明は、半導体ウエーハの裏面のダイシン
グ対応位置に硬質の絶縁膜を有するから、半導体
ウエーハをハーフカツトしてブレーキングする場
合に、前記絶縁膜が確実に破断するし、半導体ウ
エーハをダイシング法で完全カツトしても、ダイ
シングブレードの目詰りを生じることなく確実に
ダイシングできる。しかも、絶縁膜を薬品によつ
て溶解除去しないので、その後の洗浄や乾燥を省
略することも可能で製造する容易になるのみなら
ず、資材費や用力費等が節減できて、原価低減が
図れる。さらに、絶縁膜を残存されることによつ
て、この絶縁膜を積極的に利用して、半導体ペレ
ツトとリードフレームやステム等の放熱板との間
に、容易にヒートサイクルに強い最適な半田圧を
確保することができる。発明を実施するための最良の形態 以下に、この発明の実施例を図面を参照して説
明する。
Since this invention has a hard insulating film on the back surface of the semiconductor wafer at a position corresponding to dicing, when the semiconductor wafer is half-cut and braked, the insulating film is reliably broken, and the semiconductor wafer can be completely cut by the dicing method. Even when cutting, dicing can be performed reliably without clogging the dicing blade. Moreover, since the insulating film is not removed by dissolving it with chemicals, subsequent cleaning and drying can be omitted, which not only simplifies manufacturing, but also saves on materials and utility costs, leading to lower costs. . Furthermore, by leaving an insulating film, it is possible to actively utilize this insulating film to create an optimal soldering pressure that is resistant to heat cycles between the semiconductor pellet and a heat sink such as a lead frame or stem. can be ensured. DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

第4図ないし第9図はこの発明による方法の各
段階における半導体ウエーハの断面図を示す。
4 to 9 show cross-sectional views of a semiconductor wafer at various stages of the method according to the invention.

まず、N+N-半導体ウエーハ1を用意し、表裏
両面に酸化膜等の絶縁膜8,9を形成し、表面側
の絶縁膜8のみに窓孔を形成し、N-型領域内に
P型不純物を選択拡散してP型領域を形成するこ
とにより、多数の半導体素子2を形成する(第4
図)。
First, an N + N - semiconductor wafer 1 is prepared, insulating films 8 and 9 such as oxide films are formed on both the front and back surfaces, a window hole is formed only in the insulating film 8 on the front side, and P is formed in the N - type region. A large number of semiconductor elements 2 are formed by selectively diffusing type impurities to form P-type regions (fourth
figure).

次に、周知のフオトエツチング法によつて、表
面側の絶縁膜8にオーミツク接触用の窓孔10を
形成するとともに、裏面の絶縁膜9を前記各半導
体素子2,2間に対応する位置のみに残す(第5
図)。
Next, by a well-known photo-etching method, windows 10 for ohmic contact are formed in the insulating film 8 on the front side, and the insulating film 9 on the back side is formed only at positions corresponding to between the semiconductor elements 2, 2. (5th
figure).

続いて、表面の絶縁膜8上および窓孔10を含
む全面に金を蒸着して金属層3を形成するととも
に、裏面の絶縁膜9上を含む全面に、金を蒸着し
て金層4aを形成し、さらにこの金層4a上に銀
を蒸着して銀層4bを積層することによつて金属
層4を形成する(第6図)。
Subsequently, gold is vapor-deposited on the entire surface including the insulating film 8 on the front surface and the window hole 10 to form the metal layer 3, and gold is vapor-deposited on the entire surface including the insulating film 9 on the back surface to form the gold layer 4a. The metal layer 4 is formed by depositing silver on the gold layer 4a and laminating the silver layer 4b (FIG. 6).

次に半導体ウエーハ1の表裏両面に接着テープ
を貼り付けたのち剥離することにより、金属層3
および金属4aのシリコンと絶縁膜8,9上の接
着力の差を利用して、絶縁膜8,9上の金属層3
および金層4aを剥離除去し、絶縁膜8の窓孔1
0および絶縁膜9,9間部分に、金属層3および
4を形成する(第7図)。
Next, by pasting adhesive tape on both the front and back sides of the semiconductor wafer 1 and peeling it off, the metal layer 3
The metal layer 3 on the insulating films 8 and 9 is then
Then, the gold layer 4a is peeled off and the window hole 1 of the insulating film 8 is removed.
Metal layers 3 and 4 are formed between 0 and insulating films 9, 9 (FIG. 7).

さらに、半導体ウエーハ1の裏面に接着テープ
5を貼り付けて、表面側から各半導体素子2,2
間部分をダイシングして、残り代が60〜80μ程度
のダイシング溝6を形成する(第8図)。
Further, an adhesive tape 5 is pasted on the back side of the semiconductor wafer 1, and each semiconductor element 2, 2 is attached from the front side.
The intermediate portion is diced to form a dicing groove 6 with a remaining margin of approximately 60 to 80 μm (FIG. 8).

この半導体ウエーハ1を下側にしてゴム板等の
上に載せ、接着テープ5の上から鋼製ローラ(図
示せず)を転動させて、半導体ウエーハ1に撓屈
力を作用せしめ、ダイシング溝6の底部から裏面
の絶縁膜9にかけて破断11を生じさせて、各半
導体素子2毎に分離する(第9図)。
This semiconductor wafer 1 is placed face down on a rubber plate, etc., and a steel roller (not shown) is rolled over the adhesive tape 5 to apply a bending force to the semiconductor wafer 1, thereby forming a dicing groove. A break 11 is caused from the bottom of the semiconductor element 6 to the insulating film 9 on the back surface, and each semiconductor element 2 is separated (FIG. 9).

上記の製造方法にしたがえば、ダイシング溝6
に対応する裏面に、硬質の絶縁膜9が形成されて
いるので、ブレーキング時に絶縁膜9が容易かつ
確実に破断し、アベツク不良は発生しない。
According to the above manufacturing method, the dicing groove 6
Since the hard insulating film 9 is formed on the back surface corresponding to the insulating film 9, the insulating film 9 is easily and reliably broken during braking, and no abnormality occurs.

なお、上記実施例は半導体ウエーハ1を所定の
残り代を設けてハーフカツトしたのちブレーキン
グする場合について説明したが、絶縁膜9部分を
含んで完全カツトするようにしてもよい。この場
合、絶縁膜9が硬質なので、ダイシングソウが目
詰りするとなく、容易かつ確実に完全カツトでき
る。
In the above embodiment, the case where the semiconductor wafer 1 is half-cut with a predetermined remaining margin and then braked is performed, but it is also possible to completely cut the semiconductor wafer 1 including the insulating film 9 portion. In this case, since the insulating film 9 is hard, the dicing saw will not become clogged and can be easily and reliably completely cut.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第3図は従来方法について説明す
るための各段階の半導体ウエーハの断面図であ
る。第4図ないし第9図はこの発明による方法に
ついて説明するための各段階の半導体ウエーハの
断面図である。 1……半導体ウエーハ、2……半導体素子、
3,4……金属層、5……接着テープ、6……ダ
イシング溝、8,9……絶縁膜、11……破断
部。
1 to 3 are cross-sectional views of a semiconductor wafer at various stages for explaining the conventional method. 4 to 9 are cross-sectional views of semiconductor wafers at various stages for explaining the method according to the present invention. 1... Semiconductor wafer, 2... Semiconductor element,
3, 4... Metal layer, 5... Adhesive tape, 6... Dicing groove, 8, 9... Insulating film, 11... Broken part.

Claims (1)

【特許請求の範囲】 1 半導体ウエーハに多数の半導体素子を形成す
る工程と、 半導体ウエーハの裏面の各半導体素子間に対応
する位置に絶縁膜を形成する工程と、 半導体ウエーハの裏面全面に軟質金属層を形成
する工程と、 半導体ウエーハの裏面に接着テープを貼り付け
たのち剥離することにより、前記軟質金属層の半
導体材料に対する接着力と前記絶縁膜に対する接
着力との差を利用して、絶縁膜上の軟質金属層を
除去し、絶縁膜形成部分以外に軟質金属層を形成
する工程と、 前記絶縁膜に対応する位置から半導体ウエーハ
をダイシングする工程とを含む半導体装置の製造
方法。
[Claims] 1. A step of forming a large number of semiconductor elements on a semiconductor wafer, a step of forming an insulating film at a position corresponding to each semiconductor element on the back surface of the semiconductor wafer, and a step of forming a soft metal over the entire back surface of the semiconductor wafer. The process involves forming a layer, and by applying an adhesive tape to the back surface of the semiconductor wafer and then peeling it off, the insulation is formed by utilizing the difference between the adhesive strength of the soft metal layer to the semiconductor material and the adhesive strength to the insulating film. A method for manufacturing a semiconductor device, comprising: removing a soft metal layer on a film and forming a soft metal layer in a region other than a portion where an insulating film is to be formed; and dicing a semiconductor wafer from a position corresponding to the insulating film.
JP58175794A 1983-09-22 1983-09-22 Manufacture of semiconductor device Granted JPS6066830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58175794A JPS6066830A (en) 1983-09-22 1983-09-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58175794A JPS6066830A (en) 1983-09-22 1983-09-22 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6066830A JPS6066830A (en) 1985-04-17
JPH0342507B2 true JPH0342507B2 (en) 1991-06-27

Family

ID=16002360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58175794A Granted JPS6066830A (en) 1983-09-22 1983-09-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6066830A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2932278B2 (en) * 1989-02-23 1999-08-09 日本インター株式会社 Method for manufacturing semiconductor device
DE102011112659B4 (en) * 2011-09-06 2022-01-27 Vishay Semiconductor Gmbh Surface mount electronic component

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5158862A (en) * 1974-11-19 1976-05-22 Matsushita Electronics Corp Handotaisoshino bunkatsuho
JPS5386570A (en) * 1977-01-10 1978-07-31 Mitsubishi Electric Corp Production of semiconductor device

Also Published As

Publication number Publication date
JPS6066830A (en) 1985-04-17

Similar Documents

Publication Publication Date Title
JP3455762B2 (en) Semiconductor device and manufacturing method thereof
JP6500481B2 (en) Semiconductor device manufacturing method
JPH10163401A (en) Lead frame, semiconductor package, and method of manufacturing semiconductor package
JPWO1998013862A1 (en) Semiconductor device and manufacturing method thereof
CN104064509A (en) Temporary bonding method and separation method of wafers
JP2011204765A (en) Method for manufacturing semiconductor device, and semiconductor device
JP3957506B2 (en) Substrate surface protection sheet affixing device and affixing method
JP5300470B2 (en) Semiconductor package and method for forming the same
JPH04297056A (en) Manufacture of semiconductor device
JPH0342507B2 (en)
JP2895328B2 (en) Semiconductor device manufacturing method
JP3310576B2 (en) Method for manufacturing semiconductor device
JP3724834B2 (en) Manufacturing method of semiconductor laser device
JPH06112312A (en) Manufacture of semiconductor chip
JP2006041263A (en) Method for manufacturing photoelectric conversion element and photoelectric conversion element
JPH06338563A (en) Semiconductor device and manufacturing method thereof
JPS60176231A (en) Electrode forming process of compound semiconductor element
JPS6020895B2 (en) Manufacturing method of semiconductor device
JPS607139A (en) Bonding method
JPS59103342A (en) Manufacture of semiconductor device
JPS5815242A (en) Manufacture of semiconductor device
JP2823046B2 (en) Semiconductor device and manufacturing method thereof
JPH0864632A (en) Electrode structure of semiconductor device and method of forming the electrode
JPS6016432A (en) semiconductor equipment
JPS6290930A (en) Forming method for electrode of compound semiconductor element