JPH0342533B2 - - Google Patents
Info
- Publication number
- JPH0342533B2 JPH0342533B2 JP57202614A JP20261482A JPH0342533B2 JP H0342533 B2 JPH0342533 B2 JP H0342533B2 JP 57202614 A JP57202614 A JP 57202614A JP 20261482 A JP20261482 A JP 20261482A JP H0342533 B2 JPH0342533 B2 JP H0342533B2
- Authority
- JP
- Japan
- Prior art keywords
- station
- speed
- frame
- control frame
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
Landscapes
- Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Small-Scale Networks (AREA)
Description
【発明の詳細な説明】
本発明は中継回線のデータ伝送速度の速度切替
方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed switching system for data transmission speed of a trunk line.
一般に、多重化分離装置又は多重化集線分離装
置は、端末装置とセンター局に設けられる通信制
御装置との間に中継回線と変復調装置とを介して
対向して設置される。 In general, a multiplexing/demultiplexing device or a multiplexing/concentrating/demultiplexing device is installed opposite to each other via a trunk line and a modulation/demodulation device between a terminal device and a communication control device provided in a center station.
通信制御装置と、端末装置との間のデータ伝送
においては、回線の利用効率を上げる為に中継回
線の通信速度をより高速度とする場合が多い。こ
のとき、通信速度が高速となるほど、信号は回線
の雑音等の影響を受け易すくなり、中継回線のデ
ータ誤り率が増し、その通信速度でのデータ伝送
に支障を生じる。これを回避するために通信速度
を低下させると、中継回線のデータ誤り率が減少
し、データ伝送を継続して行うことができるが、
回線の利用効率が悪くなるので、回線品質が良好
になつたときには、速かに通信速度を復旧させる
必要がある。しかしながら、従来は、一方の局か
ら対向局に電話等の手段を用いてデータ伝送速度
の復旧を連絡し、各々の局で個別に人手を介して
多重化分離装置、あるいは多重化集線装置と変復
調装置との速度変更を行つている。 In data transmission between a communication control device and a terminal device, the communication speed of a relay line is often set to a higher speed in order to increase line utilization efficiency. At this time, as the communication speed increases, the signal becomes more susceptible to line noise, etc., and the data error rate of the relay line increases, causing problems in data transmission at that communication speed. If the communication speed is reduced to avoid this, the data error rate of the relay line will decrease and data transmission can continue, but
Since the line usage efficiency deteriorates, it is necessary to quickly restore the communication speed when the line quality becomes good. However, in the past, one station notified the opposite station of the restoration of the data transmission speed using means such as a telephone, and each station individually manually connected the demultiplexer or multiplex concentrator to the modulation/demodulation. Performing a speed change with the device.
このように従来の方式では、中継回線の品質回
復後の判定、対向局への連絡、多重化分離装置あ
るいは多重化集線分離装置および変復調装置の速
度変更等を行うために人手を介在させる必要があ
り、データ伝送効率の低い状態が持続され、シス
テムのスループツトが低下するうえに、センター
局および対向局の両者に保守要員を配置しなけれ
ばならないという欠点がある。 In this way, conventional systems require human intervention to make decisions after the quality of the trunk line has been restored, to contact the opposing station, and to change the speed of the demultiplexer, demultiplexer, demultiplexer, and modem. However, there are disadvantages in that a state of low data transmission efficiency is maintained, the throughput of the system is reduced, and maintenance personnel must be assigned to both the center station and the opposite station.
本発明の目的は多重化分離装置・多重化集線分
離装置を用いたデータ伝送システムにおいて、中
継回線の障害復旧時に人手の介在なしに障害回復
を判定し、変復調装置・多重化分離装置または多
重化集線分離装置の通信速度の自動的変更と速や
かなデータ通信システムのスループツトの向上お
よび効率低下時間の短縮を達成できる伝送速度切
替方式を提供することにある。 An object of the present invention is to determine failure recovery without human intervention when recovering from a fault in a trunk line in a data transmission system using a demultiplexer/multiplexer/demultiplexer or multiplexer/demultiplexer. An object of the present invention is to provide a transmission speed switching method that can automatically change the communication speed of a concentrator and separate equipment, quickly improve the throughput of a data communication system, and shorten the time for efficiency decline.
本発明の方式は、複数局間の中継回線の伝送品
質の劣化検出時に変更された伝送速度を元の速度
にもどすための伝送速度切替方式において、それ
ぞれの局が、多重化分離手段と、変復調手段と、
伝送品質の回復を検出する監視手段と、該監視手
段による伝送品質の回復の検出に応答して第1の
制御信号の発生と前記監視手段による前記相手局
からの第1の制御信号の受信に応答して第2の制
御信号の発生とを行ない前記監視手段による前記
相手局からの第2の制御信号の受信に応答して第
3の制御信号の発生と前記第3の制御信号の発生
後または前記相手局からの第3の制御信号の受信
後の予め定めた時間に第4の制御信号を発生し前
記監視手段が前記相手局からの第4の制御信号に
誤りを検出しないときには第5の制御信号を発生
する制御信号発生手段と、前記第1〜第5の制御
信号の前記相手局への送出を行なう送出手段と前
記監視手段による相手局からの前記第2または第
3の制御信号の検出または伝送品質の回復の検出
に応答して自局の前記多重化分離手段および変復
調手段のクロツク周波数を変更前の元の周波数に
もどずクロツク制御手段と、を備えている。 The method of the present invention is a transmission speed switching method for returning the changed transmission speed to the original speed when deterioration in the transmission quality of a relay line between multiple stations is detected. means and
monitoring means for detecting recovery of transmission quality; generating a first control signal in response to detection of recovery of transmission quality by the monitoring means; and receiving the first control signal from the partner station by the monitoring means. generating a second control signal in response, generating a third control signal in response to the reception of the second control signal from the partner station by the monitoring means, and after generating the third control signal; Alternatively, a fourth control signal is generated at a predetermined time after receiving the third control signal from the partner station, and when the monitoring means does not detect an error in the fourth control signal from the partner station, a fifth control signal is generated. control signal generating means for generating a control signal; sending means for sending the first to fifth control signals to the partner station; and the second or third control signal from the partner station by the monitoring means. and clock control means for returning the clock frequencies of the multiplexing/demultiplexing means and the modulation/demodulation means of the own station to the original frequencies before the change in response to the detection of the transmission quality or the recovery of transmission quality.
次に本発明について図面を参照して詳細に説明
する。 Next, the present invention will be explained in detail with reference to the drawings.
第1図は本発明の原理を示すシステム構成図で
ある。 FIG. 1 is a system configuration diagram showing the principle of the present invention.
センター側に設けられた通信制御装置1からの
低速回線2−1〜2−nは多重化分離装置または
多重化集線分離装置3と接続される。この分離装
置3と端末側に設けられた多重化分離装置または
多重化集線分離装置10とは、高速変復調装置
4,5,6および7ならびに中継回線(高速回
線)8および9を介して相互に接続される。端末
装置12−1〜12−nは低速回線11−1〜1
1−nを介して多重化分離装置または多重化集線
分離装置10と接続される。 Low-speed lines 2-1 to 2-n from the communication control device 1 provided on the center side are connected to a multiplexing/demultiplexing device or a multiplexing/concentrating/separating device 3. This demultiplexing device 3 and the multiplexing demultiplexing device or multiplexing concentrator demultiplexing device 10 provided on the terminal side are mutually connected via high speed modem devices 4, 5, 6 and 7 and trunk lines (high speed lines) 8 and 9. Connected. Terminal devices 12-1 to 12-n are connected to low-speed lines 11-1 to 11-1.
1-n to a demultiplexer or demultiplexer 10.
第2図は第1図に使用する多重化分離装置また
は多重化集線分離装置3および10を示すブロツ
ク図である。図において、分離装置は、低速回線
対応に設けたレベル変換回路13,14,15お
よび16と、送受信回路17,18,19および
20と、多重化分離回路21と、高速回線対応に
設けた送受信回路22および23と、レベル変換
回路24および25とを備えた従来の分離装置
に、フレーム監視回路26と、制御フレーム発生
回路27と、速度制御回路28と、レベル変換回
路29および30とが付加されている。低速回線
に入力された低速データはレベル変換回路13,
14,15および16によりレベル変換されたあ
と、送受信回路17,18,19および20等で直
並列変換され、多重化分離回路21に送られる。
多重化分離回路21では、低速回線からの並列デ
ータが時分割多重化されて、高速回線用の送受信
回路22および23を介してレベル変換回路2
4,25に送られレベル変換されて高速回線用変
復調装置に送出される。一方、中継回線8および
9を介して対向局から送られてきた多重化データ
は、レベル変換回路24および25を介して送受
信回路22および23で直並列変換され、多重化
分離回路21で各低速回線対応に分離されて、各
低速回線の送受信回路17,18,19および2
0に送られ、ここで並直列変換されたあとレベル
変換回路13,14,15および16を介して低
速回線に送出される。 FIG. 2 is a block diagram showing the demultiplexing device or demultiplexing device 3 and 10 used in FIG. In the figure, the demultiplexing device includes level conversion circuits 13, 14, 15, and 16 provided for low-speed lines, transmitting/receiving circuits 17, 18, 19, and 20, a multiplexing/demultiplexing circuit 21, and a transmitting/receiving circuit provided for high-speed lines. A frame monitoring circuit 26, a control frame generation circuit 27, a speed control circuit 28, and a level conversion circuit 29 and 30 are added to the conventional separation device including circuits 22 and 23 and level conversion circuits 24 and 25. has been done. The low-speed data input to the low-speed line is sent to the level conversion circuit 13,
After level conversion by 14, 15 and 16, serial-to-parallel conversion is performed by transmitting/receiving circuits 17, 18, 19 and 20, etc., and sent to a multiplexing/demultiplexing circuit 21.
In the multiplexing/demultiplexing circuit 21, parallel data from the low-speed line is time-division multiplexed and sent to the level conversion circuit 2 via the high-speed line transmitting/receiving circuits 22 and 23.
4 and 25, level-converted and sent to a high-speed line modem. On the other hand, the multiplexed data sent from the opposing station via the relay lines 8 and 9 is serial-parallel converted by the transmitting/receiving circuits 22 and 23 via the level converting circuits 24 and 25, and is converted into serial/parallel data by the transmitting/receiving circuits 22 and 23, and then sent to the multiplexing/demultiplexing circuit 21 for each low-speed Transmission/reception circuits 17, 18, 19 and 2 for each low-speed line are separated according to the line.
0, where it is parallel-to-serial converted and then sent to a low-speed line via level conversion circuits 13, 14, 15 and 16.
次に伝送速度切替動作について説明する。 Next, the transmission speed switching operation will be explained.
通常、中継回線8または9を介して行なわれる
多重化分離装置3および10間のデータ伝送にお
いては、第3図に示されるようなフレーム構成を
有する信号が使用される。これは、フレーム同期
用のフラグキヤラクタ31と、アドレスキヤラク
タ32と、データを示す制御キヤラクタ33と、
多重化データ用の情報フイールド34と、フレー
ムチエツクキヤラクタ35とから構成される。 Normally, in data transmission between the multiplexing and demultiplexing devices 3 and 10 via the trunk line 8 or 9, a signal having a frame structure as shown in FIG. 3 is used. This includes a flag character 31 for frame synchronization, an address character 32, a control character 33 indicating data,
It consists of an information field 34 for multiplexed data and a frame check character 35.
中継回線8を介して対向局から受信されたデー
タフレームは送受信回路22の受信部に入力され
たあと、フラグキヤラクタ31が検出され、これ
に続くデータ列が直並列変換されて多重化分離回
路21およびフレーム監視回路26に加えられ
る。フレーム監視回路26では受信したデータの
巡回符号検査を行ない、受信フレーム中のフレー
ムチエツクキヤラクタ35との照合を行ないフレ
ーム誤りを検出する。このとき、通常のデータ伝
送速度から低下させた速度において、一定期間フ
レーム誤りが検出されなくなると、フレーム監視
回路26から制御フレーム発生回路27および速
度制御回路28に対して該中継回線の回復を示す
回復信号が第5図のの如く出力される。ここ
で、第5図は、本実施例の動作を示しており、S1
は、多重化分離装置3のレベル変換回路24の送
信部R1は同受信部、S2は多重化分離装置10の
レベル変換回路24′の送信部、R2は同受信部の
動作を示している。 After the data frame received from the opposite station via the relay line 8 is input to the receiving section of the transmitting/receiving circuit 22, the flag character 31 is detected, and the following data string is serial-parallel converted and sent to the multiplexing/demultiplexing circuit 21 and Added to frame monitoring circuit 26. The frame monitoring circuit 26 performs a cyclic code check on the received data, and compares it with the frame check character 35 in the received frame to detect frame errors. At this time, when no frame errors are detected for a certain period of time at a speed lowered from the normal data transmission speed, the frame monitoring circuit 26 indicates to the control frame generation circuit 27 and the speed control circuit 28 that the trunk line has recovered. A recovery signal is output as shown in FIG. Here, FIG. 5 shows the operation of this embodiment, and S 1
shows the operation of the transmitting section R1 of the level conversion circuit 24 of the multiplexing and demultiplexing device 3, S2 is the transmitting section of the level conversion circuit 24' of the multiplexing and demultiplexing device 10, and R2 is the operation of the receiving section. ing.
制御フレーム発生回路27は上記回復信号を受
信すると、多重化分離装置の送受信回路22に対
して通信速度変更用の制御フレームA(第4図a
参照)を送出する。送受信回路22はこの制御フ
レームAを受け取ると、多重化分離回路21から
の多重化データの替りに、第5図のS1の C1 の
如く、この制御フレームAを送信する。対向局の
多重化分離装置10のフレーム監視回路26は、
中継回線8を介してこの制御フレームAを受信す
ると、制御フレーム発生回路27に対し、制御フ
レーム応答信号を送出する。制御フレーム発生回
路27は制御フレームB(第4図b参照)を送受
信回路22に送出し対向局に中継回線8を介して
第5図のS2の C2 の如く、送信する。対向局の
多重化分離装置3のフレーム監視回路26では、
この制御フレームBを受信すると、第5図のの
如く、制御フレーム応答信号を制御フレーム発生
回路27に対し送出する。制御フレーム発生回路
27ではこの応答信号により制御フレームBを送
受信回路22に送出し、さらに、第5図のS1の
C2 の如く中継回線8に制御フレームBを送信す
る。その後速度復旧信号が速度制御回路28より
送受信回路22及び多重化分離回路21とレベル
変換回路29に送出され、該多重化分離装置3と
変復調装置4の通信速度を元の通信速度に復旧さ
せる。 When the control frame generation circuit 27 receives the recovery signal, it sends a control frame A for changing the communication speed to the transmission/reception circuit 22 of the demultiplexing device (Fig. 4a).
(see). When the transmitting/receiving circuit 22 receives this control frame A, it transmits this control frame A instead of the multiplexed data from the multiplexing/demultiplexing circuit 21, as shown in C1 of S1 in FIG. The frame monitoring circuit 26 of the multiplexing and demultiplexing device 10 of the opposite station is
When this control frame A is received via the relay line 8, a control frame response signal is sent to the control frame generation circuit 27. The control frame generation circuit 27 sends the control frame B (see FIG. 4b) to the transmitting/receiving circuit 22, and transmits it to the opposite station via the relay line 8 as shown in C2 of S2 in FIG. In the frame monitoring circuit 26 of the multiplexing and demultiplexing device 3 of the opposite station,
When this control frame B is received, a control frame response signal is sent to the control frame generation circuit 27 as shown in FIG. The control frame generating circuit 27 sends the control frame B to the transmitting/receiving circuit 22 according to this response signal, and further, the control frame B is sent to the transmitting/receiving circuit 22 in accordance with the response signal, and further, the control frame B is sent to the transmitting/receiving circuit 22 in response to the response signal.
Control frame B is transmitted to trunk line 8 as shown in C2. Thereafter, a speed restoration signal is sent from the speed control circuit 28 to the transmitting/receiving circuit 22, the multiplexing/demultiplexing circuit 21, and the level converting circuit 29, thereby restoring the communication speed of the multiplexing/demultiplexing device 3 and the modulation/demodulation device 4 to the original communication speed.
多重化分離装置10のフレーム監視回路26
は、第5図のR2の C2 の如く、制御フレームB
を受信すると速度制御回路28に対して受信信号
を送出する。これにより速度制御回路28は速度
復旧信号を送受信回路22、多重化分離回路21
およびレベル変換回路29に送出し、該多重化分
離装置10と、変復調装置6との伝送速度を元の
状態に復旧させる。多重化分離装置3側では速度
復旧信号により元の伝送速度に変更されるととも
に制御フレーム発生回路27から制御フレームC
が送受信回路22に送出され、さらに、レベル変
換回路24、変復調装置4および中継回線8を介
して第5図のS1の C3 の如く対向する多重化分
離装置10に送信される。一方、多重化分離装置
10でも時間的遅れはあるが伝送速度が元に戻さ
れるので多重化分離装置3からの制御フレームC
が正しく受信される。多重化分離装置10のフレ
ーム監視回路26でこの制御フレームCが認識さ
れ且つ誤りが一定期間検出されないと、制御フレ
ーム認識信号が第5図のの如く、フレーム監視
回路26から制御フレーム発生回路27に送出さ
れる。これを受けて制御フレーム発生回路27で
は、応答の制御フレームBが発生され、対向局
へ、第5図のS2の如く、送信される。これより以
前に多重化分離装置10では、伝送速度切替後
に、制御フレームCが制御フレーム発生回路27
で発生され、対向局へ送出されている。多重化分
離装置3では制御フレームCを第5図のR1の如
く受信すると、制御フレーム監視回路26で一定
期間誤りの有無を検出し、誤りが無ければ制御フ
レーム認識信号を制御フレーム発生回路27に送
出し制御フレームCの替りに制御フレームBを送
受信回路22に送出する。 Frame monitoring circuit 26 of demultiplexing device 10
is the control frame B, such as C2 of R 2 in Figure 5.
When received, a reception signal is sent to the speed control circuit 28. As a result, the speed control circuit 28 sends a speed recovery signal to the transmitting/receiving circuit 22 and the multiplexing/demultiplexing circuit 21.
and is sent to the level conversion circuit 29 to restore the transmission speed between the multiplexer/demultiplexer 10 and the modulator/demodulator 6 to the original state. On the multiplexing/demultiplexing device 3 side, the transmission speed is changed to the original transmission speed by the speed restoration signal, and the control frame C is sent from the control frame generation circuit 27.
is sent to the transmitting/receiving circuit 22, and further transmitted to the opposing multiplexing/demultiplexing device 10 as indicated by C3 of S1 in FIG. 5 via the level conversion circuit 24, modem device 4, and relay line 8. On the other hand, although there is a time delay in the multiplexing and demultiplexing device 10, the transmission speed is restored to the original value, so the control frame C from the multiplexing and demultiplexing device 3 is
is received correctly. When this control frame C is recognized by the frame monitoring circuit 26 of the multiplexing/demultiplexing device 10 and no error is detected for a certain period of time, a control frame recognition signal is sent from the frame monitoring circuit 26 to the control frame generation circuit 27 as shown in FIG. Sent out. In response to this, the control frame generation circuit 27 generates a response control frame B, and transmits it to the opposite station as shown in S2 in FIG. Prior to this, in the demultiplexer 10, after switching the transmission rate, the control frame C was sent to the control frame generation circuit 27.
is generated and sent to the opposite station. When the multiplexing and demultiplexing device 3 receives the control frame C as shown in R1 in FIG. 5, the control frame monitoring circuit 26 detects the presence or absence of an error for a certain period of time, and if there is no error, the control frame recognition signal is transmitted to the control frame generation circuit 27. Control frame B is sent to the transmitting/receiving circuit 22 instead of sending control frame C.
以上のように多重化分離装置3および10はそ
れぞれ自局が送出した制御フレームCに対する応
答制御フレームBを受信することになり、伝送速
度を元に戻したあとの通信路が正常であることを
確認でき、従つて、各局の装置の多重化分離回路
21からの多重化データが制御フレームの替りに
送受信回路22に取り込まれ、レベル変換回路2
4を介して中継回線8に送出される。 As described above, each of the multiplexing and demultiplexing devices 3 and 10 receives the response control frame B to the control frame C sent by its own station, and confirms that the communication path is normal after the transmission speed is restored. Therefore, the multiplexed data from the multiplexing/demultiplexing circuit 21 of each station's equipment is taken into the transmitting/receiving circuit 22 instead of the control frame, and the level converting circuit 2
4 to the trunk line 8.
第6図は本発明の一実施例を示すブロツク図で
ある。 FIG. 6 is a block diagram showing one embodiment of the present invention.
まず、多重化処理について説明する。各低速回
線CH1〜CH4からの各低速信号は、各インター
フエース回路101〜104に与えられレベル変
換等の処理を受けたあと送受信回路105および
106に送出される。送受信回路としては、1981
年発行のインテルコンポーネント・データ・カタ
ログの第8−163頁記載のHDLC/SDLCプロト
コルコントローラ8273等を使用できる。この送受
信回路105および106において、前記低速信
号は直列信号から並列信号に変換される。CPU
(central processig unit)118の制御により各チ
ヤネルの並列信号は順にデータバス107に送出
され、RAM(random access memory)119
の各アドレスに各チヤネルの並列信号が格納され
る。次に、このRAM119内容を適当な順番に
並列信号として読み出すことにより多重化処理が
行なわれ、この多重化並列信号を送受信回路11
5に与える。送受信回路115は、与えられた多
重化並列信号を多重化直列信号に変換して高速回
線に送出する。分離処理は、これと全く逆の処理
を行なえばよいので説明は省略する。 First, multiplexing processing will be explained. Each low-speed signal from each of the low-speed lines CH1 to CH4 is applied to each interface circuit 101 to 104, subjected to processing such as level conversion, and then sent to transmitting/receiving circuits 105 and 106. As a transmitter/receiver circuit, 1981
You can use the HDLC/SDLC protocol controller 8273 described on page 8-163 of the Intel Component Data Catalog published in 2016. In the transmitting/receiving circuits 105 and 106, the low-speed signal is converted from a serial signal to a parallel signal. CPU
Under the control of a (central processing unit) 118, the parallel signals of each channel are sequentially sent to a data bus 107, and a RAM (random access memory) 119
Parallel signals of each channel are stored at each address. Next, multiplexing processing is performed by reading out the contents of this RAM 119 in an appropriate order as parallel signals, and this multiplexed parallel signal is sent to the transmitter/receiver circuit 11.
Give to 5. The transmitter/receiver circuit 115 converts the applied multiplexed parallel signal into a multiplexed serial signal and sends it to the high-speed line. Since the separation process can be performed in the completely opposite manner, a description thereof will be omitted.
次に、速度切替動作について説明する。高速回
線からの高速信号のフレームは送受信回路115
内のフレーム監視回路によつて監視されている。
今、伝送品質の劣化が回復すなわちフレーム監視
回路でフレーム誤りが一定時間以上検出されなか
つたとすると、フレーム監視回路から118に割
込み信号が送出され、多重化分離処理は中断され
るとともにROM(read only memory)内の割込
み処理プログラムに基づいて、各種制御信号が
RAM119内に構成され、高速回線に送出され
る。さらに、システムタイミングコントローラ1
20を制御して伝送速度を変更する。さらに、速
度変更後に送られてくる制御信号により伝送品質
を確認したあと、中断していた多重化分離処理を
続行する。 Next, the speed switching operation will be explained. The frame of the high-speed signal from the high-speed line is sent to the transmitter/receiver circuit 115.
is monitored by a frame monitoring circuit within the frame.
Now, if the deterioration in transmission quality is recovered, that is, the frame monitoring circuit does not detect a frame error for a certain period of time, the frame monitoring circuit sends an interrupt signal to 118, interrupts the demultiplexing process, and ROM (read only Various control signals are processed based on the interrupt processing program in
It is configured in RAM 119 and sent out to a high-speed line. Furthermore, the system timing controller 1
20 to change the transmission speed. Furthermore, after checking the transmission quality using the control signal sent after the speed change, the suspended multiplexing/demultiplexing process is continued.
以上述べたように、本発明による通信速度切替
方式によれば、多重化分離装置間の中継回線の誤
り率増大時、受信側で回線の障害を自動的に判定
し、それにより先ず誤り受信側の通信速度を自動
的に低下せしめたあと、対向局側の通信速度を自
動的に低下させることが出来、対向局への連絡お
よび多重化分離装置および変復調装置の速度変更
およびデータ伝送の復旧に人手を介在させる必要
が無くなり、障害発生から障害復旧迄の時間を短
縮し、且つ、対向する両局に保守要員を配置する
必要がなくなるという効果がある。 As described above, according to the communication speed switching method according to the present invention, when the error rate of the relay line between multiplexing and demultiplexing devices increases, the receiving side automatically determines a failure in the line, thereby first After automatically lowering the communication speed of the opposite station, it is possible to automatically lower the communication speed of the opposite station, which is useful for contacting the opposite station, changing the speed of the demultiplexer and modem, and restoring data transmission. This eliminates the need for human intervention, shortens the time from failure occurrence to failure recovery, and eliminates the need to station maintenance personnel at both opposing stations.
第1図は本発明の原理を説明するためのシステ
ム構成図、第2図は第1図の多重化分離装置また
は多重化集線分離装置)のブロツク図、第3図は
第1図のシステム構成における中継回線上に用い
られるフレーム構成図、第4図aおよびbはフオ
ールバツク方式の制御フレームの構成図、第5図
は第1図のシステム構成における多重化分離装置
のフオールバツク動作を示したタイムチヤートお
よび第6図は本発明の一実施例を示すブロツク図
である
図において、1……通信制御装置、2−1〜2
−n,11−1〜11−n低速回線、3,10…
…多重化分離装置(又は多重化集線分離装置)、
4〜7……高速変復調装置、8,9……中継回
線、12−1〜12−n……端末装置、24,2
5,29,30……レベル変換回路、13〜16
……レベル変換回路、26……フレーム監視回
路、17〜20……送受信回路、27……制御フ
レーム発生回路、21……多重化分離回路、28
……速度制御回路、22,23,105,10
6,115,116……送受信回路、104〜1
04……インタフエース回路、117……読出し
専用メモリ、118……中央処理装置、119…
…ランダム・アクセス・メモリ、120……シス
テムタイミングコントローラ。
Fig. 1 is a system configuration diagram for explaining the principle of the present invention, Fig. 2 is a block diagram of the multiplexing/demultiplexing device or multiplexing/concentrating/demultiplexing device shown in Fig. 1, and Fig. 3 is the system configuration of Fig. 1. Figures 4a and 4b are block diagrams of control frames for the fallback system, and Figure 5 is a time chart showing the fallback operation of the multiplexing/demultiplexing device in the system configuration of Figure 1. and FIG. 6 is a block diagram showing one embodiment of the present invention. In the figure, 1... communication control device, 2-1 to 2
-n, 11-1 to 11-n low speed line, 3, 10...
...multiplexing/separating device (or multiplexing/concentrating/separating device),
4 to 7...High speed modulation/demodulation device, 8, 9...Relay line, 12-1 to 12-n...Terminal device, 24, 2
5, 29, 30...Level conversion circuit, 13-16
... Level conversion circuit, 26 ... Frame monitoring circuit, 17-20 ... Transmission and reception circuit, 27 ... Control frame generation circuit, 21 ... Multiplexing and demultiplexing circuit, 28
...Speed control circuit, 22, 23, 105, 10
6,115,116...transmission/reception circuit, 104-1
04...Interface circuit, 117...Read-only memory, 118...Central processing unit, 119...
... Random access memory, 120 ... System timing controller.
Claims (1)
の伝送品質の劣化検出時に変更された伝送速度を
元の速度にもどすための伝送速度切替方式におい
て、 前記A局において、一定期間データフレームの
誤りが検出されなくなると低下速度での回線品質
が回復したと判断し前記多重化データの替りに第
1の制御フレームAを前記B局に送出し、 前記B局ではデータフレームを常時モニタし前
記A局からの前記第1の制御フレームAを検出す
ると応答フレームBを前記A局に返送し、 前記A局では前記B局からの前記応答フレーム
Bを受信すると前記B局へ前記応答フレームBを
送信すると共に前記A局の速度を元の速度に戻
し、元の速度で第2の制御フレームCを前記B局
に送出し、 前記B局では前記A局からの前記応答フレーム
Bを受信すると前記B局の速度を元の速度に戻
し、元の速度で前記第2の制御フレームCをA局
に送出し、 前記B局では前記A局からの前記第2の制御フ
レームCを監視し、前記第2の制御フレームが一
定期間正常に受信されたとき前記応答フレームB
を前記A局に返送し、 前記A局では前記B局からの前記第2の制御フ
レームCが一定期間正しく受信されると前記応答
フレームBを前記B局に返送し、前記A局および
B局共前記元の速度で送られてきた第2の制御フ
レームCの検出に対応して送られてきた相手局か
らの前記応答フレームBを受信すると前記制御フ
レームの替りに前記多重化データを切替えて伝送
することを特徴とする伝送速度切替方式。[Scope of Claims] 1. In a transmission rate switching method for restoring a transmission rate changed upon detection of deterioration in transmission quality of multiplexed data on a relay line between stations A and B to the original rate, in the station A: When no data frame errors are detected for a certain period of time, it is determined that the line quality at the reduced speed has been restored, and the first control frame A is sent to the B station instead of the multiplexed data, and the B station transmits the data. The frames are constantly monitored, and when the first control frame A from the A station is detected, a response frame B is sent back to the A station, and when the A station receives the response frame B from the B station, the B station transmits the response frame B to the station A, returns the speed of the A station to the original speed, and sends a second control frame C to the B station at the original speed, and the B station receives the response from the A station. Upon receiving frame B, the speed of the B station is returned to the original speed, and the second control frame C is sent to the A station at the original speed, and the B station receives the second control frame from the A station. C, and when the second control frame is normally received for a certain period of time, the response frame B is
When the second control frame C from the B station is correctly received for a certain period of time, the A station returns the response frame B to the B station, and the A station and the B station Upon receiving the response frame B sent from the partner station in response to the detection of the second control frame C sent at the original speed, the multiplexed data is switched in place of the control frame. A transmission speed switching method characterized by transmission.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57202614A JPS5991752A (en) | 1982-11-18 | 1982-11-18 | Switching system of transmission speed |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57202614A JPS5991752A (en) | 1982-11-18 | 1982-11-18 | Switching system of transmission speed |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5991752A JPS5991752A (en) | 1984-05-26 |
| JPH0342533B2 true JPH0342533B2 (en) | 1991-06-27 |
Family
ID=16460309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57202614A Granted JPS5991752A (en) | 1982-11-18 | 1982-11-18 | Switching system of transmission speed |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5991752A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5351134A (en) * | 1988-04-07 | 1994-09-27 | Canon Kabushiki Kaisha | Image communication system, and image communication apparatus and modem used in the system |
| KR100677147B1 (en) * | 2004-11-02 | 2007-02-02 | 삼성전자주식회사 | Facsimile transmission speed setting method and device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5527777A (en) * | 1978-08-19 | 1980-02-28 | Fujitsu Ltd | Control system for picture signal transmission |
| IL62566A0 (en) * | 1980-04-18 | 1981-06-29 | Kearney & Trecker Corp | Digital data transmission system |
| JPS57155856A (en) * | 1981-03-20 | 1982-09-27 | Fujitsu Ltd | Adaptive modulation system |
-
1982
- 1982-11-18 JP JP57202614A patent/JPS5991752A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5991752A (en) | 1984-05-26 |
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