JPH0342613B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse counting device that counts pulse signals generated in relation to changes in a measured quantity, such as the running speed or engine speed of an automobile or motorcycle.

In general, when displaying a measured quantity using pulses proportional to the measured quantity, pulses proportional to the measured quantity are counted at a gate time set by a reference clock signal, and this counted value is latched and displayed as it is updated sequentially. Devices that do this are known. The updateable time for this device is determined by setting the gate time using the reference clock signal, and measurement accuracy depends on the density of the number of pulses input within this gate time. Providing a high density of proportional pulses not only makes the pulse generator quite expensive, but even if it were available at low cost, the number of pulses generated within a clock period at high speeds would be extremely large. The disadvantage is that the capacity of the counter must be increased, resulting in an extremely large and expensive device overall. Furthermore, a method of increasing the gate time and relatively increasing the number of pulses input within this gate time can be easily achieved, but this method has the disadvantage that it is not possible to follow sudden changes in the measured quantity. Therefore, as shown in Fig. 1, when a pulse proportional to a change in the measured quantity is input to input terminal 1, it is counted by counter 2 connected to input terminal 1 and has a counting period. 2
When counting is completed, the counted value of the counter 2 is written in a plurality of registers, for example, four registers 3a, 3b, 3c, and 3d, respectively, and these registers 3a to 3d are
The count values written in are added by an adder 4, and a value corresponding to this added value P is displayed.

To explain the operation of the circuit shown in Fig. 1 with reference to Fig. 2, when a pulse A proportional to a change in a measured quantity, for example, the running speed, is input, when the counter 2 finishes counting,
At t ₁ , t ₂ , t ₃ , and t ₄ , the pulse numbers P ₁ , P ₂ , P ₃ , and P ₄ counted during each display switching time, for example, 1 second, are stored in registers 3d, 3c, 3b, and 3a. ,
The stored pulse numbers P ₁ , P ₂ , P ₃ , and P ₄ are added by the adder 4, and the display 5 shows (P ₁ +P ₂ +P ₃ +P ₄ ).
The traveling speed corresponding to the value of is displayed.

Here, if the traveling speed suddenly decreases and reaches 0 km/h at _t4 , at the end of counting by the counter 2 at _t5 , the number of pulses counted during the new display switching time _t4 to _{t5 P5} = 0 newly enters the register 3a, and the pulse numbers P ₄ , P ₃ , P ₂ previously stored in the registers 3a, 3b, 3c are sequentially shifted to the registers 3b, 3c, 3d, and the oldest display switching is performed. The number of pulses P ₁ counted from time t ₀ to t ₁ is shifted out of the register, and the running speed corresponding to the value (P ₂ +P ₃ +P ₄ +0) added by the adder 4 is displayed on the display. 5, and the display will show a certain speed value even though the traveling speed has reached 0 km/h.

Furthermore, at the end of the next counting, _t6 , the number of pulses P6 = 0 counted during the new display switching time _t5 to _t6 is newly entered into the register 3a, and until then the number of pulses _P6 = 0 is entered into the register 3a.
Number of pulses P ₅ , P ₄ , P ₃ stored in b and 3c
are sequentially shifted to registers 3b, 3c, and 3d, and the number of pulses _P2 counted during the oldest display switching time _t1 to _t2 is shifted out of the register.
The display 5 shows the traveling speed according to the value of (P ₃ +P ₄ +0+0) added by the adder 4, and the display continues to show a certain speed value even though the traveling speed is 0 km/h. .

Thereafter, at the end of counting _t7 , the pulse numbers _P3 to P6 stored in the registers 3a to 3d are shifted in the same manner as described above, and the pulse numbers counted at the oldest display switching time _t2 to _{t3 are} shifted. Instead of P ₃ being shifted out of the register, the number of pulses P ₇ =0 counted during the new display switching time t ₆ to t ₇ enters the register 3a, and is added directly to (P ₄ +0+0+0) added by the adder 4. The display 5 shows the traveling speed according to the speed, and the displayed value never reaches 0 km/h.

Then, at the end of counting _t8 , the number of pulses _P4 to _P7 stored in the registers 3a to 3d is shifted, and the number of pulses _P4 counted at the oldest display switching time _t3 to _t4 is stored in the register. The number of pulses counted in the new display switching time t ₇ to t ₈ instead of being shifted out
When P ₈ =0 enters register 3a, register 3a
The sum of ~3d is (0+0+0+0), and the traveling speed displayed on the display 5 for the first time is 0km/
h.

In this way, with a travel speedometer that uses a conventional pulse counting device, the display does not change to 0 after the car actually stops.
It took 4 seconds to display Km/h, and there was a drawback that the response was slow and there was a difference between the actual perceived speed value and the displayed value.

In order to eliminate the drawbacks of the conventional device, the present invention divides the gate time into multiple parts, counts the pulses generated according to the measured amount, detects the change in the number of pulses within the gate time, and uses this change to determine the gate time. The present invention is characterized by correcting the number of pulses counted within a period of time and displaying a numerical value according to the corrected result, and its purpose is to provide a pulse counting device that has quick response to sudden changes in the number of pulses.

To achieve the above object, the present invention divides a gate time for counting pulses generated in response to changes in a measured quantity into multiple parts, and calculates the number of pulses counted each time the divided gate time passes. A new number of pulses counted each time is stored in the first register among the registers, and a new number of pulses counted each time thereafter is stored in the first register, and the number of pulses stored in each register up to that point is sequentially stored in the subsequent register. Shift and erase the number of pulses stored in the last register, correct the number of pulses in each register according to the latest number of pulses stored in the first register, and use the corrected values stored in all registers. In the pulse counting device configured to display a corresponding value, a first register determines whether the latest pulse number is continuous including the first register and calculates the first consecutive number.
a second determining means for determining whether the latest pulse number is continuous in registers other than the consecutive registers including the first register, and calculating a second consecutive number; Comparison means for determining the difference between the first and second consecutive numbers, and means for correcting the values of registers other than the first register based on the comparison result, and correction according to the number of consecutive pulses of the latest pulse number. It is configured to perform the following.

An embodiment of the present invention will be described in detail below based on the accompanying drawings.

FIG. 3 is a block diagram of a pulse counting device according to an embodiment of the present invention. In the same figure, 6 is an input terminal for inputting pulses generated in accordance with the measured amount of a speed detecting section (not shown), and 7 is an input terminal. This is a timer that sets the counting time of the pulses inputted at the terminal 6. The counting time is a value obtained by dividing the gate time by an arbitrary integer, and in this embodiment, it is set to 1/N of the gate time. 8 is a counter that counts the pulses inputted at the input terminal 6 during a set counting time; 9 is a storage section consisting of a plurality of registers that stores the number of pulses counted by the counter 8;
The number of registers in the storage section 9 is the value of the quotient when the gate time is divided by the counting time, and in this embodiment, N registers are used, and the number of pulses counted by the counter 8 is stored every time the counting time elapses. _The pulse numbers previously stored in _the registers _{9 1 , 9 2 .
N} , and the number of pulses stored in the register 9 _N is erased from the storage section 9. The values of each register are all input to an arithmetic circuit 10, which will be described later, every time the number of pulses is input. Arithmetic circuit 10
compares the latest pulse number within the gate time input to register ₉₁ with the previous pulse numbers stored in other registers ₉₂ to _9N , and detects a sudden change in the number of pulses, that is, an increase or decrease state. A comparison is made and a command is issued to correct the contents of the number of pulses stored in the registers 9 ₂ to 9 _N based on the result of the comparison. Based on this correction command, the distributor 11 rewrites the number of pulses in each register 9 ₂ to 9 _N and stores it in each register 9 ₂ to 9 _N , and then adds the number of pulses stored in registers 9 ₁ to 9 _N. Vessel 1
2, the latch circuit 13 performs the necessary driving for display, and the display section 14 displays a numerical value corresponding to the value of the adder 12.

Next, the configuration of the arithmetic circuit 10 will be explained in more detail based on FIG. 4.

The number of pulses stored in each register ₉₁ to _9N is determined by the comparison and judgment circuit 15 as the number of pulses in register ₉₁ .
P ₁ and the number of pulses P _i of registers 9 ₂ to 9 _N (i=2 to N)
are compared, and if it is determined that |(P ₁ −P _i )|≧X (X is a certain set value), the positive/negative determination circuit 1
6, the positive or negative of (P ₁ −P _i ) is determined, and based on the result, the first or second correction command circuit 17,
At step 18, a command is issued to rewrite and correct the number of pulses in the registers 9 ₂ to 9 _N with a certain predetermined value. The rewriting correction command for the registers 9 ₂ - 9 _N is transferred to the distributor 11, and the distributor 11 rewrites the values of the registers 9 ₂ - 9 _N based on the correction command. on the other hand,
When the comparison _/ determination circuit 15 determines that |( _{P 1} −P _i )| _< It is determined whether or not there are two or more consecutive times including the register ₉₁ within, and the number of consecutive times _K1 is counted.
The second consecutive number determining circuit 20 determines whether or not there is a consecutive value other than the pulse number P ₁ among the pulse numbers in the registers 9 ₂ to 9 _N.

Based on the results of the first and second consecutive number determination circuits 19 and 20, the third correction command circuit 21 converts at least one of the pulse numbers in the registers 92 _{to 9N} to the pulse number P in the register _91. The fourth correction command circuit 22 issues a command to rewrite to ₁ and correct it, and the fourth correction command circuit ₂₂
A command is issued to rewrite and correct a predetermined number of pulses out of ~ _9N to a value other than the number of consecutive pulses _P1 , and the result is transferred to the distributor 11.

The third consecutive number determining circuit 23, which is the second determining means, determines whether the pulse number P ₁ is in any register other than the consecutive registers including the register P ₁ and the consecutive registers including the last stage register P _N. It is determined whether or not the sequence continues one or more times, and the number of consecutive times K ₂ is counted. The consecutive number comparing circuit 24, which is the comparing means _, calculates _{(K 1 −}
K ₂ )≧2. (K ₁ −K ₂ )≧
2, the fifth correction command circuit 25 issues a command to rewrite and correct the predetermined number of pulses in the registers 9 ₂ to 9 _N to the value of the number of pulses P ₁ , and the sixth correction command circuit 26 issues A command is issued to rewrite and correct a predetermined number of pulses in the registers 9 ₂ to 9 _N to a value other than the number of pulses P ₁ , and the result is transferred to the distributor 11 . The means for correcting the values of registers other than the first register are the fifth and sixth correction command circuits 25 and 26.
Composed by.

The operation of the present invention constructed as described above will be explained in detail with reference to the flowchart of the arithmetic circuit shown in FIG.

First, pulses input from the input terminal 6 are counted by the counter 8 and input to the register ₉₁ every time 1/N of the gate time elapses. This register 9 ₁
The number of pulses input to is sequentially shifted from register 9 ₂ to register 9 _N every 1/N time. The number of pulses in these registers 9 ₁ to 9 _N is determined by the arithmetic circuit 10
The data is transferred to the comparison/judgment circuit 15 that constitutes the. The comparison/judgment circuit 15 compares the number of pulses P ₁ in the register 9 ₁ and the number of pulses P _i (i=2 to N) in the other registers 9 ₂ to 9 _N , respectively, and calculates the difference between P ₁ and P _i as the set value X. In other words, it is determined whether |(P ₁ −P _i )|≧X (STEP 1). In this embodiment, the set value X is assumed to be "2" for explanation purposes. If |(P ₁ −P _i )|≧2 in at least one register 9 ₂ to 9 _N , the positive/negative determination circuit 16 determines whether (P ₁ −P _i ) is positive or negative (STEP 2). In this case, if (P ₁ − _{P i} ) is positive, the latest number of pulses input to register ₉₁
The fact that P ₁ is larger than the number of pulses P _i of the other registers 9 ₂ to 9 _N indicates that the latest number of pulses is on the rise. Conversely, if (P ₁ −P _i ) is negative, it indicates that the number of pulses is decreasing. (P ₁ −
If P _i ) is positive, the register 9 ₁ to which the latest pulse number is input in the first correction command circuit 17
The number of pulses in P ₁ and the number of pulses in other registers 9 ₂ to 9 _N
In order to correct the value of P _i by bringing it closer, each pulse number P ₂ ~
Issue a command to rewrite P _N with a predetermined value Y ₁ (STEP 3). This predetermined value Y ₁ is the latest pulse number P ₁
Alternatively, the value is "P ₁ -1", but in this embodiment, Y ₁ is set to "P ₁ -1". If (P ₁ −P _i ) is negative, in the second correction command circuit 18, the pulse number P ₁ of the register 9 ₁ to which the latest pulse number is input is
In order to correct the number of pulses P _i of the other registers 9 ₂ to 9 _N by bringing them closer to , a command is issued to rewrite each number of pulses P ₂ to P _N with a predetermined value Y ₂ (STEP 4). This predetermined value Y ₂
is the latest pulse number P ₁ or "P ₁ +1", but in this embodiment, Y ₂ is set to "P ₁ +1".
These registers 9 2 to ₉ to which correction commands have been issued by the first correction command circuit 17 or the second correction command circuit 18
The number of pulses P _i of 9 _N is corrected by the distributor 11 and transferred to each register 9 ₂ to 9 _N.
The number of pulses _{from 1} to 9 _N are added by an adder 12, and after a predetermined drive is performed by a latch circuit 13, a numerical value corresponding to the added value is displayed on a display section 14.

The operations in STEP 1 to STEP 4 above are for displaying a value close to the latest pulse number on the display unit ₁₄ when the number of pulses changes particularly rapidly _. The latest pulse number P ₁ ±
_The reason for setting it to 1 is that although the latest pulse number is input to register _{9 1} , it is not possible to predict the latest pulse number that will be input next. Part 14
Undershoot (display part 1)
This is to prevent the displayed value of 4 from being displayed smaller than the actual value) and overshoot (the displayed value of the display unit 14 being displayed larger than the actual value).

Next, in STEP 1, if |(P ₁ − P _i )|<2, the first consecutive number determination circuit 19 selects the register 9
₁ pulse number P ₁ includes this P ₁ and other registers 9 ₂
It is determined whether the number of pulses P ₂ to P _N of ~9 _N continues two or more times (STEP 5). In addition, if this occurs two or more times in a row, the number of consecutive times _K1 is counted and determined (STEP 6). Next, if the pulse number P ₁ is consecutive two or more times, the second consecutive number determination circuit 20
It is determined whether there is a value P _j other than the number of pulses P ₁ that is continuous two or more times in the registers 9 ₂ to 9 _N (STEP 7). If there is a value P _j that is continuous two or more times within the number of pulses P ₂ to P _N , the third correction command circuit 21 uses the number of pulses P ₁ to set the number of pulses in the register 9 _(K1+2) to 9 _N. Issue a command to rewrite P _(K1+2) ~P _N (STEP 8). Furthermore, in the fourth correction command circuit 22, the pulse number P _{(MK1+1) of the register 9 ( MK1} +1) is set at a value P _j that is a value other than the pulse number P ₁ and is repeated two or more times.
Rewrite the command and issue the command. However, M=2, 3,...N (STEP 9). In the operations of STEP 5 to STEP 9, the latest pulse number P ₁ does not change so rapidly as compared to the pulse numbers P ₂ to P _N , but the frequency of the input pulse is not constant (i.e., the number of consecutive input pulses In such cases, P 1 can be changed by rewriting the values of the number of pulses P ₁ to P _N into a sequence of numbers in a certain order according to the latest number of pulses _{P 1 .} Number of pulses that are regarded as main and remember the previous state P ₂ ~
It also takes P _N into account and displays values closer to the actual values. The number of pulses P ₂ to P _N for which the rewriting command was issued in STEP 8 and 9 is rewritten by the distributor 11 and transferred to each register 9 _{2 to N} , after which a predetermined control is performed and displayed on the display unit 14. be done.

Next, in STEP7, if there is no consecutive pulse number P ₁ , the third consecutive number determination circuit 23 determines that the value of the pulse number P ₁ does not include the registers 9 ₁ and 9 _N and is It is determined whether the registers 9 ₂ to 9 _N-1 are repeated two or more times in a row (STEP 10), and if it is consecutive two or more times, the consecutive number K ₂ is counted and determined (STEP 11).
Next, the number of consecutive pulses P ₁ including the register 9 ₁ is determined to be _one or more times in a row except for the consecutive registers including the register 9 ₁ and the consecutive registers including the register 9 _N. At this time, if it is continuous, count the number of consecutive times K ₂ and find it (STEP 11). Next, the consecutive number comparing circuit 24 compares whether the consecutive number _K1 is two or more larger than the consecutive number _K2 (STEP 12). If (K ₁ − K ₂ )≧2, the fifth correction command circuit 25 outputs the register 9 _(K1+2) with the number of pulses P ₁ .
~9 Issue a command to rewrite the number of pulses in _N (STEP13). Furthermore, the sixth correction command circuit 26
Issue a command to rewrite the number of pulses in the register (MK ₁ + 1) with a value P _K other than P ₁ (STEP 14). However, M=2, 3,...N. In addition, in STEP 1, it is determined that |(P ₁ − _{P i} )|≧2, so the value of the number of pulses for which the operations leading to STEP 10 to 14 are performed is the latest pulse number P ₁ and one other pulse. Number P _K
Therefore, this P _K is uniquely determined. In such STEP 10 to 14 operations, the latest pulse number P ₁ does not change as sharply as compared to the pulse numbers P ₂ to P _N , but the frequency of the input pulse is not constant (i.e., the number of consecutive input pulses varies). no regularity)
In this case, the latest input pulse P ₁ is stored continuously and it is determined that it is in a steady state to some extent. In such a case, the values of the number of pulses P ₂ to P _{N are} And by rewriting it into a sequence of numbers in a certain order according to the number of consecutive times,
It focuses on P ₁ and the number of consecutive pulses, and also takes into consideration the number of pulses P ₂ to P _N that store the previous state, and displays a value closer to the actual value more quickly. The number of pulses P ₂ to _{P N} issued the rewriting command in STEP 13 and 14 is rewritten by the distributor 11 and transferred to each register 9 ₂ to 9 _N ,
Thereafter, a predetermined control is performed and the information is displayed on the display unit 14.

In addition, if "NO" is obtained in STEP 5, 10, and 12, the latest pulse number P ₁ does not change so rapidly compared to other pulse numbers and the frequency of the input pulse is not determined to be constant, so it is left as is. Transferred to registers 9 ₂ to 9 _N without being rewritten,
After predetermined control is performed, the information is displayed on the display section 14.

Next, this specific operation will be explained with reference to a table.

First, the operations of STEP 1 to STEP 9 will be explained based on Table 1.

Table 1 shows the number of input pulses counted every 1/8 of the gate time, for example, in eight registers 9 ₁ to 9.
Display according to the contents of each register stored while sequentially shifting to 9 ₈ , the contents of each register after being rewritten by the arithmetic circuit 10 and distributor 11, and the stored contents of the register after being rewritten. A value B and a conventional display value C without such rewriting are shown.

In the initial state _t0 , "0" is stored in each register ₉₁ to ₉₈ , and the display value is also "0".

At counting time t ₁ , register 9 ₁ is input as input pulse.
"2" is input in the field. In reality, it is desirable to display a value "16" which is 8 times the value "2" of the register ₉₁ into which the latest pulse number is input, or a value close to it, but in the conventional example, "2" is displayed.
Therefore, in this embodiment, first, the comparison/judgment circuit 15 compares the latest pulse number P ₁ and other stored pulse numbers P _i
(i=2 to 8), and if it is determined that at least one of the differences exceeds the set value Since the number of input pulses is larger than other pulse numbers, it is determined that the number of input pulses is increasing, and the first correction command circuit 17 adjusts the number of pulses.
P ₂ to _{P 8} are set to a predetermined value Y ₁ (in this example, Y ₁ = P ₁ −1) =
Issue a command to rewrite with 1. Therefore, display section B after rewriting becomes "9", and by displaying this, a value close to the current desired display value "16" will be displayed.

At counting time t ₂ , the latest pulse number P ₁ is stored in register 9 ₁ .
When "4" is input as , the number of pulses P ₂ to _{P 8} becomes Y ₁ = P ₁ -1 = 4-1 by the same operation as t ₁ above.
=3, and the displayed value B becomes "25".
At this time, the desired display value is "32", which is eight times "4", but the conventional display value C would be "6" if it was not rewritten at _t1 , so in this embodiment, This means that a value close to the desired value can be displayed.

Next, at counting time _t11 , "0" is input to the register ₉₁ as the latest pulse number _P1 . At this time, if at least one of the differences between the latest pulse number P ₁ and the other pulse numbers P ₂ to P ₈ exceeds the set value Since the determination is made by the positive/negative determination circuit 16, the second
The correction command circuit 18 sets the number of pulses P ₂ to _{P 8} to a predetermined value.
A command is issued to rewrite Y ₂ (in this embodiment, Y ₂ =P ₁ +1)=1. As a result, the rewritten display value B becomes "7". Since the desired display value is "0" and the conventional display value C is "11", this embodiment allows a value close to the desired value to be displayed. This operation determines that the number of input pulses thereafter is on a decreasing trend because the latest pulse number P ₁ exceeds the set value X and is smaller than at least one of the other pulse numbers P ₂ to _{P 8} . .

Next, at counting time t ₂₁ , the latest pulse number is stored in register 9 ₁ .
“1” is input as P ₁ , and the comparison judgment circuit 15
It is determined that all the differences between the pulse number P ₁ and the other pulse numbers P ₂ to _{P 8} are within the set value X. This means that the latest pulse number P ₁ is the previously stored pulse number.
Since there is not much difference compared to P ₂ to _{P 8} , this indicates that the number of pulses inputted thereafter does not tend to increase or decrease, but is generally in a steady state. but,
In this case, the first consecutive number determination circuit 19
The latest pulse number P ₁ is "1" twice in a row, the consecutive number K ₁ is determined to be 2, and the second consecutive number determination circuit 20 determines that the pulse number P ₁ is "0" twice. Since it is determined that the input pulses are continuous, it is determined that the frequency of the input pulses is not constant, and even in such a case, the number of pulses P ₂ ~ in registers 9 ₂ ~ 9 _N
It is desirable to rewrite P _N to a certain number sequence according to P ₁ . Therefore, the third correction command circuit 21 issues a command to rewrite registers 9 ₍₂₊₂₎ to 9 ₈ with "1". Further, the fourth correction command circuit 22 inputs consecutive values "0" other than the pulse number P ₁ to registers 9 _(2M+1) (however, M=2, 3, 4...N), that is, registers 9 ₅ and 9. Issue a command to rewrite ₇ . In this case, the pulse numbers in the registers 9 ₂ to 9 ₈ are repeated in a sequence of numbers having a certain order [1.0]. In other words, when the number of input pulses tends to be approximately steady, even if there is a slight change in the latest number of input pulses, taking into account the number of previously input pulses that are stored,
Displays that match that trend will be displayed. In this case, the display value B is displayed as "5", and the desirable display value is "8", which is 8 times "1" if only the pulse number P ₁ is judged. Since there are many "0" pulses in the number of pulses, judging from this, the desirable display value is smaller than "8". That is, the display value B of this embodiment, which is "5", is a value close to that value.

Next, at counting time t ₃₁ , the latest pulse number is stored in register 9 ₁ .
"1" is input as _P1 . In this case, the comparison/judgment circuit 15 compares the number of pulses P ₁ and other numbers of pulses P ₂ to P ₈
It _is determined that all the differences between the two pulses are within the set value
It is determined that there are no consecutive occurrences including _P1 . In this case, it is not recognized that there is no sudden change in the latest input pulse number and the frequency of the input pulse is not constant, and in such a case there is no need to rewrite, so the value should be displayed as is. I made it.

■■■ Turtle Shell [0004] ■■■ Next, the operations in STEP 10 to 14 will be explained based on Table 2.

Usually, the number of registers for counting and storing pulses corresponding to changes in a measured quantity such as the running speed of a car is 10 to 20. The reason for the large number of registers is that the switching time per multi-divided gate time is shortened, and
This is because the accuracy can be improved because the display can be changed more quickly each time. The operations in STEP 10 to 14 become effective when the number of registers increases in this way, and Table 2 shows the number of input pulses counted every 1/12 of the gate time, for example, in 12 registers. The contents of each register stored while being shifted sequentially from 9 ₁ to 9 ₁₂ , the arithmetic circuit 10 and the distributor 11
The contents of each register after being rewritten by are shown.

At counting time _t41 , "1" is input to the register ₉₁ as the latest pulse number _P1 , and the comparison/judgment circuit 15 calculates all the differences between the pulse number _P1 and the other pulse numbers _P2 to _P12 as the set value X( X=2) or less. Then, the first consecutive number determining circuit 19 determines that the pulse number P ₁ "1" is consecutive two or more times and the consecutive number K 1 is 3, and the second consecutive number determining circuit 20 determines that the pulse number P 1 "_1" is consecutive two or more times and the consecutive number K 1 is 3. It is determined that a value other than the pulse number P ₁ is not consecutive two or more times, and the third consecutive number determination circuit 23
and the number of pulses P ₁ not including registers 9 ₁ and 9 _N
Determine whether "1" is consecutive two or more times. In this case, since the registers 9 ₅ and 9 ₆ are "1" twice in a row, the consecutive number K ₂ is 2. The consecutive number comparison circuit 24 compares the consecutive numbers K ₁ and K ₂ and calculates (K ₁ − _{K 2} )
= 1, so the number of pulses including register 9 ₁
The correction command is not transferred to the distributor 11 because there is no big difference between the consecutive number K ₁ of P ₁ and the consecutive number K ₂ of the pulse number P ₁ not including the register 9 ₁ , and there is no need to rewrite it into a certain sequence of numbers.

At counting time _t42 , "1" is newly input into the register ₉₁ as the latest pulse number _P1 . Below mentioned above t ₄₁
The explanation of the same operation will be omitted. The first consecutive number determination circuit 19 determines that the number of consecutive pulses _P1 is ₄ .
Further, the third consecutive number determining circuit 23 determines that the consecutive number K ₂ is 1. In this case, the consecutive number _K2 is determined to be 2 in registers ₉₆ to ₉₇ , and the consecutive number _K2 is determined to be 1 in registers ₉₉ and ₉₁₁ , but the smallest value is adopted for the consecutive number _K2 . do. Then, the consecutive number comparison circuit 24 calculates (K ₁
−K ₂ )=3 is determined later. This is because there is a difference between the consecutive number of pulses P ₁ including register 9 ₁ and _{the consecutive number K 2 of} pulse number P ₁ not including register 9 ₁ , and the values of registers 9 ₂ to 9 ₁₂ are kept constant. This is because the contents of the register can be brought closer to the newly input pulse number by rewriting them into an ordered number sequence.
Therefore, the fifth correction command circuit 25 uses the register 9
Issue a command to rewrite ₍₄₊₂₎ to 9 ₁₂ with the latest pulse number P ₁ , that is, "1". Furthermore, the sixth correction command circuit 26 has register 9 _(4M+1) (however, M=2, 3...N)
That is, a command is issued to rewrite the register ₉₉ with a value _PK other than the number of pulses _P1 , that is, "2". In this case, since there is always only one type of value other than the number of pulses _P1 , this value is uniquely determined. The number of pulses P ₁ to _{P 12} after this rewriting is a series of [1, 1, 1, 2)], and is a sequence of numbers in a certain order, so the number of pulses in the newer registers 9 ₁ to 9 ₅ is The most up-to-date display will be displayed.

Similarly, at counting time _t43 , the consecutive number _K1 is 5, and the consecutive number _K2 is 3. Therefore, registers 9 ₍₅₊₂₎ to 9 ₁₂ are rewritten with "1", and register 9 ₍₁₀₊₁₎ is rewritten with "2". Therefore,
The number of pulses P ₁ to P ₁₂ after rewriting is [1, 1, 1,
1, 2] and is a sequence of numbers in a certain order.

Furthermore, at the next counting time _t44 , "1" is written to register ₉₁ .
When , the number of consecutive pulses K ₁ becomes 6 and the number of consecutive pulses K ₂ becomes 4. Therefore, registers 9 ₍₆₊₂₎ to ₉₁₂ are rewritten as "1", and the number of pulses P ₁ to _{P 12} after rewriting is [ 1, 1, 1, 1, 1, 2], resulting in a sequence of numbers in a certain order.

Then, at the next counting time _t45 , when "1" is entered in register ₉₁ , the consecutive number _K1 becomes 7, and on the other hand, "1" is continuously written four times in registers ₉₉ to ₉₁₂ , and 2
Since there is a difference of 2 or more in the number of consecutive pulses, it seems to be rewritten as above, but the latest number of pulses
If P ₁ is continuous including the last stage register 9 ₁₂ , the number of pulses that have already been shifted out of register 9 from register 9 ₁₂ and erased from memory.
There is a possibility that P _N+1 , P _N+2 ... could have been "1", and therefore, simply determining based on the memory value existing in register 9 lacks accuracy when considered from a long time perspective. In such a case, that is, if the latest pulse number P ₁ is continuous including the last register 9 _{to 12} , it would be better not to force rewrite because the past history will be preserved. Since it is desirable, the determination of the consecutive number K ₂ is
It was decided to target only cases where the latest pulse number P ₁ does not include registers 9 ₁ and 9 ₁₂ .

■■■ Turtle Shell [0005] ■■■ Note that the number of pulses P ₁ , that is, the number of consecutive "1"s stored in the registers ₉₁ to ₉₁₂ after rewriting at counting times _t42 , _t43 , _t44 , etc. One time at a time
For example, at counting time t ₄₂ , P _1, that is, "1", occurs 4 times in registers 9 ₁ to _{9 4} and 3 times in registers 9 ₆ to _{9 8} , which is a difference of 1 time, but as shown in FIG. In addition, since the input pulse signal a and the gate signal b having multi-divided gate times are not synchronized, even if there is no fluctuation in the frequency of the input pulse signal a, the phase relationship between both signals a and b during counting is Since a maximum count difference of one occurs depending on the number of input pulses, the number of input pulses can be considered to be constant even in the case of the counting time described above.

As described above, according to the present invention, by using the latest input pulse number as the main pulse number and correcting the previously stored pulse number according to the sequence of previously stored pulse numbers, the gate time is The responsiveness of the displayed value to sudden changes in speed becomes faster, and the difference between the actual speed sensation value and the displayed value becomes very small.

Note that the set value Determined value Y
(Y ₁ , Y ₂ ) may be P ₁ instead of "P ₁ ±1" or a combination of both. Furthermore, the number of registers to be rewritten may be set in advance or the comparison/judgment circuit 15 may decide A method may also be used in which all or part of the registers 9 ₁ to 9 _N are selected depending on the result.

In addition, in order to correct the number of pulses in the registers 9 ₂ to 9 _N to a certain sequence of numbers in a certain order, the registers to be rewritten in the third and fifth correction command circuits 21 and 25 are set to the (K ₁ +2)th register and the fourth and sixth registers. Although the register to be rewritten in the correction command circuits 22 and 26 is set to the (MK ₁ +1)th register, this is just one example, and other methods are also possible.

As detailed above, according to the present invention, in a pulse counting device that counts and displays the number of pulses input within a certain gate time, by dividing the gate time into a plurality of times and counting the input pulses, Corrects the number of pulses counted within the gate time according to changes in the input pulse within the gate time,
By displaying the corrected results, it is possible to provide a pulse counting device with quick display response to sudden changes in input pulses.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional pulse counting device.
Fig. 2 is an explanatory diagram of the operation of the same device, Fig. 3 is a block diagram of a pulse counting device which is an embodiment of the present invention, Fig. 4 is a block diagram of a comparison/judgment circuit of the same device, and Fig. 5
The figure is a flowchart showing the operation of the comparison/judgment circuit, and FIG. 6 is a waveform diagram for explaining the pulse counting operation. 6...Input terminal, 8...Counter, _91-9N ...Register, 10...Arithmetic circuit _, 11...Distributor, 12...Adder, 14...Display section, 15...Comparison/judgment circuit, 16
...Positive/negative judgment circuit, 17...First correction command circuit, 1
8... Second correction command circuit, 19... First consecutive number determining circuit, 20... Second consecutive number determining circuit, 23... Third
consecutive number determination circuit, 24...consecutive number comparison circuit, 25
...Fifth correction command circuit, 26...Sixth correction command circuit.

Claims (1)

[Claims] 1 Divide the gate time that counts pulses generated in response to changes in the measured quantity into multiple parts, and store the number of pulses counted each time the divided gate time elapses in the first register among the multiple registers. After that, a new number of pulses counted each time is stored in the first register, and the number of pulses stored in each register up to that point is sequentially shifted to the subsequent registers and then entered in the final register. The number of pulses that were on is erased, the number of pulses in each register is corrected according to the latest number of pulses stored in the first register, and a value corresponding to the corrected value of all registers is displayed. In the pulse counting device, a first determining means determines whether the latest pulse number is continuous including the first register and obtains the first consecutive number; Determine if there are consecutive registers other than the register including the register, and check whether the second register is consecutive.
a second determining means for determining the consecutive number of , a comparing means for determining the difference between the first and second consecutive numbers, and a means for correcting the values of the registers other than the first register based on the comparison result. What is claimed is: 1. A pulse counting device comprising: a pulse counting device;