JPH0342816B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a master-slave frequency divider circuit using collector function logic.

[Technical Background of the Invention] In the field of measuring instruments, etc., when the frequency of the signal to be measured is high, it is often done by dividing the input frequency using a prescaler and performing measurements with the frequency reduced to a certain level. It is being said. For example, when two types of frequency division output, 1/N frequency division or 1/2N frequency division, are required, the prescaler has conventionally been constructed as shown in the block diagram of FIG. In other words, this prescaler is 1/2
A plurality of frequency dividing circuits 1 that perform frequency division are connected in multiple stages, and an input frequency fin is supplied to the first stage frequency dividing circuit 1.
Frequency divider circuit 1 of 1/N frequency division stage or 1/2N frequency division stage
The selection circuit 2 selects the output of
Two types of frequency-divided outputs of the frequency-divided signal are obtained.

Figure 3 shows the frequency dividing circuit 1 of each stage of the above prescaler.
FIG. 2 is a circuit diagram in which the circuit is realized using a master-slave T-type flip-flop of collector function logic (CFL). This master-slave T-type flip-flop is broadly divided into a clock input circuit section 10 and a master-slave type flip-flop circuit section 20.

The clock input circuit section 10 includes a differential pair 13 consisting of a pair of npn type transistors 11 and 12 whose emitters are connected in common and whose bases are supplied with a T input signal and its complementary signal. It consists of an npn type transistor 14 whose collector is connected to a common emitter of the transistors and whose base is supplied with a constant bias voltage _VBB for setting an operating current value, and an emitter resistor 15 of this transistor 14.

In the flip-flop circuit section 20, a differential pair 23 consisting of a pair of npn type transistors 21 and 22 having a multi-collector structure, each having an emitter connected in common and two collectors each, and a differential pair 23 each having an emitter connected in common and each having two collectors. A differential pair 26 consisting of a pair of npn type transistors 24 and 25 having a multi-collector structure and having two collectors is provided. The common emitter of the one differential pair 23 is connected to the collector of the transistor 11 in the clock input circuit section 10, and the common emitter of the other differential pair 26 is connected to the collector of the transistor 12 in the clock input circuit section 10. It is connected.

The first collectors C1 of the transistors 21 and 22 constituting the one differential pair 23 are connected to the positive power supply voltage V _CC application point via load resistors 27 and 28, respectively. Similarly, the first collectors C1 of the transistors 24 and 25 constituting the other differential pair 26 are connected to load resistors 29 and 30, respectively.
They are connected to the power supply voltage V _CC application point through each. The first collector C1 of the transistor 21 is connected to the base of an npn type transistor 31 whose collector is connected to the power supply voltage V _CC application point, and the emitter of this transistor 31 is connected to the base of the transistor 22 and the current source 32. connected to one end of the The first collector C1 of the transistor 22 has a collector at the power supply voltage.
NPN transistor 3 connected to V _CC application point
The emitter of this transistor 33 is connected to the base of the transistor 21 and one end of a current source 34. Similarly, the first collector C1 of the transistor 24 is an npn whose collector is connected to the power supply voltage V _CC application point.
The emitter of this transistor 35 is connected to the base of a transistor 35 of the type transistor 25.
and one end of the current source 36. The first collector C1 of the transistor 25
is connected to the base of an npn type transistor 37 whose collector is connected to the power supply voltage V _CC application point, and the emitter of this transistor 37 is connected to the base of the transistor 24 and one end of a current source 38 . Note that the current sources 32, 34,
The other ends of each of 36 and 38 are connected in parallel to the ground potential GND application point.

Transistors 21 and 2 of the one differential pair 23
2, each of the second collectors C2 of the transistors 25 and 24 of the other differential pair 26 are connected to each of the first collectors C1 of the transistors 25 and 24 of the other differential pair
transistor 2 of the other differential pair 26
The second collectors C2 of the transistors 4 and 25 are connected to the first collectors C1 of the transistors 21 and 22 of one differential pair 23, respectively. That is, one differential pair 23, load resistors 27 and 28, and transistor 3
1, 33 and current sources 32, 34 constitute a master flip-flop and its output circuit, and the other differential pair 26, load resistors 29, 30, transistors 35, 37, and current sources 36, 38 constitute a slave flip-flop. constitutes a flip-flop and its output circuit section,
The Q output signal is from the emitter of transistor 37.
The output signal complementary to the Q output signal is from transistor 3.
The signals are output from each of the 5 emitters.

In a T-type flip-flop with such a configuration, when the input signal is at the "H" level, the transistor 1
2 is turned on and the differential pair 26 is operating, the Q output signal is at the "H" level and the output signal is at the "L" level. At this time, on the slave flip-flop side, the transistor 37
The signal at the base of the transistor 35, that is, the signal at the first and second collectors C1 and C2 of the transistor 25 goes to "H" level, and the signal at the base of the transistor 35, that is, the signal at the first and second collectors C1 and C2 of the transistor 24,
The signals of 1 and C2 are set to "L" level. Therefore, at this time, on the master flip-flop side, the transistor 33 is turned on and the base signal of the transistor 21 is set to "H" level, and the transistor 31 is turned off and the base signal of the transistor 22 is set to the "H" level. is set to "L" level.

Next, when the T input signal is set to the "H" level and the transistor 11 is turned on, the differential pair 23 is activated. In the previous state, the signal at the base of the transistor 21 was at the "H" level and the signal at the base of the transistor 22 was at the "L" level, so when the T input signal was set at the "H" level, the transistor 21 is on,
Transistor 22 is turned off. As a result, the first and second collectors C of the transistor 21
The signals of the first and second collectors C1 and C2 of the transistor 22 are set to the "H" level. Therefore, at this time, the transistor 37 on the slave flip-flop side
is turned off and the base signal of the transistor 24, that is, the Q output signal, is set to the "L" level, and the transistor 35 is turned on, and the base signal of the transistor 25, that is, the output signal is set to the "L" level. Ru.

Next, when the input signal is set to "H" level and the transistor 12 is turned on, the differential pair 26 is turned on again.
is put into motion. In the previous state, the signal at the base of the transistor 24 was at the "L" level and the signal at the base of the transistor 25 was at the "H" level, so when the input signal was set at the "H" level, the transistor 24 In the off state, the transistor 25 is turned on. As a result, the signals at the first and second collectors C1 and C2 of the transistor 24 are set to "H" level, and the signals at the first and second collectors C1 and C2 of the transistor 25 are set to "L" level.
be leveled. At this time, the transistor 37 remains off and the transistor 35 remains on, so the Q output signal and the output signal remain at the "L" level and "H" level, respectively, and do not change. Further, on the master flip-flop side, the transistor 33 is turned off and the signal at the base of the transistor 21 is set to the "L" level, and the transistor 31 is turned on and the signal at the base of the transistor 22 is set to the "H" level. It has been leveled.

Next, the T input signal is set to "H" level, and the transistor 11 is turned on. In the previous state, the signal at the base of transistor 21 was at "L" level, and the signal at the base of transistor 22 was at "H" level.
Since the T input signal is set to the "H" level, the transistor 21 is turned off and the transistor 22 is turned on. As a result, the signals at the first and second collectors C1 and C2 of the transistor 21 are set to the "H" level, and the signals at the first and second collectors C1 and C2 of the transistor 22 are set to the "L" level. Therefore, at this time,
On the slave flip-flop side, transistor 3
7 is turned on and the Q output signal is set to "H" level, and the transistor 35 is turned off and the Q output signal is set to "H" level.
The output signal is set to "H" level. Thereafter, by alternately setting the T input signal or the input signal to the "H" level, the Q output signal and the output signal are divided by 1/2 of the T input signal and the input signal as shown in the timing chart of Fig. 4. It becomes a signal.

FIG. 5 is a circuit diagram in which the prescaler selection circuit 2 is implemented using emitter coupled logic (ECL). This selection circuit selects one input signal IN1.
and 1 are supplied to their respective bases, and a differential pair 43 consisting of a pair of npn type transistors 41 and 42 whose emitters are commonly connected, and the other input signals IN2 and 2 are supplied to their respective bases, and whose emitters are connected in common. A differential pair 46 consisting of a pair of commonly connected npn type transistors 44 and 45
and a differential pair 49 consisting of a pair of npn type transistors 47 and 48 whose emitters are connected in common, with a switching control signal M being supplied to one base and a predetermined bias voltage V _BI being supplied to the other base.
and an npn transistor 5 whose collector is connected to the common emitter of the differential pair 49 and whose base is supplied with a constant bias voltage V _BB for setting the operating current value.
0 and the emitter resistance 51 of this transistor 50
and a common collector load resistance 52 of the transistors 41 and 45 and the transistors 42 and 44.
A common collector load resistor 53.

In this selection circuit, by setting the switching control signal M to a voltage sufficiently higher than the bias voltage V _BI , the differential pair 43 operates and one of the input signals IN1 and 1 is selected as the output signal OUT. On the other hand, by setting the control signal M to a voltage sufficiently lower than the bias voltage _VBI , the differential pair 46 operates and the other input signals IN2 and IN2 are selectively output as the output signal OUT. .

[Problems with the Background Art] By the way, the master-slave T-type flip-flop with collector-function logic shown in FIG. 3 above and the selection circuit realized with emitter-coupled logic shown in FIG. When configuring a prescaler as shown, an independent circuit is used as a selection circuit, so there is a drawback that the total number of elements increases.

[Purpose of the invention] This invention was made in consideration of the above circumstances, and its purpose is to make it possible to select 1/2 frequency division or 1/2N frequency division with a smaller number of elements compared to conventional circuits. An object of the present invention is to provide a frequency dividing circuit that can configure a possible prescaler.

[Summary of the invention] In order to achieve the above object, this invention has the following features:
a clock input circuit section comprising first and second transistors having respective complementary clock signals coupled to their bases and having their emitters coupled;
a master flip-flop comprising first and second multi-collector transistors and third and fourth multi-collector transistors each having an emitter coupled to the collector of the first and second transistor; The collector function logic divider circuit section consists of a master-slave type flip-flop circuit having a slave flip-flop, and a fifth and sixth multi-collector transistor whose bases are connected to each other. One collector of each of the multi-collector transistors is coupled to a high potential power supply voltage, the other collectors of each of the fifth and sixth multi-collector transistors are coupled to a pair of output terminals of the frequency dividing circuit section, and a fifth and the respective emitters of the sixth multi-collector transistor are coupled to the respective collectors of the first and second transistors, and the frequency of the clock signal is divided by half and outputted to the fifth and sixth base coupling portions. A control signal is coupled to the first and second, third and fourth multi-collector transistors of the master flip-flop and slave flip-flop in response to this control signal. A control circuit section is provided which clamps each emitter coupling section with the power supply voltage and bypasses the complementary clock signal coupled to the clock input circuit section to the output end of the frequency dividing circuit section. In the above frequency dividing circuit section, 1/
It is designed to control whether or not to perform frequency division by two.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of an embodiment of the frequency divider circuit according to the present invention, which is used in place of the frequency divider circuit 1 and the selection circuit 2 at the final stage of the circuit shown in FIG. . The frequency divider circuit of this embodiment has almost the same structure as the master-slave T-type flip-flop shown in FIG. 3, except that the first and second collectors C1 and C2 are provided, respectively. A pair of npn type transistors 61 and 62 having a multi-collector structure are provided. The bases of both transistors 61 and 62 are connected in common, and a switching control signal M is input to this common base.
Further, the emitter of the one transistor 61 is connected to the transistor 1 in the clock input circuit section 10.
1 and the other transistor 6
The second emitter is also connected to the clock input circuit section 1.
It is connected to the collector of transistor 12 in 0. The first collector C1 of the one transistor 61 is connected to the power supply voltage V _CC application point,
The second collector C2 is connected to the base of the transistor 35. The first collector C1 of the other transistor 62 is connected to the power supply voltage V _CC application point, and the second collector C2 is connected to the base of the transistor 37.

In the frequency divider circuit having such a configuration, a case will now be described in which the control signal M input to the bases of the transistors 61 and 62 is set to the "L" level. Note that the "L" level of this signal M is npn
The voltage between the base and emitter of a type transistor is V _BE
The potential is less than V _CC −V _BE . now,
The collector potential of transistor 11 or 12 is V _CC , which is the value obtained by subtracting the base-to-emitter voltage of approximately two transistors, 2 V _BE, from the power supply voltage V _CC.
-2V _BE , so when the "L" level control signal M is input to the base of the transistor 61,
62 are both turned off. Therefore, both transistors 61 and 62 are connected to the flip-flop circuit section 2.
0 has no effect, and the circuit of this embodiment divides the frequency of the input signal T by 1/2 and outputs the frequency-divided signal T as shown in the timing chart of FIG. 4, similar to the circuit of FIG.

On the other hand, when the control signal M is set to "H" level, which is a potential higher than V _CC −V _BE , transistor 1
The collector potential of transistors 1 or 12 is clamped to V _CC -V _BE , and transistors 21, 22, 24, and 25 in flip-flop circuit section 20 are all cut off.

In this state, the T input signal input to the transistor 11 in the clock input circuit section 10 is "H".
When the level is set, a current flows through the load resistor 29 and the transistors 61 and 11 as shown by the broken arrow a in FIG. 1, and the signal at the base of the transistor 35 is set to the "L" level. . On the other hand, the base of the transistor 37 is set to "H" level by the load resistor 30. As a result, the Q output signal becomes "H" level, and the Q output signal becomes "L" level.

Next, when the input signal input to the transistor 12 in the clock input circuit section 10 is set to the "H" level, the load resistor 30 and the transistors 62 and 12 are turned on as shown by the broken arrow b in FIG. A current flows through the transistor 37, and the signal at the base of the transistor 37 is set to the "L" level. On the other hand, the base of the transistor 35 is set to the "H" level by the load resistor 29. As a result, the Q output signal becomes "L" level and the Q output signal becomes "H" level.

That is, when the control signal M is set to the "H" level, this circuit acts as a mere buffer circuit for the T input signal and the input signal, and the input signal is output as is.

Therefore, in this embodiment circuit, the switching control signal M
By setting the level of
It is possible to select whether to divide the frequency and output it, or to output the input signal as it is.

Here, in this embodiment circuit, two transistors 61 and 6 are newly added to the circuit shown in FIG.
Although it is necessary to add 2 transistors, the selection circuit shown in FIG. 5 is unnecessary, and compared to the case where this selection circuit is used, 5 transistors and 3 resistors can be reduced. Therefore, by using the frequency dividing circuit of this embodiment, a prescaler can be configured with a smaller number of elements than the conventional one. Furthermore, since the number of elements can be reduced, power consumption can also be reduced.

[Effects of the Invention] As explained above, according to the present invention, frequency division by 1/2 or 1/2 can be achieved with a smaller number of elements compared to conventional circuits.
It is possible to provide a frequency dividing circuit that can configure a prescaler that can select N frequency division.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional prescaler,
Figure 3 is a circuit diagram of the frequency divider circuit used in the prescaler of Figure 2, Figure 4 is a timing chart showing the operation of the frequency divider circuit of Figure 3, and Figure 5 is a circuit diagram of the frequency divider circuit used in the prescaler of Figure 2. FIG. 2 is a circuit diagram of a selection circuit. 10...Clock input circuit section, 13, 23, 2
6...differential pair, 20...master-slave type flip-flop circuit section, 61, 62...npn type transistor.

Claims (1)

[Claims] 1. Complementary clock signals are coupled to the base, and the emitters of the first and second clock signals are coupled to each other.
a clock input circuit section composed of transistors; and a first and second transistor, a third and a fourth transistor, each having an emitter coupled thereto, and this emitter coupling section being coupled to each collector of the first and second transistors. A collector function logic frequency divider circuit section consisting of a master/slave type flip-flop circuit having a master flip-flop circuit and a slave flip-flop circuit each constructed of a multi-collector transistor, and fifth and sixth multi-channel circuits whose bases are connected to each other. collector transistors, one collector of each of the fifth and sixth multi-collector transistors are both coupled to a high potential power supply voltage;
The other collectors of the and sixth multi-collector transistors are coupled to a pair of output terminals of the frequency dividing circuit section, and the emitters of the fifth and sixth multi-collector transistors are coupled to the respective emitters of the first and second transistors. A control signal is coupled to the fifth and sixth base coupling portions for determining whether to divide the clock signal by half and output it, or to pass it through and output it as is. In response to a control signal, the emitter coupling portions of the first, second, third and fourth multi-collector transistors of the master flip-flop and slave flip-flop are clamped to a power supply voltage, and are coupled to the clock input circuit portion. and a control circuit section that bypasses the complementary clock signal to the output terminal of the frequency dividing circuit section.