JPH0342819B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an up-down counter that operates in synchronization with a clock signal, and is an improvement that prevents a decrease in operating speed especially when a multi-bit configuration is used. Regarding.

[Technical background of the invention and its problems] FIG. 5 is a circuit diagram showing the configuration of a conventional up-down counter. This counter has a 4-bit configuration and includes one D-type flip-flop 1,
Three JK flip-flops 2 to 4 and logic circuits 5 to 7, etc., each consisting of two AND gates 11, 12 and one OR gate 13 for forming J and K input signals to these JK flip-flops. It consists of
A clock signal CK is supplied in parallel to each synchronizing signal input terminal of the D-type flip-flop 1 and JK flip-flops 2 to 4. Furthermore, the output terminal and data input terminal of the D-type flip-flop 1 are short-circuited to form a binary counter, and the Q output signal Q0 is the output signal of the least significant bit, that is, the 0th bit of this counter. The JK flip-flops 2 to 4 are configured such that the output signals of the corresponding ones of the three logic circuits 5 to 7 are supplied to the respective J and K signal input terminals, and the Q output signals Q1 of these flip-flops 2 to 4 are supplied. , Q2, and Q3 are output signals from the 1st bit to the 3rd bit of this counter.

The Q output signal Q0 of the D-type flip-flop 1 and the up/down mode switching signal U/D are supplied in parallel to the AND gate 11 in the logic circuit 5. is supplied with signal 0 and an inverted signal of signal U/D in parallel, and both AND gates 11, 1
Two output signals are supplied to the OR gate 13 in parallel. The output signal of this OR gate 13 is supplied to the 1st bit JK flip-flop 2 as J and K input signals.

The AND gate 11 in the logic circuit 6 above has a JK
Q output signal Q1 of flip-flop 2, Q output signal Q0 of D-type flip-flop 1, and up/down
A down mode switching signal U/D is supplied in parallel,
Another AND gate 1 in the same logic circuit 6
2 are supplied with signals 1, 0 and an inverted signal of U/D in parallel, and both AND gates 11, 1
Two output signals are supplied to the OR gate 13 in parallel. The output signal of this OR gate 13 is supplied to the second bit JK flip-flop 2 as J and K input signals.

The AND gate 11 in the logic circuit 7 has the above
The Q output signal Q2 of the JK flip-flop 3, the Q output signal Q1 of the JK flip-flop 2, the Q output signal Q0 of the D flip-flop 1, and the up/down mode switching signal U/D are supplied in parallel,
Another AND gate 1 in the same logic circuit 7
2 are supplied with signals 2, 1, 0 and an inverted signal of signal U/D in parallel, and the output signals of both AND gates 11 and 12 are supplied with OR gate 13 in parallel. The output signal of this OR gate 13 is then applied to the third bit of JK flip-flop 4.
are supplied as J and K input signals.

In such a conventional counter, in the logic circuits 5, 6, and 7 that form the input signals of the JK flip-flops 2, 3, and 4, the number of input terminals of the AND gates 11 and 12 increases one by one as the bits become more significant. are doing. For this reason, the more a multi-bit counter is configured, the greater the number of logic circuit elements that form the flip-flop input signal.
The disadvantage is that the total number of elements increases exponentially as the number of bits increases. By the way,
When realizing a counter as shown in FIG. 5 with a CMOS configuration, the total number of elements M is expressed by the following equation, where m is the number of bits.

M= _∞ 〓 ^m=1 {68+46(m-2)+(m-3)}...1 Therefore, in the course of this invention, the inventors decided to reduce the number of elements even in the case of a multi-bit configuration. We have invented an up-down counter that does not increase abnormally and can be constructed with a smaller number of elements than conventional circuits. This counter is described in the specification and drawings attached to Japanese Patent Application No. 59-144678, and its configuration is shown in the circuit diagram of FIG. This counter also has a 4-bit configuration, and uses logic circuit 2 instead of logic circuits 5, 6, and 7 in the conventional circuit.
1, 22, and 23 are used.
The first stage logic circuit 21 is a NOR gate 3 to which the Q signal 0 of the D-type flip-flop 1 and the up/down mode switching signal U/D are respectively supplied in parallel.
1 and NAND gate 32, the above NAND gate 3
2 and a NAND gate 34 to which the output signal of the NOR gate 31 is supplied in parallel via an inverter 33.
The output signal of 4 is sent to the above JK flip-flop 2.
It is supplied as K input.

The next stage logic circuit 22 is the first stage logic circuit 21.
The output signal of the inverter 33 in the first stage logic circuit 21 and the output signal of the NAND gate 32 in the first stage logic circuit 21 are supplied to the NOR gate 31, to which the output signal of the inverter 33 in the first stage and the output signal 1 of the JK flip-flop 2 are supplied in parallel. A NAND gate 43 is supplied in parallel via an inverter 42, the output signal of the NAND gate 43 and the NOR gate 41
and a NAND gate 45 to which the output signal of is supplied in parallel via an inverter 44.
The output signal of the NAND gate 45 is supplied to the JK flip-flop 3 as J and K inputs.
The subsequent logic circuits, that is, the logic circuit 23, are constructed in the same manner as the logic circuit 22 described above, and only the input signal is different.

In a counter having such a configuration, the NOR gate 41 and the NAND gate 43 always have two input terminals each, regardless of the bit position in the logic circuit that supplies input signals to each J flip-flop.
Therefore, even if a multi-bit counter is constructed, the rate at which the number of elements increases can be reduced compared to conventional counters. In this way, the counter of FIG. 6 can reduce the number of elements compared to the conventional counter.

By the way, the up/down mode switching signal U/
D is the logic circuit 21 of each stage sequentially from the least significant bit,
22 and 23, especially in the up count mode where the up/down mode switching signal U/D is set to 0 level, this signal U/D is transmitted to the NOR gate 31 in the first stage logic circuit 21. The signal is transmitted through the inverter 33 in series, and in the other logic circuits, the signal is transmitted through the NOR gate 41 and the inverter 44 in series. For this reason, the higher the number of bits is configured, the slower it becomes to determine the level of the J and K input signals supplied to each JK flip-flop in the subsequent stage, which may lead to malfunctions when operated with a high-speed clock signal CK. There is.

[Object of the Invention] The present invention has been made in consideration of the above-mentioned circumstances, and its object is to provide an up-down counter that has a small number of elements and is capable of high-speed operation.

[Summary of the invention] In order to achieve the above object, this invention has the following features:
The 0th bit, which is the least significant bit, is divided by dividing the clock signal.
A binary counter that obtains a count output signal for the 1st bit to the nth bit, and a binary counter that inverts the level of the output signal in synchronization with the clock signal when the input signal is at one logic level, and outputs the 1st bit to the nth bit count output signal. The flip-flop is inserted between the n flip-flops that obtain the count output signal of the binary counter and the first bit, and the flip-flop that obtains the count output signal of the binary counter and the up/down mode switching signal. a third logic gate that inverts the output signal of the second logic gate; and a third logic gate that inverts the output signal of the second logic gate. a fourth logic gate that obtains an AND signal of the output signals; a first logic circuit that supplies the output signal of the fourth logic gate as an input signal to the first bit flip-flop; The n flip-flops are inserted between the n flip-flops for obtaining count output signals of the 1st bit to the nth bit, and each of them is connected to the first, second, third and fourth logic gates in the same way as the first logic circuit. and the second to nth
, and the first and second logic gates in the i-th (i=2 to n) logic circuit among the second to n-th logic circuits include an (i-1)th bit. The count output signal of the flip-flop and the output signals of the first and second logic gates in the (i-1)th logic circuit are respectively supplied to obtain the count output signal of the i-th logic circuit. The third logic gate is supplied with the output signal of the second logic gate in the i-th logic circuit, and the fourth logic gate in the i-th logic circuit is supplied with the output signal of the second logic gate in the i-th logic circuit. The output signals of three logic gates are supplied to reduce the number of gates present in the transmission path of the up/down mode switching signal in the first and second to nth logic circuits.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an up-down counter according to the present invention which has a 4-bit output. A clock signal CK is supplied in parallel to each synchronizing signal input terminal of the D-type flip-flop 51 and the JK flip-flops 52 to 54. The output terminal and data input terminal of the D-type flip-flop 51 are short-circuited to form a binary counter, and the Q output signal Q0 is the lowest bit of this counter, that is, 0.
The output signal is set as the bit-th output signal. The JK flip-flops 52 to 54 are configured such that the output signals of the corresponding ones of the three logic circuits 55 to 57 are supplied to the respective J and K signal input terminals, and the Q output signals Q1, Q2 and Q3 are used as output signals for the first to third bits of this counter.

The logic circuit 55 is a D-type flip-flop 51.
and the JK flip-flop 52, and this logic circuit 54 includes a NAND gate 61 and a NOR gate 62, to which the Q signal Q0 of the D-type flip-flop 51 and the up/down mode switching signal U/D are respectively supplied in parallel. It consists of a NAND gate 64 to which the output signal of the NAND gate 61 and the output signal of the NOR gate 62 are supplied in parallel via an inverter 63. The output signal of the NAND gate 64 is supplied to the JK flip-flop 52 as J and K inputs.

The next stage logic circuit 56 is a JK flip-flop 5
2 and 53, and is inserted between the NAND gate 61 and the NOR gate 6 in the logic circuit 55.
2 output signals respectively JK flip-flop 52
The NAND gate 74 includes a NAND gate 71 and a NAND gate 72 to which the output signal 1 of the NAND gate 72 is supplied in parallel, and a NAND gate 74 to which the output signal of the NAND gate 72 and the output signal of the NOR gate 71 are supplied in parallel via an inverter 73. The output signal of the NAND gate 74 is supplied to the JK flip-flop 53 as J and K inputs.

The next stage logic circuit 57 is a JK flip-flop 5
3 and 54, and similarly to the logic circuit 56, a NOR gate 71 and a NAND gate 7
2, an inverter 73 and a NAND gate 74. The NAND gate 71 and the NAND gate 72 in the logic circuit 57 are connected to the NAND gate 71 and the NAND gate 72 in the logic circuit 56.
2 output signals each and JK flip-flop 5
Three Q output signals Q2 are supplied in parallel. The output signal of the NAND gate 72 and the output signal of the NOR gate 71 are supplied in parallel to a NAND gate 74 via an inverter 73, and the output signal of this NAND gate 74 is supplied to the JK flip-flop 54 as J and K inputs. There is.

That is, the logic circuit 55 is supplied with the Q output signal of the D-type flip-flop 51 and the signal U/D.
Logic circuit 55 generates input signals for JK flip-flop 52 from these signals. The next logic circuit 56 contains the intermediate signal of the logic circuit 55.
The output signals of the JK flip-flop 52 are supplied, and this logic circuit 56 receives the output signals of the JK flip-flop 52 from these signals.
Generates an input signal for flip-flop 53. The next logic circuit 57 is supplied with the intermediate signal of the logic circuit 56 and the Q output signal of the JK flip-flop 53, and this logic circuit 57 generates an input signal for the JK flip-flop 54 from these signals. In this way, the Q output signal of the D-type flip-flop 51 is supplied to the logic circuit 55.
The logic circuit 56 is supplied with the output signal of the JK flip-flop 56, and the logic circuit 57 is supplied with the output signal of the JK flip-flop 56.
The Q output signals of the JK flip-flop 57 are supplied to the three logic circuits 55 and 5.
6 and 57 are alternately supplied with the Q and output signals of the D type flip-flop and the JK flip-flop 52 and 53.

Next, the operation of the circuit configured as above will be explained. The counter of this embodiment operates as an up counter by setting the up/down mode switching signal U/D to 1 level, and vice versa.
It operates as a down counter by setting it to 0 level.

First, the up-count operation will be explained using the timing chart shown in FIG. Since the D-type flip-flop 51 successively divides the frequency of the clock signal CK by two, its count output signal Q0 becomes a signal having a period twice that of CK, as shown in FIG.
Since the signal U/D is at the 1 level at this time, the output signal of the NOR gate 62 in the logic circuit 55 remains at the 0 level regardless of the Q output signal of the D flip-flop 51. On the other hand, NAND gate 61 inverts Q output signal Q0 of D-type flip-flop 51 and supplies it to NAND gate 64.
Here, the output signal of the NOR gate 62 is set to 0 level, and the output signal of the inverter 63 following this is set to 1 level, so the NAND gate 64 acts as an inverter that inverts the output signal of the NAND gate 61. Therefore, the J and K input signals supplied from this logic circuit 55 to the JK flip-flop 52 are in phase with the signal Q0. Obtain the 1st bit count output signal Q1
The JK flip-flop 52 has the above logic circuit 55.
When the output signal from the clock signal is set to 1 level, the level of the output signal is inverted in synchronization with the rising edge of the clock signal CK. In the initial state, if the Q output signal Q1 of this JK flip-flop 52 is set to 0 level, this signal Q1 changes in synchronization with the falling edge of signal Q0 as shown in FIG. This results in a signal with twice the period.

In the next logic circuit 56, the NAND gate 72
is supplied with the output signal of the NOR gate 62 in the logic circuit 55 which is always at the 0 level. Therefore, the output signal of this NAND gate 72 is always at 1 level. On the other hand, Noah Gate 71 is a JK
It acts as an inverter to invert the output signal 1 of flip-flop 52, and its output signal is fed to a NAND gate 74, which also acts as an inverter. Therefore, from this logic circuit 56
The J and K input signals supplied to the JK flip-flop 53 are in phase opposite to signal 1, that is, in phase with Q1. This JK flip-flop 53 inverts the level of the output signal in synchronization with the rise of the clock signal CK when the output signal from the logic circuit 56 is at 1 level. In the initial state, if the Q output signal Q2 of this JK flip-flop 53 is set to 0 level, this signal Q2 changes in synchronization with the falling edge of the signal Q1 as shown in FIG. This results in a signal with four times the period.

In the next logic circuit 57, the NOR gate 71 is supplied with the output signal of the NAND gate 72 in the logic circuit 56, which is always at the 1 level. Therefore, the output signal of this NOR gate 71 is always at 0 level, and the output signal of inverter 73 following it is always at 1 level. On the other hand, NAND gate 72 acts as an inverter to invert the Q output signal Q2 of JK flip-flop 53, and its output signal is supplied to NAND gate 74, which also acts as an inverter. Therefore, the J and K input signals supplied from this logic circuit 57 to the JK flip-flop 54 are in phase with the signal Q2. This JK flip-flop 54 inverts the level of its output signal in synchronization with the rise of the clock signal CK when the output signal from the logic circuit 56 is at 1 level. In the initial state, if the Q output signal Q3 of this JK flip-flop 54 is set to 0 level, this signal Q3 changes in synchronization with the falling edge of signal Q2 as shown in FIG. This results in a signal with eight times the period.

In this way, when the signal U/D is at 1 level, this counter operates as an up counter, and its counting state increases sequentially in binary as shown in FIG.

Next, the down-counting operation will be explained using the timing chart shown in FIG. Since the D-type flip-flop 51 sequentially divides the frequency of the clock signal CK by two as in the up-count operation, its count output signal Q0 becomes a signal having a period twice that of CK. Since the signal U/D is at the 0 level at this time, the output signal of the NAND gate 61 in the logic circuit 55 remains at the 1 level regardless of the Q output signal of the D flip-flop 51. On the other hand, NOR gate 62 inverts Q output signal Q0 of D-type flip-flop 51 and supplies it to NAND gate 64 via inverter 63. Therefore, the J and K input signals supplied from this logic circuit 55 to the JK flip-flop 52 are in phase opposite to the signal Q0. Obtain the 1st bit count output signal Q1
The JK flip-flop 52 has the above logic circuit 55.
When the output signal from the clock signal is set to 1 level, the level of the output signal is inverted in synchronization with the rising edge of the clock signal CK. In the initial state, if the Q output signal Q1 of this JK flip-flop 52 is set to 0 level, this signal Q1 changes in synchronization with the rise of signal Q0 as shown in FIG. The signal will have twice the period.

In the next logic circuit 56, the NOR gate 71 is supplied with the output signal of the NAND gate 61 in the logic circuit 55, which is always at the 1 level. Therefore, the output signal of this NOR gate 71 is always at 0 level, and the output signal of inverter 73 following it is always at 1 level. On the other hand, NAND gate 72 acts as an inverter to invert the output signal Q1 of JK flip-flop 52, and its output signal is supplied to NAND gate 74, which also acts as an inverter. Therefore, the J and K input signals supplied from this logic circuit 56 to the JK flip-flop 53 are in phase with signal 1. This JK flip-flop 53 inverts the level of the output signal in synchronization with the rise of the clock signal CK when the output signal from the logic circuit 56 is at 1 level. In the initial state, if the Q output signal Q2 of this JK flip-flop 53 is set to 0 level, this signal Q2 changes in synchronization with the rise of signal Q1 as shown in FIG. The signal will have twice the period.

In the next logic circuit 57, the NAND gate 72
is supplied with the output signal of the NOR gate 71 in the logic circuit 56 which is always at the 0 level. Therefore, the output signal of this NAND gate 72 is always kept at 1 level. On the other hand, NOR gate 71 acts as an inverter to invert the Q output signal Q2 of JK flip-flop 53, and its output signal is supplied via inverter 73 to NAND gate 74, which also acts as an inverter. Therefore,
From this logic circuit 57 to the JK flip-flop 54
The J and K input signals supplied to the signal Q2 are in opposite phase to the signal Q2. This JK flip-flop 54 inverts the level of its output signal in synchronization with the rise of the clock signal CK when the output signal from the logic circuit 56 is at 1 level. In the initial state, if the Q output signal Q3 of this JK flip-flop 54 is set to 0 level, this signal Q3 changes in synchronization with the rise of signal Q2 as shown in FIG. The signal will have twice the period.

In this manner, when the signal U/D is at the 0 level, this counter operates as a down counter, and its counting state sequentially decreases in binary as shown in FIG.

By the way, in a counter with such a configuration, in each logic circuit that supplies input signals to each JK flip-flop, the number of input terminals of the NOR gate 71 and NAND gate 72 is 2, regardless of the position of the bit.
One book at a time. Therefore, even if a multi-bit counter is constructed, the rate at which the number of elements increases is smaller than in the conventional case.

Moreover, in the above embodiment circuit, in both up/down count modes in which the up/down mode switching signal U/D is set to 1 level and 0 level,
This signal U/D only passes through one NOR gate or NAND gate in each logic circuit. Therefore, the malfunction that occurs when operating with the high speed clock signal CK, which has been a problem particularly in the up-count mode in the circuit of FIG. 6, is shifted to the higher frequency side. Therefore, the circuit of the above embodiment can realize high-speed operation.

FIG. 4 is a circuit diagram showing the configuration of another embodiment of the present invention. In the above embodiment circuit, the logic circuit 55
is supplied with the Q output signal of the D-type flip-flop 51 and the signal U/D, and this logic circuit 55 generates an input signal for the JK flip-flop 52 from these signals. signal and JK flip-flop 52
This logic circuit 56 generates an input signal for the JK flip-flop 53 from these signals, and the next logic circuit 57 receives the intermediate signal of the logic circuit 56 and the Q output signal of the JK flip-flop 53. and this logic circuit 5
7, from these signals JK flip-flop 5
The Q output signal of the D-type flip-flop 51 is supplied to the logic circuit 55, the output signal of the JK flip-flop 56 is supplied to the logic circuit 56, and the input signal of the JK flip-flop 56 is supplied to the logic circuit 57. 57 Q output signals are supplied to each of the three logic circuits 5.
5, 56, 57 have flip-flops and JK
This is an embodiment in which the Q and output signals of flip-flops 52 and 53 are alternately supplied in this order. On the other hand, in this embodiment circuit, the Q and Q output signals of the D-type flip-flop and JK flip-flop 52, 53 are alternately supplied to the three logic circuits 55, 56, 57 in this order. It is.

In the case of this embodiment circuit, the down mode is set when the up/down mode switching signal U/D is set to 1 level, and the up mode is set when it is set to 0 level. The timing chart during the counting operation is the same as that shown in FIGS. 2 and 3.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide an up-down counter that has a small number of elements and can operate at high speed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of an up-down counter according to the present invention, FIGS. 2 and 3 are timing charts for explaining the operation of the above embodiment circuit, and FIG. FIG. 5 is a circuit diagram showing the configuration of another embodiment of the invention, FIG. 5 is a circuit diagram of a conventional circuit, and FIG. 6 is a circuit diagram of a circuit invented in the course of the present invention. 51...D-type flip-flop, 52, 53,
54...JK flip flop, 55, 56, 5
7...Logic circuit.

Claims (1)

[Claims] 1. A binary counter that divides a clock signal to obtain a count output signal of the 0th bit, which is the least significant bit; n flip-flops that invert the level of the output signal to obtain count output signals of the first to nth bits; and a first bit flip-flop that obtains the count output signal of the binary counter and the first bit. first and second logic gates that are inserted between the binary counter and obtain an AND signal and an OR signal of the count output signal of the binary counter and the up/down mode switching signal, respectively; and an output of the second logic gate. It is composed of a third logic gate that inverts a signal, and a fourth logic gate that obtains an AND signal of the output signals of the first and third logic gates, and inverts the output signal of the fourth logic gate. The first bit is supplied as an input signal to the flip-flop of the first bit.
and the n flip-flops for obtaining the count output signal of the first bit to the nth bit, and each of the n flip-flops is inserted between the logic circuit of and a second to n-th logic circuit configured from a third logic gate and a fourth logic gate, and an i-th (i
The first and second logic gates in the logic circuits (=2 to n) are connected to the count output signal of the above-mentioned flip-flop which obtains the count output signal of the (i-1)th bit, and the (i-1)th logic circuit. The third logic gate in the i-th logic circuit is supplied with the output signal of the second logic gate in the i-th logic circuit. is,
An up-down counter characterized in that the output signals of the first and third logic gates in the i-th logic circuit are supplied to the fourth logic gate in the i-th logic circuit.