JPH0343717B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a selection drive circuit for each row (or each column) of a matrix panel suitable for use in an XY matrix display device, an imaging device, or the like.

[Background of the invention]

Figure 1 shows a typical matrix display device.
It is an explanatory diagram showing an example. The display device shown in the figure is
While one scanning electrode is selected by the vertical drive unit 3, a display signal applied to the terminal 5 is applied to each pixel of the display panel 1 through the horizontal switching elements 4 which are sequentially selected by the horizontal drive unit 2. This is what is called point-sequential scanning.

Display elements (pixels) include, for example, liquid crystal, EL,
Fluorescent display tubes and the like are being considered. Also, in the case of a matrix type imaging device, the display signal becomes the imaging signal,
Although the display element is replaced by an image sensor and the signal flow is reversed from each pixel to a terminal signal, the functions of the horizontal drive unit 2 and vertical drive unit 3 are the same. In the following explanation, a matrix type display device will be used as an example, but this explanation can be similarly applied to a matrix type imaging device.

FIG. 2 shows a shift register as a conventional example of a selection drive circuit in which the horizontal drive section 2 and the vertical drive section 3 are used. The operation of this circuit will be explained below using the signal waveforms of each part shown in FIG.

First, the shift clock waveform (A) is input to the terminal 15, and the scan start pulse waveform (B) is input to the terminal 13. The scan start pulse waveform (B), the output of the inverter 17 which receives it as input, and the shift clock waveform (A) are input to the half latch 10 which takes in data at the "1" level of the shift clock and holds the data at the "0" level. When input, the waveform (C) is output as output 16.
is obtained. When the output of this half latch 10 is applied together with the shift clock waveform (A) to the half latch 11 which receives data at the shift clock's "0" level and holds the data at the "1" level, the output waveform (D) is applied to the terminal 14a. can get. Hereinafter, these two types of half latches 10 and 11 will be referred to as one set. The same circuit as the full latch 12a surrounded by the one-dot chain line is connected in cascade with the full latch 12b and 12c, and the waveforms (E) and (F) are obtained as selective drive pulses delayed by one clock period at the respective output terminals 14b and 14c. It will be done.

When trying to display on a TV using a matrix type display device, it is thought that approximately 200 or more horizontal and vertical pixels are required. Therefore, the output of each drive circuit, ie, the shift register, ie, the number of full latches forming the output, is also required to be about 200 or more. If a horizontal shift clock of approximately 5 MHz, which is required for, for example, television display, is applied to a shift register with such a large number of stages, its power consumption will become extremely large. In particular, when a display element such as a liquid crystal display device that requires almost no power for display is used, the power consumption becomes enormous compared to the display element, which poses a big problem.

In addition, in active matrix display devices that use a single-crystal _Si substrate as a drive substrate, it is necessary to incorporate horizontal and vertical drive circuits on the drive substrate in order to reduce the number of external drive circuits and interconnections. . In order to manufacture this drive board with high yield and to reduce the cost, it is necessary to reduce the chip size. For example, for a square chip size of 10 to 20 mm, the output pitch of both horizontal and vertical drive circuits is required to be approximately 30 to 80 μm. However, the second
The conventional full latch shown in the figure is, for example,
The layout rules for 5μm CMOS limit the pitch to about 110μm when arranged in one row. Therefore, it is difficult to miniaturize and incorporate the drive circuit.

There are many other types of shift registers that are being considered other than those based on the RS flip-flop as shown in Figure 2, but considering the fact that light enters the register as a display device and the vertical shift register with a slow clock, static type shift registers are considered. Shift registers are more advantageous. Static type shift registers also have various component circuits, but all of them occupy approximately the same area on the chip as the one shown in FIG. 2, which is based on an RS flip-flop, which is still a problem.

[Purpose of the invention]

It is an object of the present invention to solve the above-mentioned drawbacks of the prior art, to reduce power consumption and the area occupied by the drive circuit, and to provide a selective drive circuit for each row (or each column) of a low-cost, high-yield matrix panel. Our goal is to provide the following.

[Summary of the invention]

In order to achieve this objective, the present invention focuses on the fact that the selection pulse output in the pulse shift circuit as a drive circuit is only one pulse, and when a selection pulse is sent to the next stage, an operation is performed to reset the previous stage. The present invention is characterized in that the number of constituent elements required for one stage of the drive circuit is simplified to less than half by performing the following steps.

[Embodiments of the invention]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram showing one embodiment of the present invention.

Comparing the embodiment shown in the same figure with the conventional example shown in FIG. Circuit 2 corresponding to
2 drive outputs 20a, 20 with 18a and 19a
The major difference is that b is obtained. In addition, circuits 18a and 19a corresponding to half latches are as follows:
AND compared to conventional half latches 10 and 11.
RS consists of one less gate or OR gate and two NOR gates (or NAND gates)
Another difference is that the reset R (or) of the flip-flop is connected to the output of the next stage instead of the output of the previous stage. The operation of the embodiment shown in FIG. 4 will be explained below using the signal waveform diagram of each part shown in FIG.

When the shift clock waveform (A) is input to the terminal 15 and the scan start pulse waveform (B) is input to the terminal 13, the _S1 input of the RS flip-flop consisting of two NOR gates becomes “1” in synchronization with the “1” level of the clock. 1" level, this RS flip-flop is set, output ₁ is "0", and _Q1 is "1".
In this state, when the clock waveform (A) becomes “0”, 1
At the same time as the input gate of the second stage 18a closes, the input gate (OR) of the second stage 19a opens and sends "0" of ₁ to the _{two inputs of the RS flip-flop, which is composed of two} NAND gates of the second stage 19a. sending,
This second stage RS flip-flop is set,
“1” is obtained at the output _Q2 , and “0” is obtained at the output _Q2 . At the same time, Q ₂ is connected to the R ₁ input of the first stage RS flip-flop, so the first stage RS flip-flop is reset, and the output Q ₁ becomes “0” and output Q ₁ becomes “1”.
is obtained. After this, the state of the first stage is clock (A)
When is at the "1" level, it will not change unless the terminal 13 becomes "1".

When the clock waveform (A) becomes “1” in this state,
The input gate of the second stage 19a is closed, and the input gate of the third stage 18b is closed.
The input gate (AND) opens, and the “1” of Q ₂ is changed to 3.
It is sent to the _S3 input of the RS flip-flop consisting of two NOR gates in stage 18b, and the third stage RS flip-flop is set, and the output ₃ is set to "0".
“1” is obtained for Q ₃ . At the same time, ₃ is the second stage RS
Since it is connected to _two inputs of the flip-flop, the second stage RS flip-flop is reset,
“1” is obtained at output ₂ and “0” is obtained at _Q2 . After this, the state of the second stage will not change unless the first stage output ₁ becomes "0" when the clock (A) is "0".

Thereafter, the same operation is repeated, and outputs such as Q ₃ and Q ₄ are obtained one after another. As the matrix panel drive output, it is preferable to use the n-th stage Q _o output and use the terminals 20a, 20b, and 20c shown in FIG. 4.

In the operation of the conventional example shown in FIG. 2, the matrix panel selection drive output is obtained at the cycle of the shift clock, but in the embodiment of the present invention shown in FIG. 4, a shift clock with a duty ratio of approximately 50% is used. Therefore, the same output can be obtained in approximately half a cycle of the shift clock. Therefore, since the frequency of the shift clock can be halved, power consumption can be reduced. Furthermore, since the fan-in of the shift clock terminal for each drive stage is reduced to 1/4 compared to the conventional example, the clock driver can be made smaller and the power consumption can be reduced.

FIG. 4A is a circuit diagram completely equivalent to FIG. 4. In FIG. 4, in odd-numbered stages such as the first stage 18a and the third stage 18b, an RS flip-flop consisting of two NOR circuits and one AND gate are used.
The remaining even stages consist of two NAND circuits.
An RS flip-flop and one OR gate are used.

Therefore, regardless of whether the number is odd or even, every stage has 2
An RS flip-flop consisting of NOR circuits and one
If an attempt is made to realize a circuit equivalent to that shown in FIG. 4 by using two AND gates, as shown in FIG. It is preferable to invert and supply it.

Figure 4 and Figure 4A are completely equivalent circuits, but Figure 4A requires one extra element (inverter) in even-numbered stages, which increases the number of elements required, making it easier to integrate into an IC. Since this is disadvantageous, the circuit shown in FIG. 4 is practically adopted.

Next, in the embodiment shown in FIG. 4, since the RS flip-flop is reset by the output of the next stage, it does not show how to reset the final stage. An example of how to reset this final stage is shown in the sixth section.
As shown in Fig. and Fig. 7. In both cases, the output of the inverter 21 which receives the cycloclock as an input is used as the final stage reset input. The difference between Figure 6 and Figure 7 is
There is no essential difference in that the former has a NOR configuration and the latter has an RS flip-flop in a NAND configuration as the final stage. This operation will be explained below.

In the case of FIG. 6, when the system clock applied to the terminal 15 is at the "1" level, when "1" is applied to the terminal 13 from the previous stage, the RS flip-flop consisting of two NOR gates is set, and the terminal 20 is set.
A matrix selection drive signal "1" is output to y. After that, when the shift clock becomes "0", the input AND gate of the final stage 18y closes, and the reset signal "1" is input to _Ry by the inverter 21 which receives the shift clock, and the RS flip-flop of the final stage 18y is reset. ,
Matrix non-selection drive output “0” is at terminal 20y
is output from. In this way, it serves as the termination of the final stage. Also, in the case of Figure 7,
The operation is almost the same as in the case of Fig. 6.

If you look closely at the waveforms in Figure 5, you can see that the waveforms Q ₁ and Q ₂ , Q ₂ and Q ₃ , and Q ₃ are used as matrix drive outputs.
There is a slight partial overlap between Q4 and _Q4 . The reason for this overlap is that, as can be seen from the above explanation of the operation, the nth stage RS flip-flop is reset from the set state after the (n+1)th stage RS flip-flop is set. n stages and (n
This is because the +1) stages enter the set state at the same time.
This time is extremely short, so it does not pose much of a problem, but if it becomes a problem, it can be solved by using the matrix drive output at every other stage, that is, 20a, 20c, etc., in the embodiment shown in Fig. 4. . In this case, the matrix drive output is
Compared to the case where 20a, 20b, 20c, 20d, etc. are used, both the drive circuit and the clock frequency are doubled. However, compared to the conventional example shown in FIG. 2, the number of gates per stage is reduced by two, and the fan-in for the shift clock is also halved, resulting in a simpler configuration and lower power consumption. Furthermore, by changing the duty of the shift clock, there is an advantage that the separation time (total matrix non-selection time) between the n-th and (n+1)-th stage matrix selection drive output pulses can be adjusted.

When outputs from all stages are used as matrix drive outputs, a specific example of reducing the above-mentioned overlap of drive output pulses is shown in FIG. This is an embodiment of the present invention shown in FIG. 4 in which an output inverter with a low threshold value Vth is added to each stage. The embodiment shown in FIG. 8 will be described below with reference to FIG. 9, which shows the output change portion of the operation waveform of each part in a larger scale than in FIG. 5.

Parts described in Figure 4, 18a, 18b, 19a, 1
Regarding the operation 9b, the embodiment shown in FIG. 8 and the embodiment shown in FIG. 4 perform the same operation. In the waveform diagram of FIG. 9, the threshold value Vth of each gate in the portion corresponding to the description in FIG. 4 in FIG. 8 is set high as Vth ₁ shown in the waveform (A), ,22
The threshold value Vth of b, 22c, 22d is waveform ( ₁ )
It is set low as Vth ₂ shown in . By doing this, the outputs 23a, 23b, 23c of the inverters 22a, 22b, 22c which take inputs ₁ , ₂ , ₃ , respectively, have waveforms (G), (H), and (I), as shown in (G), (H), and (I). ₁ ), ( ₂ ), and ( ₃ ), the pulse width is narrower and the overlap of output pulses is reduced. In this way the output inverter threshold
By manipulating Vth, the overlap of output pulses can be easily reduced.

〔Effect of the invention〕

As described above, according to the present invention, the scale and occupied area of the drive circuit can be halved compared to the conventional example, so that the yield can be improved and the cost can be reduced. Furthermore, since the capacity of the shift clock supply buffer is reduced to 1/4 and the frequency is also halved, the power consumption of the drive section is reduced to nearly 1/8 compared to the conventional example.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram showing an example of a general matrix type display device, Fig. 2 is a circuit diagram showing a conventional selection drive circuit of a matrix panel, and Fig. 3 is a signal waveform diagram of each part of the circuit shown in Fig. 2. , Fig. 4 is a circuit diagram showing one embodiment of the present invention, Fig. 4A is a circuit diagram showing another embodiment equivalent to Fig. 4, and Fig. 5 is a signal waveform diagram of each part of the circuit shown in Fig. 4. , FIGS. 6 and 7 are circuit diagrams showing specific examples of how to apply the final stage reset in the embodiment shown in FIG. 4, and FIG. 8 is a circuit diagram showing another embodiment of the present invention. FIG. 9 is a diagram of signal waveforms at various parts in the circuit of FIG. 8. Description of symbols: 1...Display panel, 2...Horizontal drive section, 3...Vertical drive section, 4...Horizontal switch element, 12a, 112b, 12c...Full latch,
18a, 18b...RS flip-flop that accepts set input when the clock is "1", 19a,
19b...RS flip-flop that accepts set input when clock is "0", 21, 22a, 22
b, 22c, 22d...inverter.

Claims (1)

[Scope of Claims] 1 In each stage composed of an RS flip-flop and an AND gate, the S of the flip-flop is
The logical AND output of the previous stage output and the clock signal is input to the (set) terminal, which is generated by the AND gate, and the next stage output is input to the R (reset) terminal of the flip-flop. . A selection drive circuit for each row (or each column) of a matrix panel, characterized in that the clock signals are mutually inverted and supplied. 2. The selection drive circuit according to claim 1, wherein an inverted output of a clock signal is input to the R (reset) or (reset bar) terminal of the final stage RS flip-flop. 3. In the selection drive circuit according to claim 1, the output of each RS flip-flop is input to an inverter having a lower threshold than other gates, and the output of this inverter is used as the selection drive output. A selection drive circuit featuring: 4. Each alternate stage (first type of stage) is an RS flip-flop consisting of two NOR gates.
The remaining stages (the second type of stages) are composed of an RS flip-flop consisting of two NAND gates and an OR circuit.
In this type of stage, the AND output of the previous stage output and the clock signal is created using an AND gate and input to the S (set) terminal of the RS flip-flop, and the output of the next stage is input to the R (reset) terminal of the RS flip-flop. In the second type of stage, the inverted output of the previous stage output and the OR output of the clock signal are connected to the (set bar) terminal of the RS flip-flop.
A selection drive circuit characterized in that an OR gate is created and input, and an inverted output of the next stage output is input to a (reset bar) terminal of an RS flip-flop. 5. The selection drive circuit according to claim 4, wherein an inverted output of a clock signal is input to the R (reset) or (reset bar) terminal of the final stage RS flip-flop. 6. In the selection drive circuit according to claim 4, the output of each RS flip-flop is input to an inverter having a lower threshold than other gates, and the output of this inverter is used as the selection drive output. A selection drive circuit featuring: