JPH0345419B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplier, and more particularly to a parallel multiplier with extended functionality.

Multipliers currently in use include serial, parallel, and ROM types, but in the field of digital signal processing in computers, communications, etc., high speed is required, so parallel multipliers are used. Often used.

Since the number of bits of the multiplier and multiplicand in a parallel multiplier is fixed, it is important to easily obtain a large scale multiplier with a long number of bits using existing multipliers. There is a need for a multiplier with scalability to accommodate this.

Let's now consider a method of constructing an N×N (N>n) bit multiplier using a multiplier with an n-bit multiplier and an n-bit multiplicand (here, for explanation purposes, N/n=r, r: be an integer). In a multiplier that only has a multiplication function, each partial product is determined as an N-bit multiplier and multiplicand. At this time n
×n-bit multipliers use r ² pieces. Since the product of N×N bits is the sum of these partial products, an adder for that purpose was required.

In multipliers with built-in expansion functions, it is possible to create a multiplier with an expanded number of bits, in principle, without providing an adder. The built-in extension function means the built-in function to add partial products, and it has an extension input. There are several known methods for this, but here we will take up a multiplier having a multiplicand X, a multiplier Y, and an extended input M. The output P is expressed as P=X・Y+M (1) (X, Y are n bits, M is 2n bits).

FIG. 1 shows an embodiment of a 16 x 16 bit multiplier made using an 8 x 8 bit multiplier having the above function.

Here, each of 1 to 4 is an 8.times.8 bit multiplier, and each multiplier has a configuration as shown in FIG. The output P _32-1 is the multiplicand X _16-1 , the multiplier X _16-1 ,
For the extended input M _32-1 , we obtain P _32-1 = X _16-1・Y _16-1 + M _32-1 (2). That is, by using a multiplier having the configuration of equation (1), it is easy to obtain a multiplier with a long number of bits.

By the way, parallel multipliers are widely used as multiplication circuits in various operations, but the configuration of equation (1) is often insufficient. For example, in fast Fourier transform in the field of digital signal processing, a solution is found by the sum and difference of two products. When performing such an operation, if the multiplier has a subtraction function, there is no need to provide an external subtracter. Therefore, many recent multipliers have a built-in subtraction function in addition to addition for extended inputs, and for equation (1), P=X・Y±M (3) (X, Y is realized using n bits and M is 2n bits). The configuration at that time will be as shown in Figure 3, with addition and subtraction control terminals (ADD/SUB) added. ADD here/
If SUB is "0", Mi and Mj are directly added, and when SUB is "1", Mi and Mj are inverted and added.Now, as mentioned above, by constructing equation (3), n
It will be explained below that when an N×N (N2n) bit multiplier is created using a ×n bit multiplier, the extended input cannot be subtracted.

First, in FIG. 1, the 8.times.8 bit multipliers 1 to 4 have addition and subtraction functions as shown in equation (3), that is, the multipliers have the configuration shown in FIG. In FIG. 1, a is the output of the lower 4 bits of multiplier 2, which is added to the upper 4 bits of the expansion input of multiplier 1 (corresponding to Mj in FIG. 3). Similarly, the upper 4 bits output b of multiplier 1 are sent to the lower 4 bits of multiplier 3 (corresponding to Mi in Fig. 3), and the upper 4 bits output C of multiplier 2 are sent to the upper 4 bits of multiplier 3. The upper four bits output d of the multiplier 3 are added to the lower four bits of the multiplier 4, respectively. Product here
In either addition or subtraction of the extended input M _32-1 to X _16-1 and Y _16-1 , a to d must always be added to the partial product of the next stage multiplier. The problem with the circuit in Figure 1 is that when the ADD/SUB terminal is set to subtract the expansion input M _32-1 ,
~d is also subtracted. Therefore, using a multiplier with addition and subtraction functions for expansion inputs as shown in Figure 3, equation (3) can only be realized when used alone; subtraction is not possible during expansion. . In this way, we can subtract the product of a long number of bits (in this case
The only way to find M _32-1 ) is to add -M _32-1 ; if the data is in two's complement format, each bit of the binary number representing the original number is inverted, and the It was necessary to provide an external circuit with the function of adding "1" to the lower bit (M ₁ ).

An object of the present invention is to provide a multiplier that is capable of adding and subtracting extended inputs even when extended, in a conventional multiplier having the functions of adding and subtracting extended inputs.

In order to achieve the above object, the multiplier according to the present invention divides the extension input into two into the lower bits, and also provides a new control terminal for the extension input in addition to the addition and subtraction control terminals ADD/SUB. and the ADD/SUB terminal are used to independently add and subtract the two divided expansion inputs.

Embodiments will be described in detail below with reference to the drawings.

FIG. 4 is a block diagram showing an embodiment of the multiplier according to the present invention, in which the multiplicand Xi, the multiplier Yi, the extended input Mi,
In addition to Mj, addition and subtraction control terminals ADD/SUB,
An expansion input control terminal Kc is provided.

To make it possible to subtract the expansion inputs during expansion, basically you need to create a logic that adds the expansion inputs Mi and Mj independently, either as they are or inverted, using the two inputs ADD/SUB and Kc. good.

Here, when using a single unit, apply “0” to Kc, add when ADD/SBU = “0”, that is, Mi,
Directly input Mj, subtract when ADD/SUB="1",
In other words, if we use a multiplier configured to invert Mi and Mj and input them, Mi and Mj will be ADD/SUB during expansion.
According to the values of and Kc, directly as shown in Figure 5,
Or it is inverted and added to the products Xi and Yi. Its specific configuration is shown in FIG. In Fig. 6, 11 to 13 are Exclusive-OR gates, 14 is Xi,
Yi multiplication circuit, 15 is addition circuit, Pi, Pj
represents the output.

Let's apply the multiplier in Figure 4 with the logic in Figure 5 to Figure 1. Since a to d are always additions as mentioned above, "0" is applied to both ADD/SUB and Kc in multiplier 3. do. Also, apply “0” to Kc of multiplier 2,
Apply “0” to ADD/SUB of multiplier 4, ADD/SUB of multiplier 1, Kc, ADD/SUB of multiplier 2
Connect SUB and Kc of multiplier 4 in common. and product
If “0” is applied to the commonly connected terminals for X _16-1 and Y _16-1 , the expansion input M _32-1 will be added,
If "1" is applied, it will be subtracted. Also, when further spreading the number of bits, ADD/
The conditions for SUB and Kc are the same.

In addition, in the above explanation, the example was an expansion using a multiplier with the logic shown in Figure 5, but ADD/SUB, Kc
If the logic is such that the expansion inputs Mi and Mj can be controlled independently with the two inputs of Good.

If the multiplier according to the present invention is used in this way,
Subtraction of the expansion input during expansion can be easily achieved using only a multiplier, and the effect is significant.

[Brief explanation of drawings]

Fig. 1 is an example of a conventional parallel multiplier with extended function and an extended function parallel multiplier according to the present invention, Fig. 2 is a block diagram of a conventional parallel multiplier, and Fig. 3 is a conventional extended function. 4 is a block diagram of a parallel multiplier with extended function according to the present invention, FIG. 5 is a diagram showing the logic of the extended input in FIG. 4, and FIG. 6 is a diagram showing the logic of FIG. 5. FIG. 4 is a circuit schematic diagram of a multiplier having the configuration shown in FIG. 4 based on FIG. Explanation of symbols, 1, 2, 3, 4...Parallel multiplier with extended functions, a, b, c, d...Partial product, X _8-1 ,
X _16-9 , Xi... Multiplicand, Y _8-1 , Y _16-9 , Yi... Multiplier, P _8-1 , P _16-9 , P _24-17 , P _32-25 , Pi, Pj... Multiplier output, ADD/SUB...addition, subtraction control terminal, Kc...extension input control terminal, _M8-1 , _M16-9 ,
M _24-17 , M _32-25 , Mi, Mj...extended input, Mi,
Mj...Inverted extended input, 11, 12, 13
...exclusive-OR gate, 14...multiplication circuit,
15...Addition circuit.

Claims (1)

[Claims] 1. In a parallel multiplier that adds or subtracts an extension input to the product of a multiplier and a multiplicand using addition and subtraction control terminals, the extension input is divided into two into upper bits and lower bits, and a newly provided extension input is used. A parallel multiplier having a function of independently adding and subtracting the expanded input divided into two using a control terminal and the addition and subtraction control terminals.