JPH0346982B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Prior Art] Conventionally, memory ICs such as dynamic random access memories have had the configuration shown in FIG. In the figure, 1 is p-type Si
It is a substrate with n-type layers 2, 3, 4, 5 and 6, 8
With the charge storage capacitor consisting of the transfer gate 2, 3, 11 and the charge storage gate 10, 11,
6 and 10 constitute one bit, and 4, 5, 8, and 11 constitute a so-called one-transistor type dynamic memory cell. 7 and 9 are used as data lines, and 12 and 13 are used as word lines.

[Problems to be Solved by the Invention] When a memory IC and an LSI are configured with this configuration and sealed in a package, the most problematic point is that α-ray particles generated from impurities in the package material The surface of the LSI chip is irradiated, and the memory
The information stored in the cell is reversed to create a random
to cause an error (T.C., May
and MHWoods; “A New Physicol
Mechanism for Soft Errors in Dynamic
Memories “Relability Physics Symposium.
'78. Appril). Depending on their energy, these α-ray particles reach a depth of about 20 to 100 μm from the Si surface, forming electron-hole pairs with a certain spread and almost uniformly in the depth direction. Holes are attracted to the substrate, but electrons, for example, are attracted by the storage capacitance of a memory cell that is "1" (state with no electrons), and the memory cell becomes "0" (state with electrons). It reverses the state. The above-mentioned inversion of the information in the memory cell is related to the amount of charge stored in the storage capacitor of the memory cell and the amount of electrons created by the irradiation of α-ray particles collected in the storage capacitor. If the amount of electrons is less than the amount of accumulated charge,
No inversion of the information stored in the memory cells occurs.

SUMMARY OF THE INVENTION An object of the present invention is to overcome the drawbacks of the above-mentioned conventional examples and provide a highly reliable semiconductor device.

〔Example〕

FIG. 2 shows a first embodiment of the invention. In the figure, 30 is an n-type Si substrate, 20
is a p-type well. According to the present invention, the thickness of the p-type well 20 is as thin as 4 to 5 μm at most, and α
Even when irradiated with line particles, the number of electron-hole pairs created within the well is much smaller than in the conventional example. According to calculations using a simple model,
In the case of the structure according to the present invention, the number of electrons collected in the storage capacitor was significantly reduced to less than 1/10 of that of the conventional structure. Therefore, random inversion of memory information, which has been a problem in the past, does not occur in this structure, and a highly reliable semiconductor device can be provided.

Although only the memory cell section has been described above, it is desirable to form the peripheral circuit section and the memory cell section in separate p-type wells. This is because the peripheral circuit section operates as the input section or output section of the semiconductor memory device that processes large signal amplitudes, so in order to reduce noise to the memory cell section where the signal amplitude is small, the peripheral circuit section and memory・The cell portion should be formed in separate p-type wells.

Furthermore, even if the peripheral circuit section and the memory cell section are formed in separate p-type wells, if the thickness of the plurality of p-type wells is the same, they can be formed in the same process.
Needless to say, there is no increase in the manufacturing process.

Normally, the voltage 20 is fixed to the _ground potential V _SS or a voltage lower than that, and the voltage 30 is fixed to a voltage at the power supply voltage V _DD level, which is a voltage higher than or equal to the ground potential V _SS .
On the other hand, in order to retain the information stored in the memory cell for a longer time, fix 30 to the same voltage as the storage voltage of the memory cell, for example, V _DD - V _th (V _th : threshold voltage of a MOS transistor). Then 20 and 4
This is highly effective as the leakage current between the two is reduced.

Also, 20 becomes 20 when V _SS is fixed at around +0.5V.
This has the great effect of reducing leakage current by completely accumulating the Si surface where is formed.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional memory IC, Figure 2 is a sectional view of a conventional memory IC.
The figure is a sectional view showing a memory IC according to an embodiment of the present invention. 2, 3, 4, 5...n ⁺ type diffusion layer, 20...p
type diffusion layer well, 30...n type Si substrate.

Claims (1)

[Scope of Claims] 1. A semiconductor memory device in which a plurality of memory cells and peripheral circuits are provided in a surface region of a semiconductor substrate, wherein a plurality of p-type well regions are provided in the surface region of the semiconductor substrate, The plurality of memories are arranged in one well of the plurality of p-type well regions.
The peripheral circuit is provided in the other well of the plurality of p-type well regions, and the thickness of the one p-type well region provided with the plurality of memory cells is 5 μm or less. A semiconductor memory device characterized by: 2. A patent claim characterized in that the thickness of one of the p-type well regions in which the plurality of memory cells are provided is set to be 5 μm or less to reduce information inversion in the memory cells caused by α-ray particles. The semiconductor memory device according to scope 1. 3. The plurality of memory cells are dynamic memory cells using a charge storage capacitor configured between a substrate surface region and a charge storage gate. The semiconductor memory device described in . 4. The semiconductor memory device according to claim 3, wherein the dynamic memory cell is a one-transistor type dynamic memory cell.