JPH0347035B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a household magnetic recording/playback device (VTR).
The present invention relates to a burst gate pulse generation circuit suitable for integration in devices such as devices.

[Conventional technology]

In a VTR, when recording and reproducing a color television signal, operations such as extracting and reinserting a burst signal are necessary, and it is necessary to obtain a burst gate pulse for this purpose.

Conventionally, such a burst gate pulse generation circuit has been known to obtain a horizontal synchronizing pulse by delaying it with a delay circuit including an LCR element or the like. For example, the first
As shown in the figure, a horizontal synchronizing pulse is supplied to the input 11 of a low-pass filter 1 consisting of a resistor R, an inductance coil L, and a capacitor C, and the low-pass filter 1 performs delay shaping to obtain a predetermined delay time and a predetermined pulse width. Output burst gate pulse 1
I'm starting to get 2.

[Problem to be solved by the invention]

However, such a circuit requires elements such as a capacitor C with a relatively large capacity and a coil L with a large inductance, so even if you try to integrate the circuit, it is difficult to integrate such elements L and C. Therefore, these elements had to be installed as circuits external to the IC, which increased the number of external elements and increased costs.

In addition, the delay time and threshold level are susceptible to changes due to variations in the characteristics of the R, L, and C elements and temperature dependence, and as a result, the pulse position and pulse width of the obtained gate pulse fluctuate, resulting in color burst signals. During sampling, some parts of the video signal may be missing, or part of the video signal may be mistakenly picked up, making it impossible to obtain correct phase information, causing distortions such as uneven hue.

Furthermore, the time relationship between the horizontal synchronizing pulse and the burst signal may be different during VTR recording and playback, and in such cases the position of the gate pulse must be changed. A circuit consisting of R, L, and C elements has the disadvantage that accurate switching is difficult and the structure is complicated.

The purpose of the present invention is to eliminate the drawbacks of the prior art described above, obtain a gate pulse with stable characteristics and accuracy, and
It is an object of the present invention to provide a burst gate pulse generation circuit that can be easily integrated into an IC and can also easily switch pulse positions.

[Means to solve the problem]

In order to achieve this object, the present invention is characterized in that a gate pulse is obtained from a horizontal synchronizing signal by a digital method.

[Effect]

In home VTRs, etc., a so-called color signal low-frequency conversion method is adopted, which converts the color signal to a low frequency range and records it, and for high-density recording, the phase of the low-frequency converted color signal is converted into one horizontal line. Scanning period (1H)
It is designed to record with a 90° phase shift.
Therefore, the color signal is low-pass converted to a frequency band of 630KHz, which is 40 times the horizontal scanning frequency _fH , and the phase is shifted by 90 degrees every 1H, so
There is a method in which a 2.52 MHz reference oscillator is provided, and its output is divided by 1/4 to create four signals each with a 90° phase difference, which are switched and used every 1H. Therefore, in the present invention, good results can be obtained by using the output of this 2.52 MHz reference oscillator.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Figure 2 shows an example in which the present invention is applied to a VTR having a 2.52MHz reference oscillator as described above.
2 is a phase detection circuit, 3 is a 2.52MHz voltage controlled oscillator (VCO), 4 is a 1/4 frequency divider, 5 is a 1/40 frequency divider,
6 is a horizontal synchronization gate for extracting only the horizontal synchronization signal from the composite synchronization signal; 7 is a comparison wave generation section; 8 is a phase selection circuit; 13 is a clock pulse setting section;
4 is a synchronous 1/4 frequency divider circuit serving as the first frequency divider;
15 is a synchronous 1/6 frequency dividing circuit serving as second frequency dividing means, and 16 is a reset pulse setting section. In addition,
9 is a control voltage terminal for controlling VCO3 as necessary, 10 is a terminal to which a composite sync signal separated from the television signal is supplied, 11 is a horizontal sync pulse input, and 12 is a burst gate pulse output. .

When the signal 3a of 2.52MHz appears from VCO3, the output of the 1/4 frequency divider 4 is 630KHz, that is, the signal 4 of 40f _H.
a is obtained, which is divided by a period of 1/40 and becomes a signal of f _H , which is supplied to the horizontal synchronization gate 6. The vertical synchronization signal and equalization pulse are removed from the composite synchronization signal from the terminal 10, and the horizontal Only the synchronization pulse is extracted and supplied to the phase detection circuit 2.

Furthermore, the f _H signal from the frequency divider 5 is transmitted to the comparison wave generator 7.
The waveform-shaped signal 7a is supplied to the phase detection circuit 2, where the phase is compared with the horizontal synchronizing pulse. Then, the phase is compared and a control voltage corresponding to the difference is given from the phase detection circuit 2 to the VCO 3, so in the end, the 2.52MHz signal 3 from the VCO 3
A is a signal whose phase is synchronized with the horizontal synchronizing pulse of the synchronizing signal supplied to the terminal 10. this
The signal of VOC3 becomes a signal 4a whose frequency is divided by 1/4, which is output from the phase selection circuit 8 as a 40f _H signal, which is used in the color signal low frequency conversion method.

Therefore, the burst gate pulse generating circuit according to the present invention utilizes the signal 3a from the VOC 3 as a clock pulse and supplies it to the clock pulse setting section 13 together with the horizontal synchronizing pulse from the input 11. The clock pulse from the setting section 13 is supplied to a 1/4 frequency dividing circuit 14, which is a first frequency dividing means, and sets the delay time of the burst gate pulse from the horizontal synchronizing pulse. The output is then supplied as a clock pulse to the 1/6 frequency divider circuit 15, which is the second frequency dividing means, to set the pulse width of the burst gate pulse and also to the reset pulse setting section 16.
The series of operations that begin at the rising edge of the horizontal synchronizing pulse are completed before the rising edge of the next synchronizing pulse.

Next, details of one embodiment of the burst gate pulse generation circuit according to the present invention will be explained with reference to FIG.

In FIG. 3, 17 and 18 are NAND gates forming an R to S flip-flop, 19 is a NAND gate for gating the clock pulse 3a, 20 and 23 are inverters, and 21 is, for example, five inverters connected in series. delay circuit, 2
2 is a NAND gate.

Further, F1 and F2 constitute the first frequency dividing circuit 14, and F3 and F2 are D-type flip-flops to which the same clock for performing 1/4 frequency division is input.
4 and F5 constitute the second frequency dividing circuit 15, and are D-type flip-flops to which the same clock for performing 1/6 frequency division is input. Therefore, the first frequency dividing circuit 14 (F1, F2) and the second frequency dividing circuit 15 (F3, F4, and F5) each operate with the same clock, and are synchronous type frequency dividing circuits.

Note that 24 is a terminal connected to the output of the second VCO 3 and supplied with the clock pulse 3a.

Next, the operation shown in FIG. 3 will be explained using the waveform diagram shown in FIG. 4.

NAND gates 17 and 18 form an R to S flip-flop whose trigger input is a negative pulse;
It is set by a horizontal synchronizing pulse of opposite polarity from terminal 11 and reset by a reset pulse of opposite polarity from NAND gate 22, and the clock pulse 3a is turned into a flip-flop (hereinafter simply referred to as FF) by a NAND gate formed by NAND gate 19 and inverter 20. ) given to F1 and F2. Therefore, when the horizontal synchronizing pulse shown by waveform i in Fig. 4 rises at time _t0 , the clock pulse of waveform a becomes FFF.
1 and F2, a pulse of waveform b appears at the Q output of FFF1, which is then supplied to FFF2.
Since it is supplied to the D input of , pulses of waveforms c and d are obtained at its output Q. At this time,
The second rising part of the waveform d of the output of FFF2 is 8 seconds after the clock pulse a is applied at time _t0 .
It rises at the rising edge of the second pulse, and since the period of clock pulse a is 0.4 μs, time t ₀ ,
In other words, 2.8μs from the rise time of the horizontal synchronization pulse
Occurs after a delay. Therefore, the output of FFF2 is applied as a rising signal of the burst gate pulse to the second frequency dividing circuit 15, and also to the D input of FFF1, so that the operations of FFF1 and F2 are performed with a difference of one clock. Since this first frequency divider circuit is a synchronous frequency divider, the output delay with respect to the clock can be minimized by a single flip-flop stage as a frequency divider circuit.

The signal of waveform d of the output of FFF2 is the first
The Q outputs of the second FF, F3 and F4 are connected to the D input of the next FF, and the output of the third FF, F5 is connected to the D input of the first FF, F3.
Three FFs connected to the input, i.e. F3
~ Since it is supplied to the clock input CL of F5,
The Q outputs of FFF3 to F5 have waveforms e, f, and
It becomes like g. Now, if we focus on the Q output of FFF4, it is clear from the waveform f that it rises when 8 clock pulses a are applied from time _t0 , and then when 13 clock pulses a are applied. When it comes down to the ground. Therefore this
The signal of waveform f which is the Q output of FFF4 is at time t ₀ ,
In other words, from the time when horizontal synchronization pulse i occurs
It can be seen that the pulse has a delay of 2.8 μs and a width of 4.8 μs, making it the ideal pulse for gating a burst signal. So this FFF
If the Q output of 4 is taken out as output 12, a burst gate pulse will be obtained. Since this second frequency divider circuit is also a synchronous frequency divider, the output delay with respect to the clock input is only one stage of a flip-flop, like the first frequency divider circuit. In this way, the output can be obtained with only a delay of two flip-flop stages in total, making it possible to reduce the influence of the flip-flop delay time.

By the way, if left as is, signals of waveform f will appear one after another during the 1H period until the next horizontal synchronization pulse is given, so the output of FFF5 should be
The signal is applied to one input of the NAND gate 22, and is also supplied to the other input of the gate 22 via a delay circuit 21 consisting of an odd number of inverters. This results in
A reset pulse in the negative direction with a pulse width corresponding to the delay time of the delay circuit 21 is obtained from the rising part of the output of FFF5, that is, the falling part of the waveform g which is the Q output, and is therefore output from the NAND gate 22. All FFF1 to F are inverted by the inverter 23 as a reset pulse shown in waveform h.
In addition to reset input R of 5, reset all these FFs and form R-SFF.
Supply to the input of NAND gate 18, that is, the reset input of this FF, and reset this FF.
Consists of 19 NAND gates and 20 inverters
Close the AND gate to stop supplying clock pulses.

As a result, when a horizontal synchronization pulse appears at input 11, only one pulse with a pulse width of 4.8μs appears at output 12 with a delay of 2.8μs, and after 1H has passed, the horizontal synchronization pulse is input again. 1
No output appears at output 12 until it appears at output 1.

As described above, according to this embodiment, the burst gate pulse is obtained digitally by dividing the clock pulse from the VCO 3, which is synchronized by the horizontal synchronizing pulse, using a synchronous frequency divider. Therefore, the delay time and pulse width of the gate pulse obtained at the output from the horizontal synchronizing pulse are precisely specified by the clock pulse, and are always accurate without being affected by variations in circuit elements or temperature changes. Burst gate pulses can be obtained.

FIG. 5 shows another embodiment of the invention. This fifth
The difference between the embodiment shown in the figure and the embodiment shown in FIG.
The reset side output of the R-SFF consisting of NAND gates 17 and 18 is supplied together with the reset pulse from the inverter 23 to the reset inputs of all FFF1 to F5, and after the signal f appears at the Q output of FFF4, the reset pulse is output. h is inverter 23
appears at the output of FFF1 to F5, and at the same time, the R-SFF consisting of NAND gates 17 and 18 is reset.
Following the reset pulse h from the inverter 23, the output on the reset side of
The clock pulse 3a is applied to the reset input of FFF1 and FFF5, and until the horizontal synchronizing pulse is supplied to the input 11 again after 1H has elapsed, the clock pulse 3a is not operated even if it is supplied to FFF1 and F2. The other operations are the same as the embodiment shown in FIG. 3, and accurate burst gate pulses can be obtained at the output 12.

FIG. 6 shows yet another embodiment of the invention. The embodiment shown in FIG. 6 differs from the embodiment shown in FIG. 3 in that a switching circuit 25 is provided so that the delay time of the burst gate pulse can be switched and selected.

In a VTR, the luminance signal and color signal are generally separated and processed separately, so the delay time of the burst signal from the horizontal synchronization pulse differs during recording and playback.

Therefore, it is desirable to be able to switch the delay time of the burst gate pulse between recording and reproduction.

Therefore, in the embodiment shown in FIG. 6, the NAND gate 30,
A switching circuit 25 consisting of 31 and 32 is provided, and the clock pulse to the 1/6 frequency divider circuit 15, which is the second frequency dividing means, is transferred to the 1/4 frequency divider circuit 1, which is the first frequency dividing means.
It is possible to select either the Q output or the output of FFF2 that constitutes FFF4. When recording
A voltage is supplied to one input of the NAND gate 31 to take out the output of FFF2 as a clock pulse, and during reproduction, a voltage is applied to one input of the NAND gate 30 to take out the Q output of FFF2 as a clock pulse. As a result, as is clear from the waveform diagram in FIG. 4, the clock inputs of FFF3 to F5 are switched to either waveform c or d, and when switched to waveform c, the Q
The output rises quickly, and the delay time of the burst gate pulse can be optimally and accurately changed in response to switching between recording and playback on the VTR.

In each of the above embodiments of the present invention, the clock pulse is obtained from a 2.52MHz VCO for color signal low frequency conversion, but the clock pulse for color subcarrier is
The output of the 3.58 MHz VCO may be used; in this case, the frequency division ratio of the first frequency dividing means 15 may be set to 1/6, and the width of the resulting burst gate pulse will be approximately 5 μs. However, this also makes it possible to obtain a burst gate pulse generation circuit that is sufficiently practical and can be applied to many VTRs with great effects.

Further, in the above embodiment, a D type FF was used as the FF, but it is obvious to those skilled in the art that the FF is not limited to this. For example, a J-K type FF is used. The same effect can be obtained even if it is tilted.

〔Effect of the invention〕

As explained above, according to the present invention, the burst gate pulse is digitally generated by counting the clock pulse from the reference oscillator whose phase is synchronized with the horizontal synchronizing pulse using a synchronous frequency divider. It is possible to obtain accurate gate pulses at all times without being affected by variations in the characteristics of the elements used or changes in conditions during use.
In addition, since it is not necessary to use elements such as LC elements that are extremely difficult to integrate into an IC, the number of external parts required for integration into an IC can be reduced, reducing factors that increase costs and reducing costs. This provides advantages such as the ease of accurately switching the generation conditions.

In addition, many home-use VTRs use a color signal low-frequency conversion method, so clock pulses can be obtained from a VCO for that purpose, and the configuration can be shared, making it possible to further reduce costs. Become.

[Brief explanation of drawings]

Fig. 1 is a wiring diagram of a conventional circuit for obtaining a burst gate pulse from a horizontal synchronizing pulse, Fig. 2 is a block diagram of a portion including a burst gate pulse generation circuit of a VTR to which the present invention is applied, and Fig. 3 is a circuit diagram of a portion of a VTR to which the present invention is applied. A wiring diagram of a burst gate pulse generation circuit according to one embodiment, FIG. 4 is a waveform diagram for explaining its operation, and FIGS. 5 and 6 show burst gate pulses according to other embodiments of the present invention, respectively. It is a wiring diagram of a generation circuit. 3...Voltage controlled oscillator (VCO), 13...Clock pulse setting section, 14...1/4 serving as first frequency dividing means
Frequency divider circuit, 15... 1/6 frequency divider circuit as second frequency dividing means, 16... Reset pulse setting section.

Claims (1)

[Claims] 1. In a burst gate pulse generation circuit for obtaining a burst gate pulse having a predetermined delay time and a predetermined pulse width from a horizontal synchronizing signal; An oscillation means that oscillates at an oscillation frequency of a larger integer (fH is the horizontal repetition frequency), an oscillation output signal of the oscillation means and a horizontal synchronization signal are input, a phase comparison between the oscillation output signal and the horizontal synchronization signal is performed, and the above oscillation is performed. a pulse generating circuit comprising: a phase detection means for supplying a phase control signal to the means; and a pulse generation circuit that divides the output of the oscillation means by 1/N to generate a pulse at a subcarrier frequency of a low-pass conversion color signal; A frequency dividing means which inputs the output of the oscillation means which oscillates at the frequency of N×40fH of the generating circuit; By starting supplying a clock to the frequency dividing means in synchronization with the horizontal synchronization signal, the frequency of the frequency dividing means is divided. The frequency dividing operation of the frequency dividing means is stopped by starting the operation, stopping the supply of clock to the frequency dividing means after a predetermined time, and resetting the frequency dividing means using the output of the frequency dividing means. A burst gate pulse generation circuit includes a frequency division control means for controlling the frequency.