JPH0347525B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a DC voltage generation circuit, and is particularly used as a reference voltage for an encoder/decoder (hereinafter abbreviated as CODEC), etc., and generates a DC voltage with a small error from a standard value. Regarding the circuit in which it occurs.

(Prior art) A CODEC converts an input audio signal into a PCM signal,
Conversely, it is a device that converts an input PCM signal into an audio signal, and is manufactured as a monolithic integrated circuit.

Conventionally, some integrated circuit CODECs do not have a built-in reference voltage generation circuit, but have a configuration shown in the block diagram of FIG. 1, in which the reference voltage is supplied from an external terminal. In the CODEC shown in the figure, the analog signal is band-limited to prevent aliasing distortion, and then applied to the analog input terminal 1, converted to a PCM signal by the encoder 5, and output from the digital output terminal 2. The PCM signal input from the digital input terminal 4 is processed as an 8kHz PAM (Pulse) by the decoder 6.
Amplitude Modulation) wave is output from the analog output terminal 3. Encoder 5 and decoder 6
A reference voltage used for this is supplied from terminal 9. Since the reference voltage applied from the terminal 9 can be easily driven with low impedance, it is considered that the crosstalk characteristics will not usually deteriorate even if it is used in common for the encoder 5 and the decoder 6.

In the CODEC of the type shown in FIG. 1, since the reference voltage is supplied from the terminal 9, a dedicated terminal for inputting the reference voltage is required, and an external component is required as a reference voltage generating circuit. Therefore, in order to reduce the number of required parts, some integrated circuits have a reference voltage generation circuit mounted on the same chip as the CODEC. On the other hand, in recent years
Since the analog-to-digital conversion accuracy required for CODECs is becoming increasingly high, high accuracy is required for the reference voltage. Additionally, CODECs have emerged in which the encoder and decoder operate with reference voltages of different magnitudes. In this way, the voltage value is 2
In order to provide a high-precision reference voltage,
If only two reference voltage generating circuits were used according to the conventional method, the circuit scale would be large, and the chip area required for integration would be large. Therefore,
It is not easy to mount a CODEC and two reference voltage generation circuits on one chip to form a monolithic integrated circuit. Even if this monolithic integrated circuit were to be realized, it would be expensive.

(Objective of the Invention) An object of the present invention is to provide a DC voltage generation circuit which generates two highly accurate DC voltages having different sizes and which requires a small circuit scale.

(Structure of the Invention) A DC voltage generation circuit according to the present invention includes a power supply circuit that outputs a stable first DC voltage, and a DC voltage generation circuit that outputs first and second reference voltages that are stable DC voltages. , a first DC voltage that adjusts the first DC voltage by voltage division or voltage division after amplification and outputs the first reference voltage and a second DC voltage that is equal to or proportional to the first reference voltage. a voltage adjustment circuit; and a second voltage adjustment circuit that adjusts the second DC voltage by voltage division or voltage division after amplification and outputs the second reference voltage, and the voltage adjustment circuit outputs the second reference voltage. voltage and said second
The DC voltages are configured such that an error with respect to each predetermined standard voltage is smaller than an error of the first DC voltage with respect to the predetermined standard voltage.

(Example) Next, the present invention will be explained in detail with reference to Examples.

FIG. 2 is a block diagram of a reference voltage generating circuit according to a first embodiment of the present invention. In Figure 2,
A stabilized power supply 21 (corresponding to the power supply circuit in the above-mentioned "Configuration of the Invention" section) provides a stabilized voltage 27 that is stable against voltage fluctuations and temperature fluctuations of the DC power supplied from the outside in this embodiment. First adjustment circuit 22
supply to. The first adjustment circuit 22 outputs a first reference voltage 28 to a terminal 23 and outputs a DC voltage 29 to a second adjustment circuit 25, respectively. The second adjustment circuit 25 outputs the second reference voltage 30 to the terminal 26.

This embodiment generates two reference voltages 28, 30 of different magnitudes, but has only one regulated power supply. With the conventional method, in order to obtain such two reference voltages, two stabilized power supplies and two
Two adjustment circuits were required. Therefore, in this embodiment, first, the circuit scale is reduced by one stabilized power supply, and the power consumption is reduced accordingly. Next, in this embodiment, since the first adjustment circuit 22 and the second adjustment circuit 25 are connected in series, the scale of the second adjustment circuit is larger than that of the conventional system in which the two adjustment circuits are independent from each other. becomes smaller. The reason for this will be explained in detail below.

Now, consider a reference voltage generation circuit in which the first reference voltage 28 is 2.5V±10mV and the second reference voltage 30 is 2.0V±10mV. Consider, for example, a bandgap type stabilized power supply with a stabilized voltage of 1.2V±0.3V. The scale of the adjustment circuit is determined by the number of values that the output reference voltage can take, that is, how many bits can be adjusted.If the number of bits is B, it can be evaluated using the following formula.

(Reference voltage tolerance) ・2 ^B-1 = (Stabilized voltage fluctuation width) ・(Reference voltage standard value) / Stabilized voltage standard value)…
(1) First, find the required number of bits for the conventional system in which the first adjustment circuit and the second adjustment circuit are independent. Substituting numerical values into equation (1) for the first reference voltage adjustment circuit, 20 (mV)・2 ^B-1 = 0.6 (V)・2.5 (V)/1.2 (V) …(2) ∴B≒7 ...(3), and 7-bit adjustment is required.

Using equation (1) to find the number of bits for the second reference voltage adjustment circuit, we get: 20 (mv)・2 ^B-1 = 0.6 (V)・2.0 (V)/1.2 (V) …(4) ∴B ≒7 (5), and 7-bit adjustment is still required.

Next, the required number of bits for the adjustment circuits 22 and 25 for the first embodiment of the present invention shown in FIG. 2 is determined. The first reference voltage adjustment circuit 22 requires 7 bits, which is the same as in the conventional example. Second reference voltage adjustment circuit 2
5 changes depending on the value of the second output voltage 29 of the first adjustment circuit 22. For example, the first adjustment circuit 2
The voltage value of the second output voltage 29 of 2 is the voltage value of the second output voltage 29 of the first adjustment circuit 2
2 is assumed to be 0.8 times the first output voltage 28 (first reference voltage) of No. 2. Then, the second output voltage 29 becomes 2.0V as a standard value. However, it is not always possible to obtain an accuracy of 0.8 times, and if you try to achieve 0.8 times with a dividing circuit using diffused resistors, etc.
It is possible to achieve an increase of about 0.02 times.

From this, calculate the number of bits according to formula (1): 20 (mv)・2 ^B-1 = 2.5 (V)・0.04・2.0 (V)/2.0 (V)…(6
) ∴B≒3 (7) Therefore, the adjustment circuit 25 for the second reference voltage 30 requires only a very small number of bits, and the circuit scale becomes small.

FIG. 3 is a circuit diagram of a ΔV _T type stabilized power supply that can be used as the stabilized power supply 21 of FIG. 2. The stabilized power supply in this diagram consists of two N-channel MOS transistors.
The difference between the different threshold values is extracted as the stabilizing voltage 27. MOS transistor 33 is an enhancement type, and MOS transistor 3
5 is a depletion type. MOS transistors 33 and 35 constitute a differential amplification stage together with loads 36 and 37 and current source 34. Terminal 31 represents a positive power supply terminal, and terminal 32 represents a negative power supply terminal. The amplifier 38 operates as an error amplifier and controls the gate voltage of the MOS transistor 33 to a DC stable point. Terminal 39 becomes the output terminal of the ΔV _T type reference voltage source.

FIG. 4 is a circuit diagram of a band gap type stabilized power source used as the stabilized power source 21 of FIG. The stabilized power supply in this diagram is the NPN transistor 43, 4
4. A bandgap voltage is output to a terminal 49 by resistors 45, 46, 47 and an error amplifier 48.
Terminal 41 is a positive power supply terminal, and terminal 42 is a ground potential or negative power supply terminal.

Figure 5 shows the first and second adjustment circuits 2 in Figure 2.
FIG. 2 is a circuit diagram of an adjustment circuit often used as 2, 25. In this adjustment circuit, a stabilized voltage is received at a terminal 50, and this stabilized voltage is applied to resistors 51, 52, and 5.
The voltage is divided by a resistor voltage divider circuit configured by 3 and 54. MOS transistors 55, 56 and 5
7 selects the divided voltage and takes it out to the terminal 58. The gate electrodes of these MOS transistors are connected to the control section 59. The control unit 59 is generally realized by cutting aluminum wiring using laser trimming technology, cutting necessary fuses using a fuse element made of polysilicon, or the like. From the control unit 59
Any one of MOS transistors 55, 56, and 57 is made conductive, and the divided reference voltage is output from terminal 58. However, it should be noted that the adjustment circuit shown in the figure cannot draw current from the terminal 58. When a current is output from the terminal 58, the accuracy of the voltage dividing circuit deteriorates because the current is supplied from the resistive voltage dividing circuit.

FIG. 6 is a circuit diagram showing a specific example of the first adjustment circuit 22 in FIG. 2. In this figure, the stabilized power source 21 is represented by a battery.
The stabilized voltage 27 is amplified by an amplifier 61. resistance 6
7, 68, 69 and 70 form feedback resistors, and MOS transistors 63, 64 and 65 feed back the divided voltage to the inverting input terminal of amplifier 61. First output voltage 28 is output from terminal 32 . The second output voltage 29 is obtained by dividing the voltage 28 at the terminal 32 (it can also be obtained from the node between the resistors 67 and 68, but in this case no output current can be obtained). The control section 66 has the same function as the control section 59 shown in FIG.
In the circuit of FIG. 5, an output voltage that is divided and attenuated from the stabilized voltage 27 is obtained, but in the circuit of FIG. 6, the voltage output from the terminal 32 is always a voltage obtained by amplifying the output voltage 27 of the stabilized power supply. It is. For this reason, the stabilized power supply is the ΔV _T type stabilized power supply shown in Figure 3, and when the stabilized voltage is 2.5V or more, the 6th
The adjustment circuit shown in the figure cannot be used. In this case, the fifth
It is preferred to use the circuit shown in the figure.

FIG. 7 is a block diagram of a second embodiment of the invention. In the embodiment of FIG. 7, the first output voltage 28 of the first adjustment circuit 22 in the embodiment of FIG.
The buffer amplifier 71 receives the first output voltage 28 without using it as a reference voltage, and the output terminal of the buffer amplifier 71 is connected to the terminal 7.
3 to set the first reference voltage 101, and connect the output voltage 30 of the second adjustment circuit 25 to the input terminal of the buffer amplifier 72, and connect the output terminal of the buffer amplifier 72 to the terminal 74 to set the second reference voltage 101. Voltage 102
It is as follows.

Using this second embodiment, the first reference voltage 1
01 and the second reference voltage 102 are doubly separated by the buffer amplifiers 71 and 72, so the crosstalk characteristics of the CODEC are improved. Furthermore, since the first and second reference voltages 101 and 102 can be driven with low impedance, digital noise and power supply noise are less likely to be added to the reference voltages 101 and 102, improving the AC characteristics of the CODEC. Note that when the first and second buffer amplifiers 71 and 72 of the first reference voltage 101 and the second reference voltage 102 are connected as shown in FIG. 7, the fluctuation of the stabilizing voltage appears to be equivalently large due to the input offset voltage. However, this is because the first and second adjustment circuits 22, 25
It is sufficient to include this in the estimation of the adjustment scale (increase the number of bits of adjustment circuits 22 and 25 by about 1 bit).

FIG. 8 is a block diagram of a third embodiment of the present invention. FIG. 8 shows that in the embodiment of FIG.
This embodiment is used when the first output voltage 28 and the second output voltage 29 of the adjustment circuit 22 are the same. Therefore, the output voltage of the first adjustment circuit 22 is set as the common output 81. The common output 81 is connected to the input terminal of the buffer amplifier 71 and also to the second adjustment circuit 25 . The output voltage 30 of the second adjustment circuit 25 is connected to the input terminal of the buffer amplifier 72 .

The third embodiment of the present invention shown in FIG. 8 is suitable when the second reference voltage is lower than the first reference voltage. In the embodiment shown in FIG. 8 (the same applies to the embodiment shown in FIG. 7), the second adjustment circuit 25 can be easily realized using a resistor voltage divider circuit as shown in FIG. It is possible to eliminate the need to take out the current output in the equivalent circuit of FIG. Similar to the second embodiment of the present invention shown in FIG.
Since the reference voltage 101 and the second reference voltage 102 are doubly separated, this is effective in improving the crosstalk characteristics of the CODEC. Furthermore, similar to the second embodiment of the present invention shown in FIG. 7, improvement in AC characteristics due to low impedance driving can be expected.

In addition, although the embodiments so far have been explained using the first reference voltage and the second reference voltage, the effects of the present invention do not change whether the first reference voltage or the second reference voltage is used in the encoder. , when the first reference voltage is used in the encoder, the second reference voltage is used in the decoder. Furthermore, when the second reference voltage is used in the encoder, the first reference voltage is used in the decoder.

(Effects of the Invention) As explained in detail above, according to the present invention,
It is possible to provide a DC voltage generation circuit which generates two highly accurate DC voltages having different magnitudes and which requires a small circuit scale.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional CODEC, Fig. 2 is a block diagram of a first embodiment of the present invention, Fig. 3 is an equivalent circuit diagram of a ΔV _T type regulated power supply used in an embodiment of the present invention, and Fig. FIG. 4 is an equivalent circuit diagram of a bandgap type regulated power supply used in an embodiment of the present invention, FIGS. FIG. 8 is a block diagram of a third embodiment of the present invention. 1... Analog input terminal, 2... Digital output terminal, 3... Analog output terminal, 4... Digital input terminal, 9, 23, 26, 31, 32, 39,
73, 74... terminal, 33, 35, 55, 56,
57, 63, 64, 65...MOS transistor,
34... Current source, 36, 37... Load, 38, 4
8...Error amplifier, 43, 44...NPN transistor, 59, 66...Control unit, 61...Amplifier, 71, 72...Buffer amplifier.

Claims (1)

[Claims] 1. A DC voltage generation circuit that outputs first and second reference voltages that are stable DC voltages, comprising: a power supply circuit that outputs a stable first DC voltage;
A first voltage that adjusts the first DC voltage by voltage division or voltage division after amplification and outputs the first reference voltage and a second DC voltage that is equal to or proportional to the first reference voltage. an adjustment circuit; and a second voltage adjustment circuit that adjusts the second DC voltage by voltage division or voltage division after amplification and outputs the second reference voltage, and the voltage adjustment circuit outputs the second reference voltage. and a DC voltage generating circuit, wherein an error of each of the second DC voltages with respect to a predetermined standard voltage is smaller than an error of the first DC voltage with respect to the predetermined standard voltage. 2. The power supply circuit has a first threshold voltage.
and a second MOS transistor having a second threshold voltage are provided in a differential input stage, and the difference between the first and second threshold voltages is set as a first DC voltage. 2. The DC voltage generating circuit according to claim 1, wherein the DC voltage generating circuit is a threshold voltage difference type stabilized power supply circuit. 3. The DC voltage generation circuit according to claim 1, wherein the power supply circuit is a bandgap type stabilized power supply circuit that utilizes a bandgap voltage of a bipolar transistor. 4. The DC voltage generation circuit according to claim 1, wherein the first and second reference voltages are outputted via first and second buffer amplifiers, respectively.