JPH0347615B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides, in a digital communication system,
This invention relates to a clock supply system for supplying predetermined clock pulses to each device from a duplicated clock source.

First, the conventional method will be explained with reference to the drawings.

FIG. 1 is a system configuration diagram of an example of a conventional clock supply system.

Here, 1 is a clock pulse supply device, 1-
1 and 1-2 are the duplicated clock pulse generation parts, 1-3 and 1-4 are the same frame pulse supply parts, 1-5A and 1-5B are the same clock route switching parts, 2A and 2B. is the clock pulse supply path,
3A and 3B are clock pulse receiving devices.

The clock pulse receiving devices 3A and 3B are duplexed, receive clock pulses from the same clock route, and distribute the clock pulses to each device in the system.

Therefore, the clock route switching section 1-5A,
1-5B and clock pulse supply paths 2A, 2B
In response to this, a duplex system is also provided.

In the clock pulse supply device 1, the clock pulse generators 1-1 and 1-2 each have the following:
A clock pulse is generated and inputted to the corresponding frame pulse supply section 1-3, 1-4.

Frame pulse supply units 1-3 and 1-4 each receive the clock pulse and send it as is to the corresponding clock routes CLK0 and CLK1, and also divide the frequency to a desired value based on the clock pulse and frame it. Create and send out pulses.

The clock route switching parts 1-5A, 1-5B are
Respectively, the clock route CLK0, determined or instructed by others in advance, or determined by yourself.
The same clock pulse and frame pulse are selected from CLK1 and sent to clock pulse receivers 3A and 3B via clock pulse supply paths 2A and 2B.

In such a conventional system, for example, when clock supply (clock pulse, frame pulse supply) is performed by clock route CLK0, the clock supply is changed to clock route CLK1 due to some reason (clock disconnection, etc.). When switched, the clock pulse generator 1-1, 1
-2 and frame pulse supply section 1-3, 1-4
Since these are asynchronous, when they are switched, (1) the synchronization between the devices receiving clock pulses and frame pulses is lost;

(2) Digital data slips by several frames.

This problem arises.

In the case of voice communication, this problem causes noise or interruption of the voice, but it usually only occurs for a short time during switching, so it does not significantly affect the intelligibility of the entire call.

However, in the case of data communication, data loss or errors may occur, and these
This is a fatal flaw. Usually, in a data communication system, the frame pulse supply units are often dispersed at several locations or more, and there is a problem in that the occurrence of data omissions and errors is unavoidable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock supply method that eliminates the above-mentioned drawbacks of the prior art, centrally manages clock pulses and frame pulse synchronization, and provides stable clock supply even when switching clock routes. be.

The features of the present invention are that each duplicated clock pulse generation section and each frame pulse supply section are connected in a master-slave format so that they are always synchronized, and that a phase synchronization circuit is added to the clock pulse supply path. This provides a clock supply system that is capable of absorbing jitter generated in the clock pulse supply path as well as jitter generated at the time of clock route switching.

Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a system configuration diagram of an embodiment of the clock supply system according to the present invention, and FIG. 3 is a block diagram of its main parts.

In FIG. 2, 10 is a clock pulse supply device;
11 and 12 are the duplicated clock pulse generation parts; 13 and 14 are the same frame pulse supply parts; 15A and 15B are the same clock route switching parts; 20A and 20B are the clock pulse supply paths;
30A, 30B are clock pulse receiving devices, 4
0A and 40B are phase locked circuits.

In FIG. 3, 11a and 12a are frequency division/phase comparators of the clock pulse generation units 11 and 12;
1b and 12b are the same up-down counters, 11
c, 12c are the same processors, 11d, 12d
is the same digital/analog converter, 11
e, 12e are the same voltage controlled crystal oscillators; 13a,
14a is a clock disconnection monitoring circuit for the frame pulse supply units 13 and 14; 13b and 14b are for common use;
The preliminary decision circuits 13c and 14c are the same selectors;
13d and 14d are the same counters.

First, an outline of the system of this embodiment will be explained based on FIG.

The generation and supply of clock pulses and frame pulses in the clock pulse generators 11, 12 and the frame pulse suppliers 13, 14 are the same as in the conventional example shown in FIG.

In addition, clock pulse receiving devices 30A and 30B
The circuits are also duplicated, receive clock supplies (clock pulses and frame pulses) from the same clock route, and distribute clocks to each device in the system.

Therefore, the clock route switching section 15A,1
5B, clock pulse supply paths 20A, 20B, and phase synchronization circuits 40A, 40B are also duplicated accordingly.

Note that these may not necessarily be duplicated, but in that case, there will be only one system, for example, the clock route switching section 15A, the clock pulse supply path 20A, the phase synchronization circuit 40A, and the clock pulse receiving device 30A.

Now, the clock pulse generators 11 and 12 and the frame pulse suppliers 13 and 14 are in a master-slave format, so that one of them is on the master side and the other is on the slave side so that they are always synchronized with the master side. Assume that it is connected.

That is, when clock route CLK0 is selected as the master side by clock route switching units 15A and 15B, clock pulses and frame pulses related to clock route CLK1 are transmitted to clock pulse generators 11 and 12 and frame pulse supply units 13 and 14, respectively. Due to the master-slave type synchronization operation between the two, slave synchronization is always performed with the clock pulses and frame pulses from the clock pulse generating section 11 and the frame pulse supplying section 13.

Therefore, even if the clock route switching units 15A and 15B switch from the clock route CLK0 to the clock route CLK1 due to some reason (for example, a clock disconnection of the clock route CLK0), no jitter due to out-of-synchronization will occur. There is some switching jitter, but this is usually small.

Moreover, the switching jitter of the clock pulses and frame pulses of the clock route CLK1 after switching is absorbed by the phase synchronization circuits 40A and 40B, and the clock pulses and frame pulses of the clock route CLK1 are supplied as normal to the clock pulse receiving circuits 30A and 30B.

Even if the cross route switching is performed in this way,
Each device receiving this clock supply can continue to operate normally without causing malfunctions such as frame slips or interruptions.

When the clock route is switched, for example, the clock route CLK1 side becomes the master side and the clock route CLK0 side becomes the slave side, and a master-slave type synchronization operation is performed.

Note that the phase locked circuits 40A and 40B can be configured using, for example, a phase locked loop circuit, and the clock pulse supply paths 20A and 2
It can also absorb jitter caused by 0B,
Furthermore, if the short-term stability is guaranteed, there is no practical problem even if the long-term stability is around 10 ^-4 .

Further, if the jitter caused by the clock pulse supply paths 20A and 20B is small enough to cause no practical problem, it may be added to the clock pulse supply device 10 side.

Next, based on FIG.
The master-slave type synchronization operation between the 14 devices will be explained.

First, in the clock pulse generating sections 11 and 12, the outputs (clock pulses) of the voltage controlled crystal oscillators 11e and 12e are sent to the frame pulse supply sections 13 and 14, respectively, and are fed back to the frequency division/phase comparators 11a and 12a. Here, the phases of the two are compared, and the phase difference data is sent to the up-down counters 11b and 12b.
It is counted and input to processors 11c and 12c.

The processors 11c and 12c each identify which one is the master side and which is the slave side by means of interlacing connections between them.

Now, if the processor 11c is the master side, it ignores the data input from the up-down counter 11b and independently sends information to the digital-to-analog converter 11d based on pre-stored data. , which controls the oscillation frequency of the voltage controlled crystal oscillator 11e to determine the output clock pulse.

On the other hand, the processor 12c always makes the clock pulse on the master side correct, and matches the clock pulse on its own system to the master side.

That is, the accumulator ACC of the processor 12c accumulates the phase difference data from the up-down counter 12b, and only the low-frequency components of the processing result are input to the digital/analog converter 12d via the digital filter DF. , the voltage controlled crystal oscillator 12e can be controlled by its output, and its output clock pulses can be synchronized with those on the master side.

The above operation is the same even when the master side and slave side are reversed, and the output clock pulses of the clock pulse generators 11 and 12 can always be synchronized.

Next, in the frame pulse supply units 13 and 14, according to instructions from the processors 11c and 12c to the regular/preliminary determination circuits 13b and 14b,
It is assumed that the frame pulse supply section 13 is on the master side.

That is, the regular/preliminary decision circuits 13b, 14b
The selectors 13c and 14c are made to select the output clock pulse of the clock pulse generator 11, respectively.

Therefore, the outputs of selectors 13c and 14c are output directly to clock routes CLK0 and CLK0, respectively.
At the same time as the clock pulse CP of CLK1, it is input to the clock input terminal CK of counters 13d and 14d, and every time a predetermined number of counts is performed, an output is sent out (divided) and routed to the clock.
Let it be the clock pulse FP of CLK0 and CLK1.

At this time, the counter 14d is reset by inputting the output (frame pulse FP) of the counter 13d to its reset input terminal CK, so that the frame pulse FP (clock route CLK1) of the frame pulse supply section 14 is reset to the clock route CLK0.
It will completely follow and synchronize with the side.

The above operation is the same even if the master side and slave side are reversed.

Note that the clock disconnection monitoring circuits 13a and 14a are
The clock pulses from the clock pulse generators 11 and 12 are constantly monitored, respectively, and when a clock disconnection on the master side is detected, information to that effect is immediately sent to the regular/preliminary decision circuits 13b and 14b, which are then sent to the selectors 13c and 14b. 14c is performed to select the slave side clock pulse.

In the above embodiment, the processors 11c and 12
Although the main operations of the circuit c have been explained as being based on hardware configurations such as the accumulator ACC and the digital filter DF, the present invention is not limited thereto.

That is, it is clear that the processors 11c and 12c can be of the storage program control type, and the above-mentioned predetermined functions can be realized by software processing. It is possible to make the system more economical and improve reliability by using the computer.

As described above in detail, according to the present invention, even when clock routes are switched from duplicated clock sources, a stable clock supply can be provided at all times, and jitter in the clock pulse supply path can be prevented. The present invention is capable of accurately supplying clocks by absorbing the clock signals.Specific effects of the present invention will be listed below.

(1) Since the synchronization of clock pulses and frame pulses can be centrally managed, the reliability of the entire clock distribution system is extremely high.

(2) Failures due to clock jitter, synchronization deviations, etc. are extremely reduced, the reliability of the entire system is improved, and problems such as frame slips during system switching are eliminated. This enables a dual system clock supply system in which the master and slave can freely alternate.

(3) As the clock system and frame system are centrally managed, it is possible to retry at the same time when out-of-sync, frame slip, or severe jitter is detected, thereby maintaining high reliability of the system as a whole. I can do it.

(4) Frame pulses can be handled in the same way as clock pulses, and during design, frame pulses can be used as a power source or a general-purpose signal source like clock pulses, which reduces the burden on design. Furthermore, a frame pulse supply unit for each signal handling destination is not required, and the overall system configuration is simplified.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of an example of a conventional clock supply system, FIG. 2 is a system configuration diagram of an embodiment of the clock supply system according to the present invention, and FIG. 3 is a block diagram of its main parts. be. 10 is a clock pulse supply device, 11, 12...
...Clock pulse generator, 11a, 12a... Frequency division/phase comparator, 11b, 12b... Up/down counter, 11c, 12c... Processor, 1
1d, 12d...Digital/analog converter, 11e, 12e...Voltage controlled crystal oscillator, 1
3, 14...Frame pulse supply section, 13a, 1
4a...Clock disconnection monitoring circuit, 13b, 14b...
...Common/preliminary decision circuit, 13c, 14c...Selector, 13d, 14d...Counter, 15A, 1
5B...Clock route switching section, 20A, 20B
...Clock pulse supply path, 30A, 30B...
Clock pulse receiver, 40A, 40B...phase synchronization circuit.

Claims (1)

[Scope of Claims] 1. In a clock supply system including two duplicate systems of clock pulse generation means, each clock pulse generation means has a means for comparing the phase of its own system's clock pulse with that of another system, and a means for comparing the phase of its own system's clock pulse with that of the other system's clock pulse, and (master) or slave (subordinate), and the identification result of the means,
means for accumulating phase difference data based on the comparison result of the means for comparing phases when the own system is on the slave side; means for extracting a low frequency component of the processing result; means for controlling its own oscillator, connected to the oscillation output section of the clock pulse generation means, and generated based on each clock provided in duplication corresponding to each of the clock pulse generation means. means for identifying which clock pulse generating means the clock pulse from the clock pulse generating means is output from, provided corresponding to each of the pulse generating means and the frame pulse generating means, and a frame pulse on the slave side. By resetting the counter to be created in accordance with instructions from the master side, a means for synchronizing with the master side, a means for monitoring at least an abnormality of the clock pulse on the master side, and a means for monitoring the master side are connected to the master side. A clock supply system characterized by having means for switching to a slave side clock pulse when the slave side clock pulse is abnormal. 2. The clock supply system according to claim 1, wherein an up-down counter is driven based on the phase comparison result, and the phase difference data is cumulatively processed based on the output of the counter. 3. The clock according to item 1 or 2, characterized in that a phase synchronization circuit is added to each of the clock pulse supply paths, so that the clock pulse supply path can absorb phase fluctuations that occur during clock route switching. Supply method. 4. The clock supply system according to item 1, wherein the oscillator is a voltage controlled oscillator.