JPH0347769B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bias control circuit for a push-pull power amplifier.

Conventionally, in class AB and class B push-pull power amplifiers, the idling current to avoid crossover distortion of the output stage transistors is set by adjusting the voltage between the bases of a pair of drive stage transistors.

An example of the configuration of such a conventional push-pull power amplifier will be explained with reference to FIG.
In FIG. 1, 2 is a pnp type pre-drive stage transistor, and an input signal terminal 1 is connected to its base. The emitter of the transistor 2 is connected to the first positive power supply terminal 3, and its collector is connected to the first positive power supply terminal 3 through a series circuit including a semi-fixed resistor 5 for bias adjustment, a plurality of diodes 6 connected in series in the same direction, and a constant current source 7. It is connected to the negative power supply terminal 4 of.
The sum of the forward voltage drops across the plurality of diodes 6 and the voltage drops across the semi-fixed resistor 5 is used as a bias voltage to drive the npn transistors 8 and pnp in the drive stage.
type transistor 9 between the bases thereof. Output transistors 10 and 11 of the same conductivity type are Darlington connected to both transistors 8 and 9 of the drive stage, respectively, and second positive and negative power supply terminals 12 and 13 are connected to npn type transistors 8 and 10.
The emitters of output transistors 10 and 11 are connected to emitter resistors 14 and 15, respectively.
An output terminal 16 is led out from the midpoint of the connection between the output terminals 15 and 15, and a load resistor 17 is connected to the output terminal 16 to form a complementary push-pull power amplifier.

In the power amplifier described above, the plurality of diodes 6 are thermally coupled to both output transistors 10 and 11 to perform temperature compensation of the bias current. In the case of amplifiers, it has been difficult to achieve perfect thermal coupling. As a result, it may take a long time for the idling current of the output transistor to reach a predetermined value after the power amplifier is turned on, and the temperature of the output transistor may change as the output of the power amplifier changes, causing the idling current to reach the specified value. The drawback was that the current fluctuated.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a bias control circuit that can eliminate fluctuations in the idling current of an output transistor without using thermal coupling.

Hereinafter, an embodiment of the bias control circuit of an amplifier according to the present invention will be described with reference to FIGS. 2 and 3. In this figure 2, the first
Portions corresponding to those in the figures are designated by the same reference numerals and redundant explanation will be omitted.

In FIG. 2, 18 indicates an idling current detection circuit, and this idling current detection circuit 18
is a sense amplifier 19 connected to each emitter of output transistors 10 and 11 of the power amplifier, respectively.
and 20, and the output terminals of both amplifiers 19 and 20 are connected to the bases of PnP transistors 24 and 25, which constitute a selection circuit 23 and whose collectors and emitters are connected in parallel, respectively.
The output of the selection circuit 23 is the output of the peak hold circuit PH.
It is supplied to the base of the npn transistor 27. 3
0 indicates a comparison circuit, and this comparison circuit 30 consists of a comparator 31 and a resistive voltage divider connected between positive and negative floating power supply terminals 32 and 33, and a reference voltage set by this voltage divider and a peak hold circuit.
Compare with the output of PH. In addition, both power supply terminals 32
and 33 and the output terminal 16 of the power amplifier are connected by large capacitors 34 and 35, respectively. Reference numeral 39 indicates a bias voltage supply circuit, and this bias voltage supply circuit 39 is connected to the comparator circuit 3.
PNP transistor 4 that divides the phase of the output of 0
0, and pnp and npn transistors 43 and 44 connected to the emitter side and collector side of the transistor 40, respectively, and the transistor 43
and 44 are connected to the bases of drive transistors 8 and 9 of the power amplifier, respectively.

Note that in FIG. 2, unsigned resistors are used for setting the operating points of individual circuits or for impedance matching between individual circuits.

Next, a more detailed explanation of this example will be given along with the operation. When a sinusoidal signal is input to the power amplifier, collector currents i ₁₀ and i ₁₁ flow through the output transistors 10 and 11 every positive and negative half cycle, respectively, and the emitter resistors 14 and 15 have their respective resistances. With the value _RE , a positive half-cycle voltage e ₁₄ =i _{10 RE} and a negative half-cycle voltage e ₁₅ =i _{11 RE} result, respectively, as shown in FIG. 3A.

Voltage e ₁₄ is at non-inverting input terminal 1 of sense amplifier 19
9a. This amplifier 19 has a high gain A, and has a Zener diode 21 as described later.
Since the amplitude is limited by
The output voltage e ₁₉ becomes a positive trapezoidal wave every half cycle, as shown in FIG. 3B.

On the other hand, the voltage e ₁₅ is supplied to the inverting input terminal 20b of the sense amplifier 20. This amplifier 20 performs amplitude limitation in the same way as the amplifier 19, and the semi-fixed resistor 20s in the negative feedback loop limits the amplitude of the amplifier 19.
It is set to have the same gain as . Therefore, the output voltage e ₂₀ of amplifier 20 becomes a half-cycle positive trapezoid as shown by the dashed line in FIG. 3B, which is the inverse of the negative trapezoid in FIG. 3B.

The inputs and outputs of both sense amplifiers 19 and 20 near the zero crossing point t ₀ where the input sinusoidal signal changes from positive to negative will now be described with reference to FIG. 3C.

The collector current i ₁₀ of the output transistor 10 of the power amplifier is finally cut off at a time t _a after t ₀ , and the collector current i ₁₁ of the transistor 11 starts flowing at a time t _b before t ₀ . At time t ₀ , the collector currents i ₁₀₀ and i ₁₁₀ have the same absolute value and opposite directions, so no output current flows through the load resistor 17 . That is, the collector currents i ₁₀₀ and i ₁₁₀ of the output transistor at time t ₀ are idling currents. Therefore, both emitter resistors 1
The voltages e ₁₄ and e ₁₅ generated at the terminals 4 and 15 change as shown by the solid lines in FIG _. . Then, the value of the input voltage of both sense amplifiers 19 and 20 at time t ₀
e ₁₄₀ and e ₁₅₀ correspond to the idling current of the output transistor.

Since the voltages e ₁₄ and e ₁₅ in the vicinity of time t ₀ are at a low level, they are both linearly amplified in both sense amplifiers 19 and 20 without being amplitude limited, and only the negative polarity voltage e ₁₅ is inverted. Therefore, the outputs of both amplifiers 19 and 20 are similar to the curve e ₁₄ shown as a solid line and the curve ₁₅ shown as a broken line in FIG. 3C, respectively.

The output voltages of both sense amplifiers 19 and 20 as described above are applied to the pnp transistors 24 and 2 of the selection circuit 23.
When supplied to the base of 5, respectively, from the tb point
In the previous period up to time point to, the output of the amplifier 20 (corresponding to the inverted voltage 15) is at a lower level than the output of the amplifier 19 (corresponding to the voltage e14), so the transistor 25 is in the on state. Also, from the point of to
In the later period up to time ta, amplifier 19
Since the output of the amplifier 20 is at a lower level than the output of the amplifier 20, the transistor 24 is turned on.
Therefore, the emitter voltage of both transistors 24 and 25, that is, the output of selection circuit 23, is
Out of the outputs 9 and 20, the lower level one is selectively followed, and reaches the maximum at time t ₀ as shown by the thick line in FIG. 3C. transistor 27, resistor 28
The peak-hold circuit PH, consisting of a capacitor 29 and a capacitor 29, holds this maximum emitter voltage level, but as mentioned above, the input voltage of both sense amplifiers 19 and 20 at time _t0 , and hence the output voltage, is the same as that of the output transistor 10. and 11, the hold voltage of the peak hold circuit PH naturally also corresponds to the idling current. Note that the time constant of the peak hold circuit PH is set to be sufficiently larger than the low cutoff frequency of the power amplifier.

The peak hold voltage _e27 corresponding to the idling current is supplied to the non-inverting input terminal 31a of the comparator 31. On the other hand, positive and negative floating power terminals 32 and 3
A resistive voltage divider consisting of a resistor 36, a variable resistor 37, and a resistor 38 is connected between 3 and 3, and the reference voltage Vr is supplied from the variable resistor 37 to the inverting input terminal 31b of the comparator, and the peak hold voltage is _e27
When e ₂₇ >Vr, the output voltage e ₃₁ of the comparator 31 becomes high, and when e ₂₇ <Vr, e ₃₁ becomes low.

The output voltage e 31 of the comparator ₃₁ is the transistor 40
However, as the voltage e ₃₁ increases, the collector current i ₄₀ of the transistor 40 decreases. Therefore, the drive level of both transistors 43 and 44 decreases, the collector current of transistors 43 and 44 becomes small, and resistors 45 and 46 connected in series between the collectors of both transistors 43 and 44 decrease.
The bias voltage Vb generated in this case also becomes smaller. This bias voltage Vb is supplied between the bases of the drive transistors 8 and 9 of the power amplifier, and the idling currents i ₁₀₀ and 100 of the output transistors 10 and 11 are
Control so that i ₁₁₀ is small.

When the output voltage of the comparator 31 becomes low, the bias voltage supply circuit 39 acts in the exact opposite manner as described above, and controls the idling currents of the transistors 10 and 11 to become large.

Note that 47 is a preamplifier for compensating for distortion of the power amplifier, and the output of this preamplifier 47 is connected to the bases of both drive transistors 8 and 9 via resistors 45 and 46 and capacitors 48 and 49. supplied to

The Zener diodes 21 and 22 connected in parallel to the negative feedback resistors of the sense amplifiers 19 and 20 will now be explained.

When an excessive input is supplied to the sense amplifier 19 or 20, the amplifier becomes saturated and even if the input level returns to a predetermined value or less, a certain amount of recovery time is required before the amplifier returns to normal operation. Therefore, immediately after an excessive input is supplied, the output of the sense amplifier is not normal, and the operation of the bias control circuit based on the abnormal output of the sense amplifier is naturally also not normal.

To prevent amplifier saturation, an amplitude limiter consisting of two diodes connected in parallel with opposite polarities is generally used, but this is ineffective for input levels below the forward direction of the diodes, and the gain of the amplifier is reduced. If it is high, it will eventually reach saturation.

If the gains of the sense amplifiers 19 and 20 as shown in FIG. 2 are A, the input voltage is Vi, the output voltage is V ₀ , and the Zener voltage of the Zener diode is Vz, then
As shown in Figure 4, if the input voltage Vi is within the range of Vz/(1-A)ViVz/(A-1), the input voltage will be linearly amplified, and if it exceeds this range, the output voltage will be is A・
In the circuit shown in Figure 2, the idling current of the output transistor is 0.1A, and the maximum peak current is 7A (100W/4Ω). If the resistance is 0.2Ω, the input level of the sense amplifier is 20mV~
It becomes 1.4V. If the gain of the sense amplifier is 40 dB and the saturation output level is 6 V, if the Zener diode is not connected, the sense amplifier will saturate if there is an input of 60 mV or more. By connecting a diode with a Zener voltage of about 4V, the output of the sense amplifier can be set to 4V for inputs exceeding about 40mV.
It can be kept in a non-saturated state at a certain level.

As described in detail above, according to the present invention, fluctuations in the idling current of the output transistor can be eliminated. Furthermore, since the desired purpose can be achieved without relying on thermal coupling, there are no restrictions regarding the arrangement of transistors, etc.

[Brief explanation of drawings]

FIG. 1 is a wiring diagram showing a configuration example of a conventional push-pull power amplifier, FIG. 2 is a wiring diagram showing an embodiment of an amplifier bias adjustment circuit according to the present invention, and FIG.
4 and 4 are diagrams for explaining the circuit shown in FIG. 2, respectively. 10 and 11 are output transistors, 19 and 2
0 is a detection amplifier, 23 is a selection circuit, PH is a peak hold circuit, and 31 is a comparator.

Claims (1)

[Claims] 1. First and second current detection means for detecting respective emitter currents of first and second output transistors constituting a push-pull power amplifier; and the first and second current detection means. a selection circuit that compares the absolute values of the detection outputs of and selects the detection output with the smaller absolute value, a peak hold circuit that holds the peak value of the output of the selection circuit, and a hold of the peak hold circuit. 1. A bias control circuit for an amplifier, comprising: bias setting means for controlling the base biases of the first and second output transistors in accordance with the base bias values of the first and second output transistors to keep the idling current constant.